OV - exec - Function .omp_outlined..20#0x437930

	Function: .omp_outlined..20#0x437930	Module: exec	Source: par_multi_interp.c:1575-1663 [...]	Coverage: 2.06%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1575 - 1663

--------------------------------------------------------------------------------

1575: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa)

[...]

1585:            if (n_fine)

1586:            {   tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); }

1587:            tmp_marker_offd = NULL;

1588:            if (num_cols_offd)

1589:            {   tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); }

1590:            for (i=0; i < n_fine; i++)

1591:            {   tmp_marker[i] = -1; }

1592:            for (i=0; i < num_cols_offd; i++)

1593:            {   tmp_marker_offd[i] = -1; }

1594:

1595:            /* Compute this thread's range of pass_length */

1596:            my_thread_num = hypre_GetThreadNum();

1597:            num_threads = hypre_NumActiveThreads();

1598:            thread_start = pass_pointer[1] + (pass_length/num_threads)*my_thread_num;

1599:            if (my_thread_num == num_threads-1)

[...]

1605:            for (i=thread_start; i < thread_stop; i++)

1606:            {

1607:              i1 = pass_array[i];

1608:              sum_C = 0;

1609:              sum_N = 0;

1610:              j_start = P_diag_start[i1];

1611:              j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1612:              for (j=j_start; j < j_end; j++)

1613:              {

1614:                 k1 = P_diag_pass[1][j];

1615:                 tmp_marker[C_array[k1]] = i1;

1616:              }

1617:              cnt = P_diag_i[i1];

1618:              for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1619:              {

1620:                 j1 = A_diag_j[j];

1621:                 if (CF_marker[j1] != -3 &&

1622:                    (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1623:                    sum_N += A_diag_data[j];

1624:                 if (j1 != -1 && tmp_marker[j1] == i1)

1625:                 {

1626:                    P_diag_data[cnt] = A_diag_data[j];

1627:                    P_diag_j[cnt++] = fine_to_coarse[j1];

1628:                    sum_C += A_diag_data[j];

1629:                 }

1630:              }

1631:              j_start = P_offd_start[i1];

1632:              j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1633:              for (j=j_start; j < j_end; j++)

1634:              {

1635:                 k1 = P_offd_pass[1][j];

1636:                 tmp_marker_offd[C_array_offd[k1]] = i1;

1637:              }

1638:              cnt_offd = P_offd_i[i1];

1639:              for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1640:              {

1641:                 if (col_offd_S_to_A)

1642:                     j1 = map_A_to_S[A_offd_j[j]];

1643:                 else

1644:                     j1 = A_offd_j[j];

1645:                 if (CF_marker_offd[j1] != -3 &&

1646:                   (num_functions == 1 || dof_func[i1] == dof_func_offd[j1]))

1647:                     sum_N += A_offd_data[j];

1648:                 if (j1 != -1 && tmp_marker_offd[j1] == i1)

1649:                 {

1650:                    P_offd_data[cnt_offd] = A_offd_data[j];

1651:                    P_offd_j[cnt_offd++] = map_S_to_new[j1];

1652:                    sum_C += A_offd_data[j];

1653:                 }

1654:              }

1655:              diagonal = A_diag_data[A_diag_i[i1]];

1656:              if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1657:              for (j=P_diag_i[i1]; j < cnt; j++)

1658:                 P_diag_data[j] *= alfa;

1659:              for (j=P_offd_i[i1]; j < cnt_offd; j++)

1660:                 P_offd_data[j] *= alfa;

1661:           }

1662:           hypre_TFree(tmp_marker);

1663:           hypre_TFree(tmp_marker_offd);

0x437930 SUB	SP, SP, #304

0x437934 STP	X29, X30, [SP, #208]

0x437938 STP	X28, X27, [SP, #224]

0x43793c STP	X26, X25, [SP, #240]

0x437940 STP	X24, X23, [SP, #256]

0x437944 STP	X22, X21, [SP, #272]

0x437948 STP	X20, X19, [SP, #288]

0x43794c ADD	X29, SP, #208

0x437950 LDR	X8, [X29, #296]

0x437954 STP	X7, X6, [X29, #992]

0x437958 STUR	X4, [X29, #432]

0x43795c LDR	X0, [X2]

0x437960 ORR	X24, XZR, X5

0x437964 ORR	X25, XZR, X3

0x437968 ORR	X26, XZR, X2

0x43796c STR	X8, [SP, #88]

0x437970 LDR	X8, [X29, #288]

0x437974 STR	X8, [SP, #80]

0x437978 LDR	X8, [X29, #280]

0x43797c STUR	X8, [X29, #416]

0x437980 LDR	X8, [X29, #272]

0x437984 STR	X8, [SP, #72]

0x437988 LDR	X8, [X29, #264]

0x43798c STR	X8, [SP, #64]

0x437990 LDP	X8, X22, [X29, #248]

0x437994 STR	X8, [SP, #56]

0x437998 LDR	X8, [X29, #240]

0x43799c STR	X8, [SP, #48]

0x4379a0 LDP	X9, X28, [X29, #224]

0x4379a4 LDR	X8, [X29, #216]

0x4379a8 STP	X8, X9, [X29, #960]

0x4379ac LDP	X9, X8, [X29, #200]

0x4379b0 STUR	X8, [X29, #440]

0x4379b4 LDR	X8, [X29, #192]

0x4379b8 STP	X9, X8, [X29, #976]

0x4379bc LDR	X8, [X29, #184]

0x4379c0 STR	X8, [SP, #40]

0x4379c4 LDR	X8, [X29, #176]

0x4379c8 STR	X8, [SP, #32]

0x4379cc LDR	X8, [X29, #168]

0x4379d0 STR	X8, [SP, #104]

0x4379d4 LDR	X8, [X29, #160]

0x4379d8 STR	X8, [SP, #96]

0x4379dc LDP	X23, X8, [X29, #144]

0x4379e0 STUR	X8, [X29, #496]

0x4379e4 LDR	X8, [X29, #136]

0x4379e8 STUR	X8, [X29, #424]

0x4379ec LDR	X8, [X29, #128]

0x4379f0 STR	X8, [SP, #16]

0x4379f4 LDR	X8, [X29, #120]

0x4379f8 STR	X8, [SP, #8]

0x4379fc LDR	X8, [X29, #112]

0x437a00 STR	X8, [SP]

0x437a04 LDP	X21, X27, [X29, #96]

0x437a08 CBZ	X0, 437a3c

0x437a0c MOVZ	W1, #8

0x437a10 BL	4ae430

0x437a14 ORR	X19, XZR, X0

0x437a18 LDR	X0, [X25]

0x437a1c CBZ	X0, 437a48

0x437a20 MOVZ	W1, #8

0x437a24 BL	4ae430

0x437a28 ORR	X20, XZR, X0

0x437a2c LDR	X8, [X26]

0x437a30 CMP	X8, #1

0x437a34 B.GE	437a58

0x437a38 B	437a74

0x437a3c ORR	X19, XZR, XZR

0x437a40 LDR	X0, [X25]

0x437a44 CBNZ	X0, 437a20

0x437a48 ORR	X20, XZR, XZR

0x437a4c LDR	X8, [X26]

0x437a50 CMP	X8, #1

0x437a54 B.LT	437a74

0x437a58 ORR	X8, XZR, XZR

0x437a5c MOVN	X9, #0

(1211) 0x437a60 STR	X9, [X19, X8,LSL #3]

(1211) 0x437a64 ADD	X8, X8, #1

(1211) 0x437a68 LDR	X10, [X26]

(1211) 0x437a6c CMP	X8, X10

(1211) 0x437a70 B.LT	437a60

0x437a74 LDR	X8, [X25]

0x437a78 CMP	X8, #1

0x437a7c B.LT	437a9c

0x437a80 ORR	X8, XZR, XZR

0x437a84 MOVN	X9, #0

(1212) 0x437a88 STR	X9, [X20, X8,LSL #3]

(1212) 0x437a8c ADD	X8, X8, #1

(1212) 0x437a90 LDR	X10, [X25]

(1212) 0x437a94 CMP	X8, X10

(1212) 0x437a98 B.LT	437a88

0x437a9c BL	4b05e0

0x437aa0 ORR	X25, XZR, X0

0x437aa4 BL	4b05c0

0x437aa8 LDR	X9, [X24]

0x437aac SUB	X11, X0, #1

0x437ab0 CMP	X25, X11

0x437ab4 SDIV	X10, X9, X0

0x437ab8 MADD	X8, X10, X25, XZR

0x437abc ADD	X10, X10, X8

0x437ac0 CSEL	X9, X9, X10, #0

0x437ac4 CMP	X8, X9

0x437ac8 B.GE	4380ac

0x437acc LDUR	X10, [X29, #432]

0x437ad0 LDR	X17, [X21]

0x437ad4 LDR	X4, [X28]

0x437ad8 CNTW	X25, ALL

0x437adc PTRUE	P0.D, ALL

0x437ae0 LDR	X5, [X22]

0x437ae4 LDR	X10, [X10]

0x437ae8 LDR	X11, [X10, #8]

0x437aec LDUR	X10, [X29, #488]

0x437af0 LDR	X10, [X10]

0x437af4 ADD	X0, X8, X11

0x437af8 ADD	X9, X9, X11

0x437afc STUR	X10, [X29, #488]

0x437b00 LDUR	X10, [X29, #480]

0x437b04 LDR	X10, [X10]

0x437b08 STUR	X10, [X29, #480]

0x437b0c LDR	X10, [X27]

0x437b10 STR	X10, [SP, #24]

0x437b14 LDR	X10, [SP]

0x437b18 LDUR	X8, [X29, #440]

0x437b1c LDR	X12, [X10]

0x437b20 LDR	X10, [SP, #8]

0x437b24 LDR	X8, [X8]

0x437b28 LDR	X13, [X10]

0x437b2c LDR	X10, [SP, #16]

0x437b30 LDR	X14, [X10]

0x437b34 LDUR	X10, [X29, #424]

0x437b38 LDR	X15, [X10]

0x437b3c LDUR	X10, [X29, #472]

0x437b40 LDR	X11, [X10]

0x437b44 LDUR	X10, [X29, #464]

0x437b48 STP	X9, X11, [X29, #976]

0x437b4c LDR	X6, [X10]

0x437b50 STR	X8, [SP, #16]

0x437b54 LDUR	X8, [X29, #448]

0x437b58 LDR	X2, [X8]

0x437b5c LDUR	X8, [X29, #456]

0x437b60 LDR	X3, [X8]

0x437b64 LDR	X8, [SP, #96]

0x437b68 LDR	X8, [X8]

0x437b6c STUR	X8, [X29, #456]

0x437b70 LDR	X8, [SP, #104]

0x437b74 STP	X6, X17, [X29, #952]

0x437b78 LDR	X9, [X8]

0x437b7c LDUR	X8, [X29, #416]

0x437b80 LDR	X8, [X8]

0x437b84 STP	X8, X9, [X29, #936]

0x437b88 B	437b9c

  (1199) 0x437b8c LDUR	X8, [X29, #464]

  (1199) 0x437b90 ADD	X0, X0, #1

  (1199) 0x437b94 CMP	X0, X8

  (1199) 0x437b98 B.GE	4380ac

  (1199) 0x437b9c LDUR	X8, [X29, #488]

  (1199) 0x437ba0 LDR	X26, [X8, X0,LSL #3]

  (1199) 0x437ba4 LDUR	X8, [X29, #480]

  (1199) 0x437ba8 ADD	X21, X26, #1

  (1199) 0x437bac LDR	X8, [X8, X26,LSL #3]

  (1199) 0x437bb0 LDR	X30, [X17, X26,LSL #3]

  (1199) 0x437bb4 LDR	X9, [X17, X21,LSL #3]

  (1199) 0x437bb8 ADD	X11, X9, X8

  (1199) 0x437bbc SUB	X11, X11, X30

  (1199) 0x437bc0 CMP	X8, X11

  (1199) 0x437bc4 B.GE	437c80

  (1199) 0x437bc8 LDR	X10, [SP, #24]

  (1199) 0x437bcc SUB	W16, W9, W30

  (1199) 0x437bd0 ANDS	X18, X16, #4160

  (1199) 0x437bd4 LDR	X11, [X10, #8]

  (1199) 0x437bd8 B.EQ	437c0c

  (1199) 0x437bdc ORR	X16, XZR, X8

    (1206) 0x437be0 LDR	X1, [X11, X16,LSL #3]

    (1206) 0x437be4 ADD	X16, X16, #1

    (1206) 0x437be8 SUBS	X18, X18, #1

    (1206) 0x437bec LDR	X1, [X12, X1,LSL #3]

    (1206) 0x437bf0 STR	X26, [X19, X1,LSL #3]

    (1206) 0x437bf4 B.NE	437be0

  (1199) 0x437bf8 ORN	X18, XZR, X30

  (1199) 0x437bfc ADD	X18, X9, X18

  (1199) 0x437c00 CMP	X18, #3

  (1199) 0x437c04 B.CS	437c20

  (1199) 0x437c08 B	437c7c

  (1199) 0x437c0c ORR	X16, XZR, X8

  (1199) 0x437c10 ORN	X18, XZR, X30

  (1199) 0x437c14 ADD	X18, X9, X18

  (1199) 0x437c18 CMP	X18, #3

  (1199) 0x437c1c B.CC	437c7c

  (1199) 0x437c20 ADD	X8, X9, X8

  (1199) 0x437c24 ADD	X9, X11, X16,LSL #3

  (1199) 0x437c28 ADD	X9, X9, #16

  (1199) 0x437c2c SUB	X8, X8, X16

  (1199) 0x437c30 SUB	X8, X8, X30

  (1199) 0x437c34 HINT	#0

  (1199) 0x437c38 HINT	#0

  (1199) 0x437c3c HINT	#0

    (1205) 0x437c40 LDUR	X11, [X9, #496]

    (1205) 0x437c44 SUBS	X8, X8, #4

    (1205) 0x437c48 LDR	X11, [X12, X11,LSL #3]

    (1205) 0x437c4c STR	X26, [X19, X11,LSL #3]

    (1205) 0x437c50 LDUR	X11, [X9, #504]

    (1205) 0x437c54 LDR	X11, [X12, X11,LSL #3]

    (1205) 0x437c58 STR	X26, [X19, X11,LSL #3]

    (1205) 0x437c5c LDR	X11, [X9]

    (1205) 0x437c60 LDR	X11, [X12, X11,LSL #3]

    (1205) 0x437c64 STR	X26, [X19, X11,LSL #3]

    (1205) 0x437c68 LDR	X11, [X9, #8]

    (1205) 0x437c6c ADD	X9, X9, #32

    (1205) 0x437c70 LDR	X11, [X12, X11,LSL #3]

    (1205) 0x437c74 STR	X26, [X19, X11,LSL #3]

    (1205) 0x437c78 B.NE	437c40

  (1199) 0x437c7c LDR	X30, [X17, X26,LSL #3]

  (1199) 0x437c80 LDR	X8, [X13, X26,LSL #3]

  (1199) 0x437c84 LDR	X16, [X13, X21,LSL #3]

  (1199) 0x437c88 MOVI	D2, #0

  (1199) 0x437c8c ADD	X8, X8, #1

  (1199) 0x437c90 CMP	X8, X16

  (1199) 0x437c94 B.GE	437d44

  (1199) 0x437c98 LDR	X10, [SP, #96]

  (1199) 0x437c9c LDUR	X9, [X29, #496]

  (1199) 0x437ca0 MOVI	D1, #0

  (1199) 0x437ca4 MOVI	D2, #0

  (1199) 0x437ca8 LDR	X11, [X10]

  (1199) 0x437cac LDR	X10, [SP, #104]

  (1199) 0x437cb0 LDR	X9, [X9]

  (1199) 0x437cb4 LDR	X18, [X10]

  (1199) 0x437cb8 LDR	X10, [SP, #40]

  (1199) 0x437cbc LDR	X1, [X10]

  (1199) 0x437cc0 LDR	X10, [SP, #32]

  (1199) 0x437cc4 LDR	X7, [X10]

  (1199) 0x437cc8 B	437cd8

    (1204) 0x437ccc ADD	X8, X8, #1

    (1204) 0x437cd0 CMP	X8, X16

    (1204) 0x437cd4 B.GE	437d4c

    (1204) 0x437cd8 LDR	X22, [X14, X8,LSL #3]

    (1204) 0x437cdc LDR	X6, [X15, X22,LSL #3]

    (1204) 0x437ce0 CMN	X6, #3

    (1204) 0x437ce4 B.EQ	437d0c

    (1204) 0x437ce8 LDR	X6, [X23]

    (1204) 0x437cec CMP	X6, #1

    (1204) 0x437cf0 B.EQ	437d04

    (1204) 0x437cf4 LDR	X6, [X9, X26,LSL #3]

    (1204) 0x437cf8 LDR	X24, [X9, X22,LSL #3]

    (1204) 0x437cfc CMP	X6, X24

    (1204) 0x437d00 B.NE	437d0c

    (1204) 0x437d04 LDR	D3, [X11, X8,LSL #3]

    (1204) 0x437d08 FADD	D1, D1, D3

    (1204) 0x437d0c CMN	X22, #1

    (1204) 0x437d10 B.EQ	437ccc

    (1204) 0x437d14 LDR	X6, [X19, X22,LSL #3]

    (1204) 0x437d18 CMP	X6, X26

    (1204) 0x437d1c B.NE	437ccc

    (1204) 0x437d20 LDR	D3, [X11, X8,LSL #3]

    (1204) 0x437d24 LDR	X16, [X1, X22,LSL #3]

    (1204) 0x437d28 STR	X16, [X7, X30,LSL #3]

    (1204) 0x437d2c LDR	X16, [X13, X21,LSL #3]

    (1204) 0x437d30 STR	D3, [X18, X30,LSL #3]

    (1204) 0x437d34 ADD	X30, X30, #1

    (1204) 0x437d38 LDR	D3, [X11, X8,LSL #3]

    (1204) 0x437d3c FADD	D2, D2, D3

    (1204) 0x437d40 B	437ccc

  (1199) 0x437d44 MOVI	D1, #0

  (1199) 0x437d48 B	437d50

  (1199) 0x437d4c LDP	X6, X17, [X29, #952]

  (1199) 0x437d50 LDUR	X8, [X29, #472]

  (1199) 0x437d54 LDR	X9, [X6, X21,LSL #3]

  (1199) 0x437d58 LDR	X27, [X6, X26,LSL #3]

  (1199) 0x437d5c LDR	X8, [X8, X26,LSL #3]

  (1199) 0x437d60 ADD	X11, X9, X8

  (1199) 0x437d64 SUB	X11, X11, X27

  (1199) 0x437d68 CMP	X8, X11

  (1199) 0x437d6c B.LT	437ee0

  (1199) 0x437d70 LDR	X28, [X3, X26,LSL #3]

  (1199) 0x437d74 LDR	X22, [X3, X21,LSL #3]

  (1199) 0x437d78 CMP	X28, X22

  (1199) 0x437d7c B.LT	437fb0

  (1199) 0x437d80 LDR	X8, [X13, X26,LSL #3]

  (1199) 0x437d84 LDUR	X9, [X29, #456]

  (1199) 0x437d88 LDR	D3, [X9, X8,LSL #3]

  (1199) 0x437d8c FMUL	D2, D2, D3

  (1199) 0x437d90 FCMP	D2, #0

  (1199) 0x437d94 B.EQ	437da0

  (1200) 0x437d98 FNEG	D0, D1

  (1200) 0x437d9c FDIV	D0, D0, D2

  (1199) 0x437da0 LDR	X18, [X17, X26,LSL #3]

  (1199) 0x437da4 SUBS	X11, X30, X18

  (1199) 0x437da8 B.LE	437e34

  (1199) 0x437dac ORR	X8, XZR, X18

  (1199) 0x437db0 CMP	X11, X25

  (1199) 0x437db4 B.CC	437e0c

  (1199) 0x437db8 UDIV	X8, X11, X25

  (1199) 0x437dbc LDUR	X1, [X29, #432]

  (1199) 0x437dc0 UBFM	X10, X18, #61, #60

  (1199) 0x437dc4 ORR	X9, XZR, XZR

  (1199) 0x437dc8 DUP	Z1.D, Z0.D[0]

  (1199) 0x437dcc MADD	X16, X8, X25, XZR

  (1199) 0x437dd0 ADD	X8, X18, X16

  (1199) 0x437dd4 ADD	X18, X1, X10

  (1199) 0x437dd8 ADDVL	X10, X10, #1

  (1199) 0x437ddc SUB	X11, X11, X16

  (1199) 0x437de0 ADD	X1, X1, X10

    (1210) 0x437de4 LD1D	{Z2.D}, P0/Z, [X18, X9,LSL #3]

    (1210) 0x437de8 LD1D	{Z3.D}, P0/Z, [X1, X9,LSL #3]

    (1210) 0x437dec FMUL	Z2.D, Z1.D, Z2.D

    (1210) 0x437df0 FMUL	Z3.D, Z1.D, Z3.D

    (1210) 0x437df4 ST1D	{Z2.D}, P0, [X18, X9,LSL #3]

    (1210) 0x437df8 ST1D	{Z3.D}, P0, [X1, X9,LSL #3]

    (1210) 0x437dfc ADD	X9, X9, X25

    (1210) 0x437e00 CMP	X16, X9

    (1210) 0x437e04 B.NE	437de4

  (1199) 0x437e08 CBZ	X11, 437e34

  (1199) 0x437e0c LDUR	X10, [X29, #432]

  (1199) 0x437e10 SUB	X9, X30, X8

  (1199) 0x437e14 ADD	X8, X10, X8,LSL #3

  (1199) 0x437e18 HINT	#0

  (1199) 0x437e1c HINT	#0

    (1209) 0x437e20 LDR	D1, [X8]

    (1209) 0x437e24 SUBS	X9, X9, #1

    (1209) 0x437e28 FMUL	D1, D0, D1

    (1209) 0x437e2c STR	D1, [X8], #8

    (1209) 0x437e30 B.NE	437e20

  (1199) 0x437e34 LDR	X18, [X6, X26,LSL #3]

  (1199) 0x437e38 SUBS	X11, X27, X18

  (1199) 0x437e3c B.LE	437b8c

  (1199) 0x437e40 ORR	X8, XZR, X18

  (1199) 0x437e44 CMP	X11, X25

  (1199) 0x437e48 B.CC	437ea8

  (1199) 0x437e4c UDIV	X8, X11, X25

  (1199) 0x437e50 LDUR	X1, [X29, #424]

  (1199) 0x437e54 UBFM	X10, X18, #61, #60

  (1199) 0x437e58 ORR	X9, XZR, XZR

  (1199) 0x437e5c DUP	Z1.D, Z0.D[0]

  (1199) 0x437e60 MADD	X16, X8, X25, XZR

  (1199) 0x437e64 ADD	X8, X18, X16

  (1199) 0x437e68 ADD	X18, X1, X10

  (1199) 0x437e6c ADDVL	X10, X10, #1

  (1199) 0x437e70 SUB	X11, X11, X16

  (1199) 0x437e74 ADD	X1, X1, X10

  (1199) 0x437e78 HINT	#0

  (1199) 0x437e7c HINT	#0

    (1208) 0x437e80 LD1D	{Z2.D}, P0/Z, [X18, X9,LSL #3]

    (1208) 0x437e84 LD1D	{Z3.D}, P0/Z, [X1, X9,LSL #3]

    (1208) 0x437e88 FMUL	Z2.D, Z1.D, Z2.D

    (1208) 0x437e8c FMUL	Z3.D, Z1.D, Z3.D

    (1208) 0x437e90 ST1D	{Z2.D}, P0, [X18, X9,LSL #3]

    (1208) 0x437e94 ST1D	{Z3.D}, P0, [X1, X9,LSL #3]

    (1208) 0x437e98 ADD	X9, X9, X25

    (1208) 0x437e9c CMP	X16, X9

    (1208) 0x437ea0 B.NE	437e80

  (1199) 0x437ea4 CBZ	X11, 437b8c

  (1199) 0x437ea8 LDUR	X10, [X29, #424]

  (1199) 0x437eac SUB	X9, X27, X8

  (1199) 0x437eb0 ADD	X8, X10, X8,LSL #3

  (1199) 0x437eb4 HINT	#0

  (1199) 0x437eb8 HINT	#0

  (1199) 0x437ebc HINT	#0

    (1207) 0x437ec0 LDR	D1, [X8]

    (1207) 0x437ec4 SUBS	X9, X9, #1

    (1207) 0x437ec8 FMUL	D1, D0, D1

    (1207) 0x437ecc STR	D1, [X8], #8

    (1207) 0x437ed0 B.NE	437ec0

  (1199) 0x437ed4 B	437b8c

0x437ed8 HINT	#0

0x437edc HINT	#0

  (1199) 0x437ee0 LDR	X10, [SP, #16]

  (1199) 0x437ee4 SUB	W16, W9, W27

  (1199) 0x437ee8 ANDS	X18, X16, #4160

  (1199) 0x437eec LDR	X11, [X10, #8]

  (1199) 0x437ef0 B.EQ	437f2c

  (1199) 0x437ef4 ORR	X16, XZR, X8

  (1199) 0x437ef8 HINT	#0

  (1199) 0x437efc HINT	#0

    (1203) 0x437f00 LDR	X1, [X11, X16,LSL #3]

    (1203) 0x437f04 ADD	X16, X16, #1

    (1203) 0x437f08 SUBS	X18, X18, #1

    (1203) 0x437f0c LDR	X1, [X2, X1,LSL #3]

    (1203) 0x437f10 STR	X26, [X20, X1,LSL #3]

    (1203) 0x437f14 B.NE	437f00

  (1199) 0x437f18 ORN	X18, XZR, X27

  (1199) 0x437f1c ADD	X18, X9, X18

  (1199) 0x437f20 CMP	X18, #3

  (1199) 0x437f24 B.CS	437f40

  (1199) 0x437f28 B	437f9c

  (1199) 0x437f2c ORR	X16, XZR, X8

  (1199) 0x437f30 ORN	X18, XZR, X27

  (1199) 0x437f34 ADD	X18, X9, X18

  (1199) 0x437f38 CMP	X18, #3

  (1199) 0x437f3c B.CC	437f9c

  (1199) 0x437f40 ADD	X8, X9, X8

  (1199) 0x437f44 ADD	X9, X11, X16,LSL #3

  (1199) 0x437f48 ADD	X9, X9, #16

  (1199) 0x437f4c SUB	X8, X8, X16

  (1199) 0x437f50 SUB	X8, X8, X27

  (1199) 0x437f54 HINT	#0

  (1199) 0x437f58 HINT	#0

  (1199) 0x437f5c HINT	#0

    (1202) 0x437f60 LDUR	X11, [X9, #496]

    (1202) 0x437f64 SUBS	X8, X8, #4

    (1202) 0x437f68 LDR	X11, [X2, X11,LSL #3]

    (1202) 0x437f6c STR	X26, [X20, X11,LSL #3]

    (1202) 0x437f70 LDUR	X11, [X9, #504]

    (1202) 0x437f74 LDR	X11, [X2, X11,LSL #3]

    (1202) 0x437f78 STR	X26, [X20, X11,LSL #3]

    (1202) 0x437f7c LDR	X11, [X9]

    (1202) 0x437f80 LDR	X11, [X2, X11,LSL #3]

    (1202) 0x437f84 STR	X26, [X20, X11,LSL #3]

    (1202) 0x437f88 LDR	X11, [X9, #8]

    (1202) 0x437f8c ADD	X9, X9, #32

    (1202) 0x437f90 LDR	X11, [X2, X11,LSL #3]

    (1202) 0x437f94 STR	X26, [X20, X11,LSL #3]

    (1202) 0x437f98 B.NE	437f60

  (1199) 0x437f9c LDR	X27, [X6, X26,LSL #3]

  (1199) 0x437fa0 LDR	X28, [X3, X26,LSL #3]

  (1199) 0x437fa4 LDR	X22, [X3, X21,LSL #3]

  (1199) 0x437fa8 CMP	X28, X22

  (1199) 0x437fac B.GE	437d80

(1201) 0x437fb0 LDR	X8, [SP, #48]

(1201) 0x437fb4 LDR	X9, [SP, #88]

(1201) 0x437fb8 LDR	X11, [X8]

(1201) 0x437fbc LDR	X8, [SP, #56]

(1201) 0x437fc0 LDR	X9, [X9]

(1201) 0x437fc4 LDR	X18, [X8]

(1201) 0x437fc8 LDUR	X8, [X29, #496]

(1201) 0x437fcc LDR	X1, [X8]

(1201) 0x437fd0 LDR	X8, [SP, #64]

(1201) 0x437fd4 ADD	X18, X18, X28,LSL #3

(1201) 0x437fd8 LDR	X7, [X8]

(1201) 0x437fdc LDP	X8, X10, [SP, #72]

(1201) 0x437fe0 LDR	X24, [X8]

(1201) 0x437fe4 LDUR	X8, [X29, #416]

(1201) 0x437fe8 LDR	X16, [X10]

(1201) 0x437fec LDR	X8, [X8]

(1201) 0x437ff0 B	438010

0x437ff4 HINT	#0

0x437ff8 HINT	#0

0x437ffc HINT	#0

(1201) 0x438000 ADD	X28, X28, #1

(1201) 0x438004 ADD	X18, X18, #8

(1201) 0x438008 CMP	X28, X22

(1201) 0x43800c B.GE	43808c

(1201) 0x438010 ORR	X6, XZR, X18

(1201) 0x438014 CBZ	X4, 438020

(1201) 0x438018 LDR	X6, [X18]

(1201) 0x43801c ADD	X6, X11, X6,LSL #3

(1201) 0x438020 LDR	X6, [X6]

(1201) 0x438024 LDR	X10, [X5, X6,LSL #3]

(1201) 0x438028 CMN	X10, #3

(1201) 0x43802c B.EQ	438054

(1201) 0x438030 LDR	X10, [X23]

(1201) 0x438034 CMP	X10, #1

(1201) 0x438038 B.EQ	43804c

(1201) 0x43803c LDR	X10, [X1, X26,LSL #3]

(1201) 0x438040 LDR	X17, [X7, X6,LSL #3]

(1201) 0x438044 CMP	X10, X17

(1201) 0x438048 B.NE	438054

(1201) 0x43804c LDR	D3, [X24, X28,LSL #3]

(1201) 0x438050 FADD	D1, D1, D3

(1201) 0x438054 CMN	X6, #1

(1201) 0x438058 B.EQ	438000

(1201) 0x43805c LDR	X10, [X20, X6,LSL #3]

(1201) 0x438060 CMP	X10, X26

(1201) 0x438064 B.NE	438000

(1201) 0x438068 LDR	D3, [X24, X28,LSL #3]

(1201) 0x43806c LDR	X10, [X9, X6,LSL #3]

(1201) 0x438070 STR	X10, [X16, X27,LSL #3]

(1201) 0x438074 LDR	X22, [X3, X21,LSL #3]

(1201) 0x438078 STR	D3, [X8, X27,LSL #3]

(1201) 0x43807c ADD	X27, X27, #1

(1201) 0x438080 LDR	D3, [X24, X28,LSL #3]

(1201) 0x438084 FADD	D2, D2, D3

(1201) 0x438088 B	438000

(1201) 0x43808c LDP	X6, X17, [X29, #952]

(1201) 0x438090 LDR	X8, [X13, X26,LSL #3]

(1201) 0x438094 LDUR	X9, [X29, #456]

(1201) 0x438098 LDR	D3, [X9, X8,LSL #3]

(1201) 0x43809c FMUL	D2, D2, D3

(1201) 0x4380a0 FCMP	D2, #0

(1201) 0x4380a4 B.NE	437d98

(1201) 0x4380a8 B	437da0

0x4380ac ORR	X0, XZR, X19

0x4380b0 BL	4ae530

0x4380b4 ORR	X0, XZR, X20

0x4380b8 LDP	X20, X19, [SP, #288]

0x4380bc LDP	X22, X21, [SP, #272]

0x4380c0 LDP	X24, X23, [SP, #256]

0x4380c4 LDP	X26, X25, [SP, #240]

0x4380c8 LDP	X28, X27, [SP, #224]

0x4380cc LDP	X29, X30, [SP, #208]

0x4380d0 ADD	SP, SP, #304

0x4380d4 B	4ae530

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	par_multi_interp.c:1575-1663
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1575,1585-1599,1605-1663.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 34.83 to 1.50 cycles (23.22x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 27% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 34.83 to 2.50 cycles (13.93x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 640 bytes. The binary function is storing 376 bytes.

General properties

nb instructions	157
loop length	628
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

19.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	7.50	7.50	9.50	9.50	9.50	9.50	0.00	0.00	0.00	0.00	34.83	34.50	34.67	17.50	17.50
cycles	7.50	7.50	9.50	9.50	9.50	9.50	0.00	0.00	0.00	0.00	34.83	34.50	34.67	17.50	17.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	19.00
Overall L1	34.83

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 34.83 cycles. At this rate:

19% of peak load performance is reached (18.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (10.79 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 437930

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X7, X6, [X29, #992]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X4, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X24, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X22, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X9, X28, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X8, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X8, X9, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X9, X8, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X9, X8, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X23, X8, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X21, X27, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CBZ X0, 437a3c <.omp_outlined..20+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X0, 437a48 <.omp_outlined..20+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 437a58 <.omp_outlined..20+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 437a74 <.omp_outlined..20+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X0, 437a20 <.omp_outlined..20+0xf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 437a74 <.omp_outlined..20+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 437a9c <.omp_outlined..20+0x16c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b05e0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b05c0 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X11, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X25, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SDIV X10, X9, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MADD X8, X10, X25, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X10, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X9, X9, X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4380ac <.omp_outlined..20+0x77c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X10, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CNTW X25, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X5, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X10, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X8, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X10, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X10, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X10, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X9, X11, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X6, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X6, X17, [X29, #952]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X8, X9, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 437b9c <.omp_outlined..20+0x26c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae530 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X20, X19, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4ae530 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	par_multi_interp.c:1575-1663
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1575,1585-1599,1605-1663.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 27% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 34.83 to 2.50 cycles (13.93x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 640 bytes. The binary function is storing 376 bytes.

General properties

nb instructions	157
loop length	628
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

19.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	7.50	7.50	9.50	9.50	9.50	9.50	0.00	0.00	0.00	0.00	34.83	34.50	34.67	17.50	17.50
cycles	7.50	7.50	9.50	9.50	9.50	9.50	0.00	0.00	0.00	0.00	34.83	34.50	34.67	17.50	17.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	19.00
Overall L1	34.83

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 34.83 cycles. At this rate:

19% of peak load performance is reached (18.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (10.79 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 437930

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X7, X6, [X29, #992]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X4, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X24, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X22, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X9, X28, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X8, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X8, X9, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X9, X8, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X9, X8, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X23, X8, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X21, X27, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CBZ X0, 437a3c <.omp_outlined..20+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X0, 437a48 <.omp_outlined..20+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 437a58 <.omp_outlined..20+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 437a74 <.omp_outlined..20+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X0, 437a20 <.omp_outlined..20+0xf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 437a74 <.omp_outlined..20+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 437a9c <.omp_outlined..20+0x16c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b05e0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b05c0 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X11, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X25, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SDIV X10, X9, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MADD X8, X10, X25, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X10, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X9, X9, X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4380ac <.omp_outlined..20+0x77c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X10, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CNTW X25, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X5, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X10, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X8, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X10, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X10, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X10, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X9, X11, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X6, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X6, X17, [X29, #952]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X8, X9, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 437b9c <.omp_outlined..20+0x26c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae530 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X20, X19, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4ae530 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼.omp_outlined..20#0x437930–	2.06	0.78
○Loop 1211 - par_multi_interp.c:1590-1591 - exec	1.74	0.57
▼Loop 1201 - par_multi_interp.c:1598-1660 - exec–	0	0
▼Loop 1199 - par_multi_interp.c:1598-1660 - exec–	0.07	0.02
○Loop 1204 - par_multi_interp.c:1618-1628 - exec	0.24	0.08
○Loop 1206 - par_multi_interp.c:1612-1615 - exec	0.01	0.01
○Loop 1209 - par_multi_interp.c:1657-1658 - exec	0	0
○Loop 1207 - par_multi_interp.c:1659-1660 - exec	0	0
○Loop 1208 - par_multi_interp.c:1660-1660 - exec	0	0
○Loop 1210 - par_multi_interp.c:1658-1658 - exec	0	0
○Loop 1205 - par_multi_interp.c:1612-1615 - exec	0	0
○Loop 1202 - par_multi_interp.c:1633-1636 - exec	0	0
○Loop 1203 - par_multi_interp.c:1633-1636 - exec	0	0
○Loop 1200 - par_multi_interp.c:1656-1656 - exec	0	0
○Loop 1212 - par_multi_interp.c:1592-1593 - exec	0	0

Report Configuration

Code clean check

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Vectorization

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

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Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code