OV - exec - Function .omp_outlined..18#0x4a6160

	Function: .omp_outlined..18#0x4a6160	Module: exec	Source: csr_matvec.c:243-404 [...]	Coverage: 15.66%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 243 - 404

--------------------------------------------------------------------------------

243: #pragma omp parallel private(i,jj,tempx)

244: #endif

245:       {

246:       HYPRE_Int iBegin = hypre_CSRMatrixGetLoadBalancedPartitionBegin(A);

247:       HYPRE_Int iEnd = hypre_CSRMatrixGetLoadBalancedPartitionEnd(A);

248:       hypre_assert(iBegin <= iEnd);

249:       hypre_assert(iBegin >= 0 && iBegin <= num_rows);

250:       hypre_assert(iEnd >= 0 && iEnd <= num_rows);

251:

252:       if (0 == temp)

253:       {

254:          if (1 == alpha) // JSP: a common path

255:          {

256:             for (i = iBegin; i < iEnd; i++)

257:             {

258:                tempx = 0.0;

259:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

260:                {

261:                   tempx += A_data[jj] * x_data[A_j[jj]];

262:                }

263:                y_data[i] = tempx;

264:             }

265:          } // y = A*x

266:          else if (-1 == alpha)

267:          {

268:             for (i = iBegin; i < iEnd; i++)

269:             {

270:                tempx = 0.0;

271:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

272:                {

273:                   tempx -= A_data[jj] * x_data[A_j[jj]];

274:                }

275:                y_data[i] = tempx;

276:             }

277:          } // y = -A*x

278:          else

279:          {

280:             for (i = iBegin; i < iEnd; i++)

281:             {

282:                tempx = 0.0;

283:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

284:                {

285:                   tempx += A_data[jj] * x_data[A_j[jj]];

286:                }

287:                y_data[i] = alpha*tempx;

288:             }

289:          } // y = alpha*A*x

290:       } // temp == 0

291:       else if (-1 == temp) // beta == -alpha

292:       {

293:          if (1 == alpha) // JSP: a common path

294:          {

295:             for (i = iBegin; i < iEnd; i++)

296:             {

297:                tempx = -b_data[i];

298:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

299:                {

300:                   tempx += A_data[jj] * x_data[A_j[jj]];

301:                }

302:                y_data[i] = tempx;

303:             }

304:          } // y = A*x - y

305:          else if (-1 == alpha) // JSP: a common path

306:          {

307:             for (i = iBegin; i < iEnd; i++)

308:             {

309:                tempx = b_data[i];

310:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

311:                {

312:                   tempx -= A_data[jj] * x_data[A_j[jj]];

313:                }

314:                y_data[i] = tempx;

315:             }

316:          } // y = -A*x + y

317:          else

318:          {

319:             for (i = iBegin; i < iEnd; i++)

320:             {

321:                tempx = -b_data[i];

322:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

323:                {

324:                   tempx += A_data[jj] * x_data[A_j[jj]];

325:                }

326:                y_data[i] = alpha*tempx;

327:             }

328:          } // y = alpha*(A*x - y)

329:       } // temp == -1

330:       else if (1 == temp)

331:       {

332:          if (1 == alpha) // JSP: a common path

333:          {

334:             for (i = iBegin; i < iEnd; i++)

335:             {

336:                tempx = b_data[i];

337:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

338:                {

339:                   tempx += A_data[jj] * x_data[A_j[jj]];

340:                }

341:                y_data[i] = tempx;

342:             }

343:          } // y = A*x + y

344:          else if (-1 == alpha)

345:          {

346:             for (i = iBegin; i < iEnd; i++)

347:             {

348:                tempx = -b_data[i];

349:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

350:                {

351:                   tempx -= A_data[jj] * x_data[A_j[jj]];

352:                }

353:                y_data[i] = tempx;

354:             }

355:          } // y = -A*x - y

356:          else

357:          {

358:             for (i = iBegin; i < iEnd; i++)

359:             {

360:                tempx = b_data[i];

361:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

362:                {

363:                   tempx += A_data[jj] * x_data[A_j[jj]];

364:                }

365:                y_data[i] = alpha*tempx;

[...]

371:          if (1 == alpha) // JSP: a common path

372:          {

373:             for (i = iBegin; i < iEnd; i++)

374:             {

375:                tempx = b_data[i]*temp;

376:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

377:                {

378:                   tempx += A_data[jj] * x_data[A_j[jj]];

379:                }

380:                y_data[i] = tempx;

381:             }

382:          } // y = A*x + temp*y

383:          else if (-1 == alpha)

384:          {

385:             for (i = iBegin; i < iEnd; i++)

386:             {

387:                tempx = -b_data[i]*temp;

388:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

389:                {

390:                   tempx -= A_data[jj] * x_data[A_j[jj]];

391:                }

392:                y_data[i] = tempx;

393:             }

394:          } // y = -A*x - temp*y

395:          else

396:          {

397:             for (i = iBegin; i < iEnd; i++)

398:             {

399:                tempx = b_data[i]*temp;

400:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

401:                {

402:                   tempx += A_data[jj] * x_data[A_j[jj]];

403:                }

404:                y_data[i] = alpha*tempx;

0x4a6160 STP	X29, X30, [SP, #928]!

0x4a6164 STR	X27, [SP, #16]

0x4a6168 STP	X26, X25, [SP, #32]

0x4a616c STP	X24, X23, [SP, #48]

0x4a6170 STP	X22, X21, [SP, #64]

0x4a6174 STP	X20, X19, [SP, #80]

0x4a6178 ADD	X29, SP, #0

0x4a617c LDR	X0, [X2]

0x4a6180 ORR	X23, XZR, X7

0x4a6184 ORR	X24, XZR, X6

0x4a6188 ORR	X21, XZR, X5

0x4a618c ORR	X22, XZR, X4

0x4a6190 ORR	X25, XZR, X3

0x4a6194 ORR	X19, XZR, X2

0x4a6198 BL	4a4c20

0x4a619c ORR	X20, XZR, X0

0x4a61a0 LDR	X0, [X19]

0x4a61a4 BL	4a4cb0

0x4a61a8 ORR	X19, XZR, X0

0x4a61ac CMP	X20, X0

0x4a61b0 B.LE	4a61ec

0x4a61b4 ADRP	X8,

0x4a61b8 ADRP	X1,

0x4a61bc ADD	X1, X1, #1027

0x4a61c0 ADRP	X2,

0x4a61c4 ADD	X2, X2, #137

0x4a61c8 LDR	X8, [X8, #4056]

0x4a61cc LDR	X0, [X8]

0x4a61d0 BL	4ae6f0

0x4a61d4 ORR	X3, XZR, XZR

0x4a61d8 ADRP	X0,

0x4a61dc ADD	X0, X0, #1934

0x4a61e0 MOVZ	W1, #248

0x4a61e4 MOVZ	W2, #1

0x4a61e8 BL	4b0fc0

0x4a61ec TBNZ	X20, #63, 4a61fc

0x4a61f0 LDR	X8, [X25]

0x4a61f4 CMP	X20, X8

0x4a61f8 B.LE	4a6238

0x4a61fc ADRP	X8,

0x4a6200 ADRP	X1,

0x4a6204 ADD	X1, X1, #1027

0x4a6208 ADRP	X2,

0x4a620c ADD	X2, X2, #3539

0x4a6210 LDR	X8, [X8, #4056]

0x4a6214 LDR	X0, [X8]

0x4a6218 BL	4ae6f0

0x4a621c ORR	X3, XZR, XZR

0x4a6220 ADRP	X0,

0x4a6224 ADD	X0, X0, #1934

0x4a6228 MOVZ	W1, #249

0x4a622c MOVZ	W2, #1

0x4a6230 BL	4b0fc0

0x4a6234 LDR	X8, [X25]

0x4a6238 LDP	X26, X25, [X29, #104]

0x4a623c LDR	X27, [X29, #96]

0x4a6240 TBNZ	X19, #63, 4a637c

0x4a6244 CMP	X19, X8

0x4a6248 B.GT	4a637c

0x4a624c LDR	D1, [X22]

0x4a6250 FCMP	D1, #0

0x4a6254 B.NE	4a63c0

0x4a6258 LDR	D0, [X21]

0x4a625c FMOV	D1, #1.0000000

0x4a6260 FCMP	D0, D1

0x4a6264 B.NE	4a64fc

0x4a6268 CMP	X20, X19

0x4a626c B.GE	4a6ffc

0x4a6270 LDR	X8, [X24]

0x4a6274 LDR	X9, [X23]

0x4a6278 LDR	X11, [X26]

0x4a627c ADD	X13, X9, #16

0x4a6280 LDR	X10, [X27]

0x4a6284 LDR	X12, [X25]

0x4a6288 LDR	X14, [X8, X20,LSL #3]

0x4a628c ADD	X15, X11, #16

0x4a6290 B	4a62b0

0x4a6294 HINT	#0

0x4a6298 HINT	#0

0x4a629c HINT	#0

(1065) 0x4a62a0 STR	D0, [X12, X20,LSL #3]

(1065) 0x4a62a4 ORR	X20, XZR, X16

(1065) 0x4a62a8 CMP	X16, X19

(1065) 0x4a62ac B.EQ	4a6ffc

(1065) 0x4a62b0 ADD	X16, X20, #1

(1065) 0x4a62b4 ORR	X17, XZR, X14

(1065) 0x4a62b8 MOVI	D0, #0

(1065) 0x4a62bc LDR	X14, [X8, X16,LSL #3]

(1065) 0x4a62c0 CMP	X14, X17

(1065) 0x4a62c4 B.LE	4a62a0

(1065) 0x4a62c8 SUB	W18, W14, W17

(1065) 0x4a62cc MOVI	D0, #0

(1065) 0x4a62d0 ANDS	X0, X18, #4160

(1065) 0x4a62d4 B.EQ	4a6310

(1065) 0x4a62d8 ORR	X18, XZR, X17

(1065) 0x4a62dc HINT	#0

  (1067) 0x4a62e0 LDR	X1, [X11, X18,LSL #3]

  (1067) 0x4a62e4 LDR	D1, [X9, X18,LSL #3]

  (1067) 0x4a62e8 ADD	X18, X18, #1

  (1067) 0x4a62ec SUBS	X0, X0, #1

  (1067) 0x4a62f0 LDR	D2, [X10, X1,LSL #3]

  (1067) 0x4a62f4 FMADD	D0, D1, D2, D0

  (1067) 0x4a62f8 B.NE	4a62e0

(1065) 0x4a62fc ORN	X17, XZR, X17

(1065) 0x4a6300 ADD	X17, X14, X17

(1065) 0x4a6304 CMP	X17, #3

(1065) 0x4a6308 B.CC	4a62a0

(1065) 0x4a630c B	4a6324

(1065) 0x4a6310 ORR	X18, XZR, X17

(1065) 0x4a6314 ORN	X17, XZR, X17

(1065) 0x4a6318 ADD	X17, X14, X17

(1065) 0x4a631c CMP	X17, #3

(1065) 0x4a6320 B.CC	4a62a0

(1065) 0x4a6324 UBFM	X0, X18, #61, #60

(1065) 0x4a6328 SUB	X17, X14, X18

(1065) 0x4a632c ADD	X18, X13, X0

(1065) 0x4a6330 ADD	X0, X15, X0

(1065) 0x4a6334 HINT	#0

(1065) 0x4a6338 HINT	#0

(1065) 0x4a633c HINT	#0

  (1066) 0x4a6340 LDP	X1, X2, [X0, #1008]

  (1066) 0x4a6344 LDP	D2, D3, [X18, #1008]

  (1066) 0x4a6348 SUBS	X17, X17, #4

  (1066) 0x4a634c LDR	D1, [X10, X1,LSL #3]

  (1066) 0x4a6350 FMADD	D0, D2, D1, D0

  (1066) 0x4a6354 LDR	D1, [X10, X2,LSL #3]

  (1066) 0x4a6358 FMADD	D0, D3, D1, D0

  (1066) 0x4a635c LDP	X1, X2, [X0], #32

  (1066) 0x4a6360 LDR	D2, [X10, X1,LSL #3]

  (1066) 0x4a6364 LDP	D1, D3, [X18], #32

  (1066) 0x4a6368 FMADD	D0, D1, D2, D0

  (1066) 0x4a636c LDR	D1, [X10, X2,LSL #3]

  (1066) 0x4a6370 FMADD	D0, D3, D1, D0

  (1066) 0x4a6374 B.NE	4a6340

(1065) 0x4a6378 B	4a62a0

0x4a637c ADRP	X8,

0x4a6380 ADRP	X1,

0x4a6384 ADD	X1, X1, #1027

0x4a6388 ADRP	X2,

0x4a638c ADD	X2, X2, #3573

0x4a6390 LDR	X8, [X8, #4056]

0x4a6394 LDR	X0, [X8]

0x4a6398 BL	4ae6f0

0x4a639c ORR	X3, XZR, XZR

0x4a63a0 ADRP	X0,

0x4a63a4 ADD	X0, X0, #1934

0x4a63a8 MOVZ	W1, #250

0x4a63ac MOVZ	W2, #1

0x4a63b0 BL	4b0fc0

0x4a63b4 LDR	D1, [X22]

0x4a63b8 FCMP	D1, #0

0x4a63bc B.EQ	4a6258

0x4a63c0 LDR	X8, [X29, #120]

0x4a63c4 FMOV	D0, #-1.0000000

0x4a63c8 FCMP	D1, D0

0x4a63cc B.NE	4a661c

0x4a63d0 LDR	D0, [X21]

0x4a63d4 FMOV	D1, #1.0000000

0x4a63d8 FCMP	D0, D1

0x4a63dc B.NE	4a673c

0x4a63e0 CMP	X20, X19

0x4a63e4 B.GE	4a6ffc

0x4a63e8 LDR	X9, [X24]

0x4a63ec LDR	X10, [X23]

0x4a63f0 LDR	X12, [X26]

0x4a63f4 ADD	X14, X10, #16

0x4a63f8 LDR	X8, [X8]

0x4a63fc LDR	X11, [X27]

0x4a6400 LDR	X13, [X25]

0x4a6404 LDR	X16, [X9, X20,LSL #3]

0x4a6408 ADD	X15, X12, #16

0x4a640c B	4a6430

0x4a6410 HINT	#0

0x4a6414 HINT	#0

0x4a6418 HINT	#0

0x4a641c HINT	#0

(1062) 0x4a6420 STR	D0, [X13, X20,LSL #3]

(1062) 0x4a6424 ORR	X20, XZR, X17

(1062) 0x4a6428 CMP	X17, X19

(1062) 0x4a642c B.EQ	4a6ffc

(1062) 0x4a6430 LDR	D0, [X8, X20,LSL #3]

(1062) 0x4a6434 ADD	X17, X20, #1

(1062) 0x4a6438 ORR	X18, XZR, X16

(1062) 0x4a643c LDR	X16, [X9, X17,LSL #3]

(1062) 0x4a6440 CMP	X16, X18

(1062) 0x4a6444 FNEG	D0, D0

(1062) 0x4a6448 B.LE	4a6420

(1062) 0x4a644c SUB	W0, W16, W18

(1062) 0x4a6450 ANDS	X1, X0, #4160

(1062) 0x4a6454 B.EQ	4a6490

(1062) 0x4a6458 ORR	X0, XZR, X18

(1062) 0x4a645c HINT	#0

  (1064) 0x4a6460 LDR	X2, [X12, X0,LSL #3]

  (1064) 0x4a6464 LDR	D1, [X10, X0,LSL #3]

  (1064) 0x4a6468 ADD	X0, X0, #1

  (1064) 0x4a646c SUBS	X1, X1, #1

  (1064) 0x4a6470 LDR	D2, [X11, X2,LSL #3]

  (1064) 0x4a6474 FMADD	D0, D1, D2, D0

  (1064) 0x4a6478 B.NE	4a6460

(1062) 0x4a647c ORN	X18, XZR, X18

(1062) 0x4a6480 ADD	X18, X16, X18

(1062) 0x4a6484 CMP	X18, #3

(1062) 0x4a6488 B.CC	4a6420

(1062) 0x4a648c B	4a64a4

(1062) 0x4a6490 ORR	X0, XZR, X18

(1062) 0x4a6494 ORN	X18, XZR, X18

(1062) 0x4a6498 ADD	X18, X16, X18

(1062) 0x4a649c CMP	X18, #3

(1062) 0x4a64a0 B.CC	4a6420

(1062) 0x4a64a4 UBFM	X1, X0, #61, #60

(1062) 0x4a64a8 SUB	X18, X16, X0

(1062) 0x4a64ac ADD	X0, X14, X1

(1062) 0x4a64b0 ADD	X1, X15, X1

(1062) 0x4a64b4 HINT	#0

(1062) 0x4a64b8 HINT	#0

(1062) 0x4a64bc HINT	#0

  (1063) 0x4a64c0 LDP	X2, X3, [X1, #1008]

  (1063) 0x4a64c4 LDP	D2, D3, [X0, #1008]

  (1063) 0x4a64c8 SUBS	X18, X18, #4

  (1063) 0x4a64cc LDR	D1, [X11, X2,LSL #3]

  (1063) 0x4a64d0 FMADD	D0, D2, D1, D0

  (1063) 0x4a64d4 LDR	D1, [X11, X3,LSL #3]

  (1063) 0x4a64d8 FMADD	D0, D3, D1, D0

  (1063) 0x4a64dc LDP	X2, X3, [X1], #32

  (1063) 0x4a64e0 LDR	D2, [X11, X2,LSL #3]

  (1063) 0x4a64e4 LDP	D1, D3, [X0], #32

  (1063) 0x4a64e8 FMADD	D0, D1, D2, D0

  (1063) 0x4a64ec LDR	D1, [X11, X3,LSL #3]

  (1063) 0x4a64f0 FMADD	D0, D3, D1, D0

  (1063) 0x4a64f4 B.NE	4a64c0

(1062) 0x4a64f8 B	4a6420

0x4a64fc FMOV	D1, #-1.0000000

0x4a6500 FCMP	D0, D1

0x4a6504 B.NE	4a685c

0x4a6508 CMP	X20, X19

0x4a650c B.GE	4a6ffc

0x4a6510 LDR	X8, [X24]

0x4a6514 LDR	X9, [X23]

0x4a6518 LDR	X11, [X26]

0x4a651c ADD	X13, X9, #16

0x4a6520 LDR	X10, [X27]

0x4a6524 LDR	X12, [X25]

0x4a6528 LDR	X14, [X8, X20,LSL #3]

0x4a652c ADD	X15, X11, #16

0x4a6530 B	4a6550

0x4a6534 HINT	#0

0x4a6538 HINT	#0

0x4a653c HINT	#0

(1059) 0x4a6540 STR	D0, [X12, X20,LSL #3]

(1059) 0x4a6544 ORR	X20, XZR, X16

(1059) 0x4a6548 CMP	X16, X19

(1059) 0x4a654c B.EQ	4a6ffc

(1059) 0x4a6550 ADD	X16, X20, #1

(1059) 0x4a6554 ORR	X17, XZR, X14

(1059) 0x4a6558 MOVI	D0, #0

(1059) 0x4a655c LDR	X14, [X8, X16,LSL #3]

(1059) 0x4a6560 CMP	X14, X17

(1059) 0x4a6564 B.LE	4a6540

(1059) 0x4a6568 SUB	W18, W14, W17

(1059) 0x4a656c MOVI	D0, #0

(1059) 0x4a6570 ANDS	X0, X18, #4160

(1059) 0x4a6574 B.EQ	4a65b0

(1059) 0x4a6578 ORR	X18, XZR, X17

(1059) 0x4a657c HINT	#0

  (1061) 0x4a6580 LDR	X1, [X11, X18,LSL #3]

  (1061) 0x4a6584 LDR	D1, [X9, X18,LSL #3]

  (1061) 0x4a6588 ADD	X18, X18, #1

  (1061) 0x4a658c SUBS	X0, X0, #1

  (1061) 0x4a6590 LDR	D2, [X10, X1,LSL #3]

  (1061) 0x4a6594 FMSUB	D0, D1, D2, D0

  (1061) 0x4a6598 B.NE	4a6580

(1059) 0x4a659c ORN	X17, XZR, X17

(1059) 0x4a65a0 ADD	X17, X14, X17

(1059) 0x4a65a4 CMP	X17, #3

(1059) 0x4a65a8 B.CC	4a6540

(1059) 0x4a65ac B	4a65c4

(1059) 0x4a65b0 ORR	X18, XZR, X17

(1059) 0x4a65b4 ORN	X17, XZR, X17

(1059) 0x4a65b8 ADD	X17, X14, X17

(1059) 0x4a65bc CMP	X17, #3

(1059) 0x4a65c0 B.CC	4a6540

(1059) 0x4a65c4 UBFM	X0, X18, #61, #60

(1059) 0x4a65c8 SUB	X17, X14, X18

(1059) 0x4a65cc ADD	X18, X13, X0

(1059) 0x4a65d0 ADD	X0, X15, X0

(1059) 0x4a65d4 HINT	#0

(1059) 0x4a65d8 HINT	#0

(1059) 0x4a65dc HINT	#0

  (1060) 0x4a65e0 LDP	X1, X2, [X0, #1008]

  (1060) 0x4a65e4 LDP	D2, D3, [X18, #1008]

  (1060) 0x4a65e8 SUBS	X17, X17, #4

  (1060) 0x4a65ec LDR	D1, [X10, X1,LSL #3]

  (1060) 0x4a65f0 FMSUB	D0, D2, D1, D0

  (1060) 0x4a65f4 LDR	D1, [X10, X2,LSL #3]

  (1060) 0x4a65f8 FMSUB	D0, D3, D1, D0

  (1060) 0x4a65fc LDP	X1, X2, [X0], #32

  (1060) 0x4a6600 LDR	D2, [X10, X1,LSL #3]

  (1060) 0x4a6604 LDP	D1, D3, [X18], #32

  (1060) 0x4a6608 FMSUB	D0, D1, D2, D0

  (1060) 0x4a660c LDR	D1, [X10, X2,LSL #3]

  (1060) 0x4a6610 FMSUB	D0, D3, D1, D0

  (1060) 0x4a6614 B.NE	4a65e0

(1059) 0x4a6618 B	4a6540

0x4a661c LDR	D0, [X21]

0x4a6620 FMOV	D2, #1.0000000

0x4a6624 FCMP	D1, D2

0x4a6628 B.NE	4a695c

0x4a662c FCMP	D0, D2

0x4a6630 B.NE	4a6a7c

0x4a6634 CMP	X20, X19

0x4a6638 B.GE	4a6ffc

0x4a663c LDR	X9, [X24]

0x4a6640 LDR	X10, [X23]

0x4a6644 LDR	X12, [X26]

0x4a6648 ADD	X14, X10, #16

0x4a664c LDR	X8, [X8]

0x4a6650 LDR	X11, [X27]

0x4a6654 LDR	X13, [X25]

0x4a6658 LDR	X16, [X9, X20,LSL #3]

0x4a665c ADD	X15, X12, #16

0x4a6660 B	4a6674

(1080) 0x4a6664 STR	D0, [X13, X20,LSL #3]

(1080) 0x4a6668 ORR	X20, XZR, X17

(1080) 0x4a666c CMP	X17, X19

(1080) 0x4a6670 B.EQ	4a6ffc

(1080) 0x4a6674 LDR	D0, [X8, X20,LSL #3]

(1080) 0x4a6678 ADD	X17, X20, #1

(1080) 0x4a667c ORR	X18, XZR, X16

(1080) 0x4a6680 LDR	X16, [X9, X17,LSL #3]

(1080) 0x4a6684 CMP	X16, X18

(1080) 0x4a6688 B.LE	4a6664

(1080) 0x4a668c SUB	W0, W16, W18

(1080) 0x4a6690 ANDS	X1, X0, #4160

(1080) 0x4a6694 B.EQ	4a66d0

(1080) 0x4a6698 ORR	X0, XZR, X18

(1080) 0x4a669c HINT	#0

  (1082) 0x4a66a0 LDR	X2, [X12, X0,LSL #3]

  (1082) 0x4a66a4 LDR	D1, [X10, X0,LSL #3]

  (1082) 0x4a66a8 ADD	X0, X0, #1

  (1082) 0x4a66ac SUBS	X1, X1, #1

  (1082) 0x4a66b0 LDR	D2, [X11, X2,LSL #3]

  (1082) 0x4a66b4 FMADD	D0, D1, D2, D0

  (1082) 0x4a66b8 B.NE	4a66a0

(1080) 0x4a66bc ORN	X18, XZR, X18

(1080) 0x4a66c0 ADD	X18, X16, X18

(1080) 0x4a66c4 CMP	X18, #3

(1080) 0x4a66c8 B.CC	4a6664

(1080) 0x4a66cc B	4a66e4

(1080) 0x4a66d0 ORR	X0, XZR, X18

(1080) 0x4a66d4 ORN	X18, XZR, X18

(1080) 0x4a66d8 ADD	X18, X16, X18

(1080) 0x4a66dc CMP	X18, #3

(1080) 0x4a66e0 B.CC	4a6664

(1080) 0x4a66e4 UBFM	X1, X0, #61, #60

(1080) 0x4a66e8 SUB	X18, X16, X0

(1080) 0x4a66ec ADD	X0, X14, X1

(1080) 0x4a66f0 ADD	X1, X15, X1

(1080) 0x4a66f4 HINT	#0

(1080) 0x4a66f8 HINT	#0

(1080) 0x4a66fc HINT	#0

  (1081) 0x4a6700 LDP	X2, X3, [X1, #1008]

  (1081) 0x4a6704 LDP	D2, D3, [X0, #1008]

  (1081) 0x4a6708 SUBS	X18, X18, #4

  (1081) 0x4a670c LDR	D1, [X11, X2,LSL #3]

  (1081) 0x4a6710 FMADD	D0, D2, D1, D0

  (1081) 0x4a6714 LDR	D1, [X11, X3,LSL #3]

  (1081) 0x4a6718 FMADD	D0, D3, D1, D0

  (1081) 0x4a671c LDP	X2, X3, [X1], #32

  (1081) 0x4a6720 LDR	D2, [X11, X2,LSL #3]

  (1081) 0x4a6724 LDP	D1, D3, [X0], #32

  (1081) 0x4a6728 FMADD	D0, D1, D2, D0

  (1081) 0x4a672c LDR	D1, [X11, X3,LSL #3]

  (1081) 0x4a6730 FMADD	D0, D3, D1, D0

  (1081) 0x4a6734 B.NE	4a6700

(1080) 0x4a6738 B	4a6664

0x4a673c FMOV	D1, #-1.0000000

0x4a6740 FCMP	D0, D1

0x4a6744 B.NE	4a6b9c

0x4a6748 CMP	X20, X19

0x4a674c B.GE	4a6ffc

0x4a6750 LDR	X9, [X24]

0x4a6754 LDR	X10, [X23]

0x4a6758 LDR	X12, [X26]

0x4a675c ADD	X14, X10, #16

0x4a6760 LDR	X8, [X8]

0x4a6764 LDR	X11, [X27]

0x4a6768 LDR	X13, [X25]

0x4a676c LDR	X16, [X9, X20,LSL #3]

0x4a6770 ADD	X15, X12, #16

0x4a6774 B	4a6790

0x4a6778 HINT	#0

0x4a677c HINT	#0

(1056) 0x4a6780 STR	D0, [X13, X20,LSL #3]

(1056) 0x4a6784 ORR	X20, XZR, X17

(1056) 0x4a6788 CMP	X17, X19

(1056) 0x4a678c B.EQ	4a6ffc

(1056) 0x4a6790 LDR	D0, [X8, X20,LSL #3]

(1056) 0x4a6794 ADD	X17, X20, #1

(1056) 0x4a6798 ORR	X18, XZR, X16

(1056) 0x4a679c LDR	X16, [X9, X17,LSL #3]

(1056) 0x4a67a0 CMP	X16, X18

(1056) 0x4a67a4 B.LE	4a6780

(1056) 0x4a67a8 SUB	W0, W16, W18

(1056) 0x4a67ac ANDS	X1, X0, #4160

(1056) 0x4a67b0 B.EQ	4a67f0

(1056) 0x4a67b4 ORR	X0, XZR, X18

(1056) 0x4a67b8 HINT	#0

(1056) 0x4a67bc HINT	#0

  (1058) 0x4a67c0 LDR	X2, [X12, X0,LSL #3]

  (1058) 0x4a67c4 LDR	D1, [X10, X0,LSL #3]

  (1058) 0x4a67c8 ADD	X0, X0, #1

  (1058) 0x4a67cc SUBS	X1, X1, #1

  (1058) 0x4a67d0 LDR	D2, [X11, X2,LSL #3]

  (1058) 0x4a67d4 FMSUB	D0, D1, D2, D0

  (1058) 0x4a67d8 B.NE	4a67c0

(1056) 0x4a67dc ORN	X18, XZR, X18

(1056) 0x4a67e0 ADD	X18, X16, X18

(1056) 0x4a67e4 CMP	X18, #3

(1056) 0x4a67e8 B.CC	4a6780

(1056) 0x4a67ec B	4a6804

(1056) 0x4a67f0 ORR	X0, XZR, X18

(1056) 0x4a67f4 ORN	X18, XZR, X18

(1056) 0x4a67f8 ADD	X18, X16, X18

(1056) 0x4a67fc CMP	X18, #3

(1056) 0x4a6800 B.CC	4a6780

(1056) 0x4a6804 UBFM	X1, X0, #61, #60

(1056) 0x4a6808 SUB	X18, X16, X0

(1056) 0x4a680c ADD	X0, X14, X1

(1056) 0x4a6810 ADD	X1, X15, X1

(1056) 0x4a6814 HINT	#0

(1056) 0x4a6818 HINT	#0

(1056) 0x4a681c HINT	#0

  (1057) 0x4a6820 LDP	X2, X3, [X1, #1008]

  (1057) 0x4a6824 LDP	D2, D3, [X0, #1008]

  (1057) 0x4a6828 SUBS	X18, X18, #4

  (1057) 0x4a682c LDR	D1, [X11, X2,LSL #3]

  (1057) 0x4a6830 FMSUB	D0, D2, D1, D0

  (1057) 0x4a6834 LDR	D1, [X11, X3,LSL #3]

  (1057) 0x4a6838 FMSUB	D0, D3, D1, D0

  (1057) 0x4a683c LDP	X2, X3, [X1], #32

  (1057) 0x4a6840 LDR	D2, [X11, X2,LSL #3]

  (1057) 0x4a6844 LDP	D1, D3, [X0], #32

  (1057) 0x4a6848 FMSUB	D0, D1, D2, D0

  (1057) 0x4a684c LDR	D1, [X11, X3,LSL #3]

  (1057) 0x4a6850 FMSUB	D0, D3, D1, D0

  (1057) 0x4a6854 B.NE	4a6820

(1056) 0x4a6858 B	4a6780

0x4a685c CMP	X20, X19

0x4a6860 B.GE	4a6ffc

0x4a6864 LDR	X8, [X24]

0x4a6868 LDR	X9, [X23]

0x4a686c LDR	X11, [X26]

0x4a6870 ADD	X13, X9, #16

0x4a6874 LDR	X10, [X27]

0x4a6878 LDR	X12, [X25]

0x4a687c LDR	X14, [X8, X20,LSL #3]

0x4a6880 ADD	X15, X11, #16

0x4a6884 B	4a68a0

(1068) 0x4a6888 LDR	D1, [X21]

(1068) 0x4a688c CMP	X16, X19

(1068) 0x4a6890 FMUL	D0, D0, D1

(1068) 0x4a6894 STR	D0, [X12, X20,LSL #3]

(1068) 0x4a6898 ORR	X20, XZR, X16

(1068) 0x4a689c B.EQ	4a6ffc

(1068) 0x4a68a0 ADD	X16, X20, #1

(1068) 0x4a68a4 ORR	X17, XZR, X14

(1068) 0x4a68a8 MOVI	D0, #0

(1068) 0x4a68ac LDR	X14, [X8, X16,LSL #3]

(1068) 0x4a68b0 CMP	X14, X17

(1068) 0x4a68b4 B.LE	4a6888

(1068) 0x4a68b8 SUB	W18, W14, W17

(1068) 0x4a68bc MOVI	D0, #0

(1068) 0x4a68c0 ANDS	X0, X18, #4160

(1068) 0x4a68c4 B.EQ	4a68fc

(1068) 0x4a68c8 ORR	X18, XZR, X17

  (1070) 0x4a68cc LDR	X1, [X11, X18,LSL #3]

  (1070) 0x4a68d0 LDR	D1, [X9, X18,LSL #3]

  (1070) 0x4a68d4 ADD	X18, X18, #1

  (1070) 0x4a68d8 SUBS	X0, X0, #1

  (1070) 0x4a68dc LDR	D2, [X10, X1,LSL #3]

  (1070) 0x4a68e0 FMADD	D0, D1, D2, D0

  (1070) 0x4a68e4 B.NE	4a68cc

(1068) 0x4a68e8 ORN	X17, XZR, X17

(1068) 0x4a68ec ADD	X17, X14, X17

(1068) 0x4a68f0 CMP	X17, #3

(1068) 0x4a68f4 B.CC	4a6888

(1068) 0x4a68f8 B	4a6910

(1068) 0x4a68fc ORR	X18, XZR, X17

(1068) 0x4a6900 ORN	X17, XZR, X17

(1068) 0x4a6904 ADD	X17, X14, X17

(1068) 0x4a6908 CMP	X17, #3

(1068) 0x4a690c B.CC	4a6888

(1068) 0x4a6910 UBFM	X0, X18, #61, #60

(1068) 0x4a6914 SUB	X17, X14, X18

(1068) 0x4a6918 ADD	X18, X13, X0

(1068) 0x4a691c ADD	X0, X15, X0

  (1069) 0x4a6920 LDP	X1, X2, [X0, #1008]

  (1069) 0x4a6924 LDP	D2, D3, [X18, #1008]

  (1069) 0x4a6928 SUBS	X17, X17, #4

  (1069) 0x4a692c LDR	D1, [X10, X1,LSL #3]

  (1069) 0x4a6930 FMADD	D0, D2, D1, D0

  (1069) 0x4a6934 LDR	D1, [X10, X2,LSL #3]

  (1069) 0x4a6938 FMADD	D0, D3, D1, D0

  (1069) 0x4a693c LDP	X1, X2, [X0], #32

  (1069) 0x4a6940 LDR	D2, [X10, X1,LSL #3]

  (1069) 0x4a6944 LDP	D1, D3, [X18], #32

  (1069) 0x4a6948 FMADD	D0, D1, D2, D0

  (1069) 0x4a694c LDR	D1, [X10, X2,LSL #3]

  (1069) 0x4a6950 FMADD	D0, D3, D1, D0

  (1069) 0x4a6954 B.NE	4a6920

(1068) 0x4a6958 B	4a6888

0x4a695c FCMP	D0, D2

0x4a6960 B.NE	4a6cbc

0x4a6964 CMP	X20, X19

0x4a6968 B.GE	4a6ffc

0x4a696c LDR	X9, [X24]

0x4a6970 LDR	X10, [X23]

0x4a6974 LDR	X12, [X26]

0x4a6978 ADD	X14, X10, #16

0x4a697c LDR	X8, [X8]

0x4a6980 LDR	X11, [X27]

0x4a6984 LDR	X13, [X25]

0x4a6988 LDR	X16, [X9, X20,LSL #3]

0x4a698c ADD	X15, X12, #16

0x4a6990 B	4a69b0

0x4a6994 HINT	#0

0x4a6998 HINT	#0

0x4a699c HINT	#0

(1053) 0x4a69a0 STR	D0, [X13, X20,LSL #3]

(1053) 0x4a69a4 ORR	X20, XZR, X17

(1053) 0x4a69a8 CMP	X17, X19

(1053) 0x4a69ac B.EQ	4a6ffc

(1053) 0x4a69b0 LDR	D0, [X8, X20,LSL #3]

(1053) 0x4a69b4 LDR	D1, [X22]

(1053) 0x4a69b8 ADD	X17, X20, #1

(1053) 0x4a69bc ORR	X18, XZR, X16

(1053) 0x4a69c0 LDR	X16, [X9, X17,LSL #3]

(1053) 0x4a69c4 CMP	X16, X18

(1053) 0x4a69c8 FMUL	D0, D0, D1

(1053) 0x4a69cc B.LE	4a69a0

(1053) 0x4a69d0 SUB	W0, W16, W18

(1053) 0x4a69d4 ANDS	X1, X0, #4160

(1053) 0x4a69d8 B.EQ	4a6a10

(1053) 0x4a69dc ORR	X0, XZR, X18

  (1055) 0x4a69e0 LDR	X2, [X12, X0,LSL #3]

  (1055) 0x4a69e4 LDR	D1, [X10, X0,LSL #3]

  (1055) 0x4a69e8 ADD	X0, X0, #1

  (1055) 0x4a69ec SUBS	X1, X1, #1

  (1055) 0x4a69f0 LDR	D2, [X11, X2,LSL #3]

  (1055) 0x4a69f4 FMADD	D0, D1, D2, D0

  (1055) 0x4a69f8 B.NE	4a69e0

(1053) 0x4a69fc ORN	X18, XZR, X18

(1053) 0x4a6a00 ADD	X18, X16, X18

(1053) 0x4a6a04 CMP	X18, #3

(1053) 0x4a6a08 B.CC	4a69a0

(1053) 0x4a6a0c B	4a6a24

(1053) 0x4a6a10 ORR	X0, XZR, X18

(1053) 0x4a6a14 ORN	X18, XZR, X18

(1053) 0x4a6a18 ADD	X18, X16, X18

(1053) 0x4a6a1c CMP	X18, #3

(1053) 0x4a6a20 B.CC	4a69a0

(1053) 0x4a6a24 UBFM	X1, X0, #61, #60

(1053) 0x4a6a28 SUB	X18, X16, X0

(1053) 0x4a6a2c ADD	X0, X14, X1

(1053) 0x4a6a30 ADD	X1, X15, X1

(1053) 0x4a6a34 HINT	#0

(1053) 0x4a6a38 HINT	#0

(1053) 0x4a6a3c HINT	#0

  (1054) 0x4a6a40 LDP	X2, X3, [X1, #1008]

  (1054) 0x4a6a44 LDP	D2, D3, [X0, #1008]

  (1054) 0x4a6a48 SUBS	X18, X18, #4

  (1054) 0x4a6a4c LDR	D1, [X11, X2,LSL #3]

  (1054) 0x4a6a50 FMADD	D0, D2, D1, D0

  (1054) 0x4a6a54 LDR	D1, [X11, X3,LSL #3]

  (1054) 0x4a6a58 FMADD	D0, D3, D1, D0

  (1054) 0x4a6a5c LDP	X2, X3, [X1], #32

  (1054) 0x4a6a60 LDR	D2, [X11, X2,LSL #3]

  (1054) 0x4a6a64 LDP	D1, D3, [X0], #32

  (1054) 0x4a6a68 FMADD	D0, D1, D2, D0

  (1054) 0x4a6a6c LDR	D1, [X11, X3,LSL #3]

  (1054) 0x4a6a70 FMADD	D0, D3, D1, D0

  (1054) 0x4a6a74 B.NE	4a6a40

(1053) 0x4a6a78 B	4a69a0

0x4a6a7c FMOV	D1, #-1.0000000

0x4a6a80 FCMP	D0, D1

0x4a6a84 B.NE	4a6ddc

0x4a6a88 CMP	X20, X19

0x4a6a8c B.GE	4a6ffc

0x4a6a90 LDR	X9, [X24]

0x4a6a94 LDR	X10, [X23]

0x4a6a98 LDR	X12, [X26]

0x4a6a9c ADD	X14, X10, #16

0x4a6aa0 LDR	X8, [X8]

0x4a6aa4 LDR	X11, [X27]

0x4a6aa8 LDR	X13, [X25]

0x4a6aac LDR	X16, [X9, X20,LSL #3]

0x4a6ab0 ADD	X15, X12, #16

0x4a6ab4 B	4a6ad0

0x4a6ab8 HINT	#0

0x4a6abc HINT	#0

(1050) 0x4a6ac0 STR	D0, [X13, X20,LSL #3]

(1050) 0x4a6ac4 ORR	X20, XZR, X17

(1050) 0x4a6ac8 CMP	X17, X19

(1050) 0x4a6acc B.EQ	4a6ffc

(1050) 0x4a6ad0 LDR	D0, [X8, X20,LSL #3]

(1050) 0x4a6ad4 ADD	X17, X20, #1

(1050) 0x4a6ad8 ORR	X18, XZR, X16

(1050) 0x4a6adc LDR	X16, [X9, X17,LSL #3]

(1050) 0x4a6ae0 CMP	X16, X18

(1050) 0x4a6ae4 FNEG	D0, D0

(1050) 0x4a6ae8 B.LE	4a6ac0

(1050) 0x4a6aec SUB	W0, W16, W18

(1050) 0x4a6af0 ANDS	X1, X0, #4160

(1050) 0x4a6af4 B.EQ	4a6b30

(1050) 0x4a6af8 ORR	X0, XZR, X18

(1050) 0x4a6afc HINT	#0

  (1052) 0x4a6b00 LDR	X2, [X12, X0,LSL #3]

  (1052) 0x4a6b04 LDR	D1, [X10, X0,LSL #3]

  (1052) 0x4a6b08 ADD	X0, X0, #1

  (1052) 0x4a6b0c SUBS	X1, X1, #1

  (1052) 0x4a6b10 LDR	D2, [X11, X2,LSL #3]

  (1052) 0x4a6b14 FMSUB	D0, D1, D2, D0

  (1052) 0x4a6b18 B.NE	4a6b00

(1050) 0x4a6b1c ORN	X18, XZR, X18

(1050) 0x4a6b20 ADD	X18, X16, X18

(1050) 0x4a6b24 CMP	X18, #3

(1050) 0x4a6b28 B.CC	4a6ac0

(1050) 0x4a6b2c B	4a6b44

(1050) 0x4a6b30 ORR	X0, XZR, X18

(1050) 0x4a6b34 ORN	X18, XZR, X18

(1050) 0x4a6b38 ADD	X18, X16, X18

(1050) 0x4a6b3c CMP	X18, #3

(1050) 0x4a6b40 B.CC	4a6ac0

(1050) 0x4a6b44 UBFM	X1, X0, #61, #60

(1050) 0x4a6b48 SUB	X18, X16, X0

(1050) 0x4a6b4c ADD	X0, X14, X1

(1050) 0x4a6b50 ADD	X1, X15, X1

(1050) 0x4a6b54 HINT	#0

(1050) 0x4a6b58 HINT	#0

(1050) 0x4a6b5c HINT	#0

  (1051) 0x4a6b60 LDP	X2, X3, [X1, #1008]

  (1051) 0x4a6b64 LDP	D2, D3, [X0, #1008]

  (1051) 0x4a6b68 SUBS	X18, X18, #4

  (1051) 0x4a6b6c LDR	D1, [X11, X2,LSL #3]

  (1051) 0x4a6b70 FMSUB	D0, D2, D1, D0

  (1051) 0x4a6b74 LDR	D1, [X11, X3,LSL #3]

  (1051) 0x4a6b78 FMSUB	D0, D3, D1, D0

  (1051) 0x4a6b7c LDP	X2, X3, [X1], #32

  (1051) 0x4a6b80 LDR	D2, [X11, X2,LSL #3]

  (1051) 0x4a6b84 LDP	D1, D3, [X0], #32

  (1051) 0x4a6b88 FMSUB	D0, D1, D2, D0

  (1051) 0x4a6b8c LDR	D1, [X11, X3,LSL #3]

  (1051) 0x4a6b90 FMSUB	D0, D3, D1, D0

  (1051) 0x4a6b94 B.NE	4a6b60

(1050) 0x4a6b98 B	4a6ac0

0x4a6b9c CMP	X20, X19

0x4a6ba0 B.GE	4a6ffc

0x4a6ba4 LDR	X9, [X24]

0x4a6ba8 LDR	X10, [X23]

0x4a6bac LDR	X12, [X26]

0x4a6bb0 ADD	X14, X10, #16

0x4a6bb4 LDR	X8, [X8]

0x4a6bb8 LDR	X11, [X27]

0x4a6bbc LDR	X13, [X25]

0x4a6bc0 LDR	X16, [X9, X20,LSL #3]

0x4a6bc4 ADD	X15, X12, #16

0x4a6bc8 B	4a6be4

(1083) 0x4a6bcc LDR	D1, [X21]

(1083) 0x4a6bd0 CMP	X17, X19

(1083) 0x4a6bd4 FMUL	D0, D0, D1

(1083) 0x4a6bd8 STR	D0, [X13, X20,LSL #3]

(1083) 0x4a6bdc ORR	X20, XZR, X17

(1083) 0x4a6be0 B.EQ	4a6ffc

(1083) 0x4a6be4 LDR	D0, [X8, X20,LSL #3]

(1083) 0x4a6be8 ADD	X17, X20, #1

(1083) 0x4a6bec ORR	X18, XZR, X16

(1083) 0x4a6bf0 LDR	X16, [X9, X17,LSL #3]

(1083) 0x4a6bf4 CMP	X16, X18

(1083) 0x4a6bf8 FNEG	D0, D0

(1083) 0x4a6bfc B.LE	4a6bcc

(1083) 0x4a6c00 SUB	W0, W16, W18

(1083) 0x4a6c04 ANDS	X1, X0, #4160

(1083) 0x4a6c08 B.EQ	4a6c50

(1083) 0x4a6c0c ORR	X0, XZR, X18

(1083) 0x4a6c10 HINT	#0

(1083) 0x4a6c14 HINT	#0

(1083) 0x4a6c18 HINT	#0

(1083) 0x4a6c1c HINT	#0

  (1085) 0x4a6c20 LDR	X2, [X12, X0,LSL #3]

  (1085) 0x4a6c24 LDR	D1, [X10, X0,LSL #3]

  (1085) 0x4a6c28 ADD	X0, X0, #1

  (1085) 0x4a6c2c SUBS	X1, X1, #1

  (1085) 0x4a6c30 LDR	D2, [X11, X2,LSL #3]

  (1085) 0x4a6c34 FMADD	D0, D1, D2, D0

  (1085) 0x4a6c38 B.NE	4a6c20

(1083) 0x4a6c3c ORN	X18, XZR, X18

(1083) 0x4a6c40 ADD	X18, X16, X18

(1083) 0x4a6c44 CMP	X18, #3

(1083) 0x4a6c48 B.CC	4a6bcc

(1083) 0x4a6c4c B	4a6c64

(1083) 0x4a6c50 ORR	X0, XZR, X18

(1083) 0x4a6c54 ORN	X18, XZR, X18

(1083) 0x4a6c58 ADD	X18, X16, X18

(1083) 0x4a6c5c CMP	X18, #3

(1083) 0x4a6c60 B.CC	4a6bcc

(1083) 0x4a6c64 UBFM	X1, X0, #61, #60

(1083) 0x4a6c68 SUB	X18, X16, X0

(1083) 0x4a6c6c ADD	X0, X14, X1

(1083) 0x4a6c70 ADD	X1, X15, X1

(1083) 0x4a6c74 HINT	#0

(1083) 0x4a6c78 HINT	#0

(1083) 0x4a6c7c HINT	#0

  (1084) 0x4a6c80 LDP	X2, X3, [X1, #1008]

  (1084) 0x4a6c84 LDP	D2, D3, [X0, #1008]

  (1084) 0x4a6c88 SUBS	X18, X18, #4

  (1084) 0x4a6c8c LDR	D1, [X11, X2,LSL #3]

  (1084) 0x4a6c90 FMADD	D0, D2, D1, D0

  (1084) 0x4a6c94 LDR	D1, [X11, X3,LSL #3]

  (1084) 0x4a6c98 FMADD	D0, D3, D1, D0

  (1084) 0x4a6c9c LDP	X2, X3, [X1], #32

  (1084) 0x4a6ca0 LDR	D2, [X11, X2,LSL #3]

  (1084) 0x4a6ca4 LDP	D1, D3, [X0], #32

  (1084) 0x4a6ca8 FMADD	D0, D1, D2, D0

  (1084) 0x4a6cac LDR	D1, [X11, X3,LSL #3]

  (1084) 0x4a6cb0 FMADD	D0, D3, D1, D0

  (1084) 0x4a6cb4 B.NE	4a6c80

(1083) 0x4a6cb8 B	4a6bcc

0x4a6cbc FMOV	D1, #-1.0000000

0x4a6cc0 FCMP	D0, D1

0x4a6cc4 B.NE	4a6edc

0x4a6cc8 CMP	X20, X19

0x4a6ccc B.GE	4a6ffc

0x4a6cd0 LDR	X9, [X24]

0x4a6cd4 LDR	X10, [X23]

0x4a6cd8 LDR	X12, [X26]

0x4a6cdc ADD	X14, X10, #16

0x4a6ce0 LDR	X8, [X8]

0x4a6ce4 LDR	X11, [X27]

0x4a6ce8 LDR	X13, [X25]

0x4a6cec LDR	X16, [X9, X20,LSL #3]

0x4a6cf0 ADD	X15, X12, #16

0x4a6cf4 B	4a6d08

(1074) 0x4a6cf8 STR	D0, [X13, X20,LSL #3]

(1074) 0x4a6cfc ORR	X20, XZR, X17

(1074) 0x4a6d00 CMP	X17, X19

(1074) 0x4a6d04 B.EQ	4a6ffc

(1074) 0x4a6d08 LDR	D0, [X8, X20,LSL #3]

(1074) 0x4a6d0c LDR	D1, [X22]

(1074) 0x4a6d10 ADD	X17, X20, #1

(1074) 0x4a6d14 ORR	X18, XZR, X16

(1074) 0x4a6d18 LDR	X16, [X9, X17,LSL #3]

(1074) 0x4a6d1c CMP	X16, X18

(1074) 0x4a6d20 FNMUL	D0, D0, D1

(1074) 0x4a6d24 B.LE	4a6cf8

(1074) 0x4a6d28 SUB	W0, W16, W18

(1074) 0x4a6d2c ANDS	X1, X0, #4160

(1074) 0x4a6d30 B.EQ	4a6d70

(1074) 0x4a6d34 ORR	X0, XZR, X18

(1074) 0x4a6d38 HINT	#0

(1074) 0x4a6d3c HINT	#0

  (1076) 0x4a6d40 LDR	X2, [X12, X0,LSL #3]

  (1076) 0x4a6d44 LDR	D1, [X10, X0,LSL #3]

  (1076) 0x4a6d48 ADD	X0, X0, #1

  (1076) 0x4a6d4c SUBS	X1, X1, #1

  (1076) 0x4a6d50 LDR	D2, [X11, X2,LSL #3]

  (1076) 0x4a6d54 FMSUB	D0, D1, D2, D0

  (1076) 0x4a6d58 B.NE	4a6d40

(1074) 0x4a6d5c ORN	X18, XZR, X18

(1074) 0x4a6d60 ADD	X18, X16, X18

(1074) 0x4a6d64 CMP	X18, #3

(1074) 0x4a6d68 B.CC	4a6cf8

(1074) 0x4a6d6c B	4a6d84

(1074) 0x4a6d70 ORR	X0, XZR, X18

(1074) 0x4a6d74 ORN	X18, XZR, X18

(1074) 0x4a6d78 ADD	X18, X16, X18

(1074) 0x4a6d7c CMP	X18, #3

(1074) 0x4a6d80 B.CC	4a6cf8

(1074) 0x4a6d84 UBFM	X1, X0, #61, #60

(1074) 0x4a6d88 SUB	X18, X16, X0

(1074) 0x4a6d8c ADD	X0, X14, X1

(1074) 0x4a6d90 ADD	X1, X15, X1

(1074) 0x4a6d94 HINT	#0

(1074) 0x4a6d98 HINT	#0

(1074) 0x4a6d9c HINT	#0

  (1075) 0x4a6da0 LDP	X2, X3, [X1, #1008]

  (1075) 0x4a6da4 LDP	D2, D3, [X0, #1008]

  (1075) 0x4a6da8 SUBS	X18, X18, #4

  (1075) 0x4a6dac LDR	D1, [X11, X2,LSL #3]

  (1075) 0x4a6db0 FMSUB	D0, D2, D1, D0

  (1075) 0x4a6db4 LDR	D1, [X11, X3,LSL #3]

  (1075) 0x4a6db8 FMSUB	D0, D3, D1, D0

  (1075) 0x4a6dbc LDP	X2, X3, [X1], #32

  (1075) 0x4a6dc0 LDR	D2, [X11, X2,LSL #3]

  (1075) 0x4a6dc4 LDP	D1, D3, [X0], #32

  (1075) 0x4a6dc8 FMSUB	D0, D1, D2, D0

  (1075) 0x4a6dcc LDR	D1, [X11, X3,LSL #3]

  (1075) 0x4a6dd0 FMSUB	D0, D3, D1, D0

  (1075) 0x4a6dd4 B.NE	4a6da0

(1074) 0x4a6dd8 B	4a6cf8

0x4a6ddc CMP	X20, X19

0x4a6de0 B.GE	4a6ffc

0x4a6de4 LDR	X9, [X24]

0x4a6de8 LDR	X10, [X23]

0x4a6dec LDR	X12, [X26]

0x4a6df0 ADD	X14, X10, #16

0x4a6df4 LDR	X8, [X8]

0x4a6df8 LDR	X11, [X27]

0x4a6dfc LDR	X13, [X25]

0x4a6e00 LDR	X16, [X9, X20,LSL #3]

0x4a6e04 ADD	X15, X12, #16

0x4a6e08 B	4a6e24

(1077) 0x4a6e0c LDR	D1, [X21]

(1077) 0x4a6e10 CMP	X17, X19

(1077) 0x4a6e14 FMUL	D0, D0, D1

(1077) 0x4a6e18 STR	D0, [X13, X20,LSL #3]

(1077) 0x4a6e1c ORR	X20, XZR, X17

(1077) 0x4a6e20 B.EQ	4a6ffc

(1077) 0x4a6e24 LDR	D0, [X8, X20,LSL #3]

(1077) 0x4a6e28 ADD	X17, X20, #1

(1077) 0x4a6e2c ORR	X18, XZR, X16

(1077) 0x4a6e30 LDR	X16, [X9, X17,LSL #3]

(1077) 0x4a6e34 CMP	X16, X18

(1077) 0x4a6e38 B.LE	4a6e0c

(1077) 0x4a6e3c SUB	W0, W16, W18

(1077) 0x4a6e40 ANDS	X1, X0, #4160

(1077) 0x4a6e44 B.EQ	4a6e7c

(1077) 0x4a6e48 ORR	X0, XZR, X18

  (1079) 0x4a6e4c LDR	X2, [X12, X0,LSL #3]

  (1079) 0x4a6e50 LDR	D1, [X10, X0,LSL #3]

  (1079) 0x4a6e54 ADD	X0, X0, #1

  (1079) 0x4a6e58 SUBS	X1, X1, #1

  (1079) 0x4a6e5c LDR	D2, [X11, X2,LSL #3]

  (1079) 0x4a6e60 FMADD	D0, D1, D2, D0

  (1079) 0x4a6e64 B.NE	4a6e4c

(1077) 0x4a6e68 ORN	X18, XZR, X18

(1077) 0x4a6e6c ADD	X18, X16, X18

(1077) 0x4a6e70 CMP	X18, #3

(1077) 0x4a6e74 B.CC	4a6e0c

(1077) 0x4a6e78 B	4a6e90

(1077) 0x4a6e7c ORR	X0, XZR, X18

(1077) 0x4a6e80 ORN	X18, XZR, X18

(1077) 0x4a6e84 ADD	X18, X16, X18

(1077) 0x4a6e88 CMP	X18, #3

(1077) 0x4a6e8c B.CC	4a6e0c

(1077) 0x4a6e90 UBFM	X1, X0, #61, #60

(1077) 0x4a6e94 SUB	X18, X16, X0

(1077) 0x4a6e98 ADD	X0, X14, X1

(1077) 0x4a6e9c ADD	X1, X15, X1

  (1078) 0x4a6ea0 LDP	X2, X3, [X1, #1008]

  (1078) 0x4a6ea4 LDP	D2, D3, [X0, #1008]

  (1078) 0x4a6ea8 SUBS	X18, X18, #4

  (1078) 0x4a6eac LDR	D1, [X11, X2,LSL #3]

  (1078) 0x4a6eb0 FMADD	D0, D2, D1, D0

  (1078) 0x4a6eb4 LDR	D1, [X11, X3,LSL #3]

  (1078) 0x4a6eb8 FMADD	D0, D3, D1, D0

  (1078) 0x4a6ebc LDP	X2, X3, [X1], #32

  (1078) 0x4a6ec0 LDR	D2, [X11, X2,LSL #3]

  (1078) 0x4a6ec4 LDP	D1, D3, [X0], #32

  (1078) 0x4a6ec8 FMADD	D0, D1, D2, D0

  (1078) 0x4a6ecc LDR	D1, [X11, X3,LSL #3]

  (1078) 0x4a6ed0 FMADD	D0, D3, D1, D0

  (1078) 0x4a6ed4 B.NE	4a6ea0

(1077) 0x4a6ed8 B	4a6e0c

0x4a6edc CMP	X20, X19

0x4a6ee0 B.GE	4a6ffc

0x4a6ee4 LDR	X9, [X24]

0x4a6ee8 LDR	X10, [X23]

0x4a6eec LDR	X12, [X26]

0x4a6ef0 ADD	X14, X10, #16

0x4a6ef4 LDR	X8, [X8]

0x4a6ef8 LDR	X11, [X27]

0x4a6efc LDR	X13, [X25]

0x4a6f00 LDR	X16, [X9, X20,LSL #3]

0x4a6f04 ADD	X15, X12, #16

0x4a6f08 B	4a6f24

(1071) 0x4a6f0c LDR	D1, [X21]

(1071) 0x4a6f10 CMP	X17, X19

(1071) 0x4a6f14 FMUL	D0, D0, D1

(1071) 0x4a6f18 STR	D0, [X13, X20,LSL #3]

(1071) 0x4a6f1c ORR	X20, XZR, X17

(1071) 0x4a6f20 B.EQ	4a6ffc

(1071) 0x4a6f24 LDR	D0, [X8, X20,LSL #3]

(1071) 0x4a6f28 LDR	D1, [X22]

(1071) 0x4a6f2c ADD	X17, X20, #1

(1071) 0x4a6f30 ORR	X18, XZR, X16

(1071) 0x4a6f34 LDR	X16, [X9, X17,LSL #3]

(1071) 0x4a6f38 CMP	X16, X18

(1071) 0x4a6f3c FMUL	D0, D0, D1

(1071) 0x4a6f40 B.LE	4a6f0c

(1071) 0x4a6f44 SUB	W0, W16, W18

(1071) 0x4a6f48 ANDS	X1, X0, #4160

(1071) 0x4a6f4c B.EQ	4a6f90

(1071) 0x4a6f50 ORR	X0, XZR, X18

(1071) 0x4a6f54 HINT	#0

(1071) 0x4a6f58 HINT	#0

(1071) 0x4a6f5c HINT	#0

  (1073) 0x4a6f60 LDR	X2, [X12, X0,LSL #3]

  (1073) 0x4a6f64 LDR	D1, [X10, X0,LSL #3]

  (1073) 0x4a6f68 ADD	X0, X0, #1

  (1073) 0x4a6f6c SUBS	X1, X1, #1

  (1073) 0x4a6f70 LDR	D2, [X11, X2,LSL #3]

  (1073) 0x4a6f74 FMADD	D0, D1, D2, D0

  (1073) 0x4a6f78 B.NE	4a6f60

(1071) 0x4a6f7c ORN	X18, XZR, X18

(1071) 0x4a6f80 ADD	X18, X16, X18

(1071) 0x4a6f84 CMP	X18, #3

(1071) 0x4a6f88 B.CC	4a6f0c

(1071) 0x4a6f8c B	4a6fa4

(1071) 0x4a6f90 ORR	X0, XZR, X18

(1071) 0x4a6f94 ORN	X18, XZR, X18

(1071) 0x4a6f98 ADD	X18, X16, X18

(1071) 0x4a6f9c CMP	X18, #3

(1071) 0x4a6fa0 B.CC	4a6f0c

(1071) 0x4a6fa4 UBFM	X1, X0, #61, #60

(1071) 0x4a6fa8 SUB	X18, X16, X0

(1071) 0x4a6fac ADD	X0, X14, X1

(1071) 0x4a6fb0 ADD	X1, X15, X1

(1071) 0x4a6fb4 HINT	#0

(1071) 0x4a6fb8 HINT	#0

(1071) 0x4a6fbc HINT	#0

  (1072) 0x4a6fc0 LDP	X2, X3, [X1, #1008]

  (1072) 0x4a6fc4 LDP	D2, D3, [X0, #1008]

  (1072) 0x4a6fc8 SUBS	X18, X18, #4

  (1072) 0x4a6fcc LDR	D1, [X11, X2,LSL #3]

  (1072) 0x4a6fd0 FMADD	D0, D2, D1, D0

  (1072) 0x4a6fd4 LDR	D1, [X11, X3,LSL #3]

  (1072) 0x4a6fd8 FMADD	D0, D3, D1, D0

  (1072) 0x4a6fdc LDP	X2, X3, [X1], #32

  (1072) 0x4a6fe0 LDR	D2, [X11, X2,LSL #3]

  (1072) 0x4a6fe4 LDP	D1, D3, [X0], #32

  (1072) 0x4a6fe8 FMADD	D0, D1, D2, D0

  (1072) 0x4a6fec LDR	D1, [X11, X3,LSL #3]

  (1072) 0x4a6ff0 FMADD	D0, D3, D1, D0

  (1072) 0x4a6ff4 B.NE	4a6fc0

(1071) 0x4a6ff8 B	4a6f0c

0x4a6ffc LDP	X20, X19, [SP, #80]

0x4a7000 LDP	X22, X21, [SP, #64]

0x4a7004 LDP	X24, X23, [SP, #48]

0x4a7008 LDP	X26, X25, [SP, #32]

0x4a700c LDR	X27, [SP, #16]

0x4a7010 LDP	X29, X30, [SP], #96

0x4a7014 RET

0x4a7018 HINT	#0

0x4a701c HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	csr_matvec.c:243-404
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:243-365,371-404.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 37.00 to 5.67 cycles (6.53x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 37.00 to 4.83 cycles (7.66x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 37.00 to 4.00 cycles (9.25x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 888 bytes. The binary function is storing 88 bytes.

General properties

nb instructions	278
loop length	1112
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

32.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	25.00	25.00	21.75	21.75	21.75	21.75	12.00	2.75	2.75	2.50	37.00	37.00	37.00	3.00	3.00
cycles	25.00	25.00	21.75	21.75	21.75	21.75	12.00	2.75	2.75	2.50	37.00	37.00	37.00	3.00	3.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	32.38
Overall L1	37.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 37.00 cycles. At this rate:

25% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.38 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4a6160

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X23, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X24, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a4c20 <hypre_CSRMatrixGetLoadBalancedPartitionBegin>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4a4cb0 <hypre_CSRMatrixGetLoadBalancedPartitionEnd>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X20, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4a61ec <.omp_outlined..18+0x8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X8, <4ef1b4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X1, <4c21b8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, #1027	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <4c41c0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #137	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8, #4056]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4ae6f0 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4c41d8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1934	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #248	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b0fc0 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
TBNZ X20, #63, 4a61fc <.omp_outlined..18+0x9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X20, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4a6238 <.omp_outlined..18+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X8, <4ef1fc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X1, <4c2200>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, #1027	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <4c4208>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #3539	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8, #4056]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4ae6f0 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4c4220>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1934	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #249	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b0fc0 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X26, X25, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X27, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
TBNZ X19, #63, 4a637c <.omp_outlined..18+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X19, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 4a637c <.omp_outlined..18+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D1, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMP D1, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 4a63c0 <.omp_outlined..18+0x260>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMOV D1, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 4a64fc <.omp_outlined..18+0x39c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a6ffc <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X9, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X8, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a62b0 <.omp_outlined..18+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
ADRP X8, <4ef37c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X1, <4c2380>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, #1027	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <4c4388>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #3573	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8, #4056]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4ae6f0 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4c43a0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1934	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #250	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b0fc0 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D1, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMP D1, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.EQ 4a6258 <.omp_outlined..18+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FMOV D0, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMP D1, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 4a661c <.omp_outlined..18+0x4bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMOV D1, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 4a673c <.omp_outlined..18+0x5dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a6ffc <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a6430 <.omp_outlined..18+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
FMOV D1, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 4a685c <.omp_outlined..18+0x6fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a6ffc <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X9, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X8, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a6550 <.omp_outlined..18+0x3f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
LDR D0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMOV D2, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMP D1, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 4a695c <.omp_outlined..18+0x7fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FCMP D0, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 4a6a7c <.omp_outlined..18+0x91c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a6ffc <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a6674 <.omp_outlined..18+0x514>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMOV D1, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 4a6b9c <.omp_outlined..18+0xa3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a6ffc <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a6790 <.omp_outlined..18+0x630>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a6ffc <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X9, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X8, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a68a0 <.omp_outlined..18+0x740>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FCMP D0, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 4a6cbc <.omp_outlined..18+0xb5c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a6ffc <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a69b0 <.omp_outlined..18+0x850>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
FMOV D1, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 4a6ddc <.omp_outlined..18+0xc7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a6ffc <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a6ad0 <.omp_outlined..18+0x970>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a6ffc <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a6be4 <.omp_outlined..18+0xa84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMOV D1, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 4a6edc <.omp_outlined..18+0xd7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a6ffc <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a6d08 <.omp_outlined..18+0xba8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a6ffc <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a6e24 <.omp_outlined..18+0xcc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a6ffc <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a6f24 <.omp_outlined..18+0xdc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Source file and lines	csr_matvec.c:243-404
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:243-365,371-404.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 37.00 to 5.67 cycles (6.53x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 37.00 to 4.00 cycles (9.25x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 888 bytes. The binary function is storing 88 bytes.

General properties

nb instructions	278
loop length	1112
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

32.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	25.00	25.00	21.75	21.75	21.75	21.75	12.00	2.75	2.75	2.50	37.00	37.00	37.00	3.00	3.00
cycles	25.00	25.00	21.75	21.75	21.75	21.75	12.00	2.75	2.75	2.50	37.00	37.00	37.00	3.00	3.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	32.38
Overall L1	37.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 37.00 cycles. At this rate:

25% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.38 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4a6160

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X23, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X24, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a4c20 <hypre_CSRMatrixGetLoadBalancedPartitionBegin>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4a4cb0 <hypre_CSRMatrixGetLoadBalancedPartitionEnd>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X20, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4a61ec <.omp_outlined..18+0x8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X8, <4ef1b4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X1, <4c21b8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, #1027	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <4c41c0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #137	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8, #4056]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4ae6f0 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4c41d8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1934	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #248	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b0fc0 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
TBNZ X20, #63, 4a61fc <.omp_outlined..18+0x9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X20, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4a6238 <.omp_outlined..18+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X8, <4ef1fc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X1, <4c2200>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, #1027	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <4c4208>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #3539	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8, #4056]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4ae6f0 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4c4220>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1934	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #249	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b0fc0 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X26, X25, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X27, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
TBNZ X19, #63, 4a637c <.omp_outlined..18+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X19, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 4a637c <.omp_outlined..18+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D1, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMP D1, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 4a63c0 <.omp_outlined..18+0x260>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMOV D1, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 4a64fc <.omp_outlined..18+0x39c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a6ffc <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X9, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X8, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a62b0 <.omp_outlined..18+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
ADRP X8, <4ef37c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X1, <4c2380>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, #1027	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <4c4388>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #3573	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8, #4056]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4ae6f0 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4c43a0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1934	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #250	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b0fc0 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D1, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMP D1, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.EQ 4a6258 <.omp_outlined..18+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FMOV D0, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMP D1, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 4a661c <.omp_outlined..18+0x4bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMOV D1, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 4a673c <.omp_outlined..18+0x5dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a6ffc <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a6430 <.omp_outlined..18+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
FMOV D1, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 4a685c <.omp_outlined..18+0x6fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a6ffc <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X9, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X8, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a6550 <.omp_outlined..18+0x3f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
LDR D0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMOV D2, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMP D1, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 4a695c <.omp_outlined..18+0x7fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FCMP D0, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 4a6a7c <.omp_outlined..18+0x91c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a6ffc <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a6674 <.omp_outlined..18+0x514>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMOV D1, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 4a6b9c <.omp_outlined..18+0xa3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a6ffc <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a6790 <.omp_outlined..18+0x630>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a6ffc <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X9, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X8, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a68a0 <.omp_outlined..18+0x740>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FCMP D0, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 4a6cbc <.omp_outlined..18+0xb5c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a6ffc <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a69b0 <.omp_outlined..18+0x850>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
FMOV D1, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 4a6ddc <.omp_outlined..18+0xc7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a6ffc <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a6ad0 <.omp_outlined..18+0x970>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a6ffc <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a6be4 <.omp_outlined..18+0xa84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMOV D1, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 4a6edc <.omp_outlined..18+0xd7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a6ffc <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a6d08 <.omp_outlined..18+0xba8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a6ffc <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a6e24 <.omp_outlined..18+0xcc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a6ffc <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a6f24 <.omp_outlined..18+0xdc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..18#0x4a6160–	15.66	5.93
▼Loop 1080 - csr_matvec.c:334-341 - exec–	0.27	0.09
○Loop 1082 - csr_matvec.c:337-339 - exec	0.41	0.13
○Loop 1081 - csr_matvec.c:337-339 - exec	0.12	0.04
▼Loop 1065 - csr_matvec.c:256-263 - exec–	0.15	0.05
○Loop 1066 - csr_matvec.c:259-261 - exec	6.08	1.98
○Loop 1067 - csr_matvec.c:259-261 - exec	0.77	0.25
▼Loop 1056 - csr_matvec.c:307-314 - exec–	0.15	0.05
○Loop 1057 - csr_matvec.c:310-312 - exec	6.8	2.22
○Loop 1058 - csr_matvec.c:310-312 - exec	0.9	0.29
▼Loop 1050 - csr_matvec.c:346-353 - exec–	0	0
○Loop 1052 - csr_matvec.c:349-351 - exec	0	0
○Loop 1051 - csr_matvec.c:349-351 - exec	0	0
▼Loop 1077 - csr_matvec.c:358-365 - exec–	0	0
○Loop 1078 - csr_matvec.c:361-363 - exec	0	0
○Loop 1079 - csr_matvec.c:361-363 - exec	0	0
▼Loop 1083 - csr_matvec.c:319-326 - exec–	0	0
○Loop 1084 - csr_matvec.c:322-324 - exec	0	0
○Loop 1085 - csr_matvec.c:322-324 - exec	0	0
▼Loop 1062 - csr_matvec.c:295-302 - exec–	0	0
○Loop 1064 - csr_matvec.c:298-300 - exec	0	0
○Loop 1063 - csr_matvec.c:298-300 - exec	0	0
▼Loop 1053 - csr_matvec.c:373-380 - exec–	0	0
○Loop 1054 - csr_matvec.c:376-378 - exec	0	0
○Loop 1055 - csr_matvec.c:376-378 - exec	0	0
▼Loop 1074 - csr_matvec.c:385-392 - exec–	0	0
○Loop 1075 - csr_matvec.c:388-390 - exec	0	0
○Loop 1076 - csr_matvec.c:388-390 - exec	0	0
▼Loop 1059 - csr_matvec.c:268-275 - exec–	0	0
○Loop 1060 - csr_matvec.c:271-273 - exec	0	0
○Loop 1061 - csr_matvec.c:271-273 - exec	0	0
▼Loop 1068 - csr_matvec.c:280-287 - exec–	0	0
○Loop 1069 - csr_matvec.c:283-285 - exec	0	0
○Loop 1070 - csr_matvec.c:283-285 - exec	0	0
▼Loop 1071 - csr_matvec.c:397-404 - exec–	0	0
○Loop 1073 - csr_matvec.c:400-402 - exec	0	0
○Loop 1072 - csr_matvec.c:400-402 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code