OV - exec - Function .omp_outlined..6#0x469040

	Function: .omp_outlined..6#0x469040	Module: exec	Source: par_strength.c:1253-1278	Coverage: 0.09%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 1253 - 1278

--------------------------------------------------------------------------------

1253: #pragma omp parallel private(i)

1254: #endif

1255:    {

1256:       HYPRE_Int num_coarse_private = 0;

1257:

1258:       HYPRE_Int i_begin, i_end;

1259:       hypre_GetSimpleThreadPartition(&i_begin, &i_end, num_cols_diag_S);

1260:

1261:       for (i = i_begin; i < i_end; i++)

1262:       {

1263:          if (CF_marker[i] > 0) num_coarse_private++;

1264:       }

1265:

1266:       hypre_prefix_sum(&num_coarse_private, &num_coarse, num_coarse_prefix_sum);

1267:

1268:       for (i = i_begin; i < i_end; i++)

1269:       {

1270:          if (CF_marker[i] > 0)

1271:          {

1272:             fine_to_coarse[i] = num_coarse_private;

1273:             coarse_to_fine[num_coarse_private] = i;

1274:             num_coarse_private++;

1275:          }

1276:          else

1277:          {

1278:             fine_to_coarse[i] = -1;

0x469040 SUB	SP, SP, #80

0x469044 STP	X29, X30, [SP, #16]

0x469048 STR	X23, [SP, #32]

0x46904c STP	X22, X21, [SP, #48]

0x469050 STP	X20, X19, [SP, #64]

0x469054 ADD	X29, SP, #16

0x469058 LDR	X2, [X2]

0x46905c ADD	X0, SP, #8

0x469060 ADD	X1, SP, #0

0x469064 ORR	X19, XZR, X7

0x469068 ORR	X20, XZR, X6

0x46906c STR	XZR, [X29, #24]

0x469070 ORR	X23, XZR, X5

0x469074 ORR	X22, XZR, X4

0x469078 ORR	X21, XZR, X3

0x46907c BL	4b0600

0x469080 LDP	X11, X8, [SP]

0x469084 SUBS	X9, X11, X8

0x469088 B.LE	4690b8

0x46908c LDR	X10, [X21]

0x469090 ADD	X12, X8, #1

0x469094 CMP	X11, X12

0x469098 B.NE	46914c

0x46909c ORR	X11, XZR, XZR

(700) 0x4690a0 TBZ	W9, #0, 4690b8

(700) 0x4690a4 LDR	X8, [X10, X8,LSL #3]

(700) 0x4690a8 CMP	X8, #1

(700) 0x4690ac B.LT	4690b8

(700) 0x4690b0 ADD	X8, X11, #1

(700) 0x4690b4 STR	X8, [X29, #24]

(700) 0x4690b8 LDR	X2, [X23]

(700) 0x4690bc ORR	X1, XZR, X22

(700) 0x4690c0 ADD	X0, X29, #24

(700) 0x4690c4 BL	4b1100

(700) 0x4690c8 LDP	X9, X8, [SP]

(700) 0x4690cc CMP	X8, X9

(700) 0x4690d0 B.GE	469134

(700) 0x4690d4 LDR	X9, [X21]

(700) 0x4690d8 LDR	X10, [X20]

(700) 0x4690dc LDR	X11, [X19]

(700) 0x4690e0 MOVN	X12, #0

(700) 0x4690e4 B	4690fc

  (701) 0x4690e8 STR	X12, [X10, X8,LSL #3]

  (701) 0x4690ec LDR	X13, [SP]

  (701) 0x4690f0 ADD	X8, X8, #1

  (701) 0x4690f4 CMP	X8, X13

  (701) 0x4690f8 B.GE	469134

  (701) 0x4690fc LDR	X13, [X9, X8,LSL #3]

  (701) 0x469100 CMP	X13, #1

  (701) 0x469104 B.LT	4690e8

  (701) 0x469108 LDR	X13, [X29, #24]

  (701) 0x46910c STR	X13, [X10, X8,LSL #3]

  (701) 0x469110 LDR	X13, [X29, #24]

  (701) 0x469114 STR	X8, [X11, X13,LSL #3]

  (701) 0x469118 LDR	X13, [X29, #24]

  (701) 0x46911c ADD	X13, X13, #1

  (701) 0x469120 STR	X13, [X29, #24]

  (701) 0x469124 LDR	X13, [SP]

  (701) 0x469128 ADD	X8, X8, #1

  (701) 0x46912c CMP	X8, X13

  (701) 0x469130 B.LT	4690fc

(700) 0x469134 LDP	X20, X19, [SP, #64]

(700) 0x469138 LDP	X22, X21, [SP, #48]

(700) 0x46913c LDR	X23, [SP, #32]

(700) 0x469140 LDP	X29, X30, [SP, #16]

(700) 0x469144 ADD	SP, SP, #80

(700) 0x469148 RET

(700) 0x46914c ORR	X11, XZR, XZR

(700) 0x469150 AND	X12, X9, #8127

(700) 0x469154 B	46916c

0x469158 HINT	#0

0x46915c HINT	#0

(700) 0x469160 ADD	X8, X8, #2

(700) 0x469164 SUBS	X12, X12, #2

(700) 0x469168 B.EQ	4690a0

(700) 0x46916c LDR	X13, [X10, X8,LSL #3]

(700) 0x469170 CMP	X13, #1

(700) 0x469174 B.LT	469180

(700) 0x469178 ADD	X11, X11, #1

(700) 0x46917c STR	X11, [X29, #24]

(700) 0x469180 ADD	X13, X10, X8,LSL #3

(700) 0x469184 LDR	X13, [X13, #8]

(700) 0x469188 CMP	X13, #1

(700) 0x46918c B.LT	469160

(700) 0x469190 ADD	X11, X11, #1

(700) 0x469194 STR	X11, [X29, #24]

(700) 0x469198 B	469160

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	par_strength.c:1253-1278
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1253-1278.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 3.50 to 0.87 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.50 to 0.50 cycles (7.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 64 bytes.

General properties

nb instructions	26
loop length	104
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.50	3.50	3.50	3.50	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50
cycles	1.50	1.50	3.50	3.50	3.50	3.50	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.00
Overall L1	3.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.50 cycles. At this rate:

9% of peak load performance is reached (9.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
38% of peak store performance is reached (18.29 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 469040

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X23, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X2, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, SP, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR XZR, [X29, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b0600 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SUBS X9, X11, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4690b8 <.omp_outlined..6+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 46914c <.omp_outlined..6+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X11, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0

Source file and lines	par_strength.c:1253-1278
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1253-1278.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.50 to 0.50 cycles (7.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 64 bytes.

General properties

nb instructions	26
loop length	104
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.50	3.50	3.50	3.50	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50
cycles	1.50	1.50	3.50	3.50	3.50	3.50	0.00	0.00	0.00	0.00	2.83	2.50	2.67	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.00
Overall L1	3.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.50 cycles. At this rate:

9% of peak load performance is reached (9.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
38% of peak store performance is reached (18.29 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 469040

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X23, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X2, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, SP, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR XZR, [X29, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b0600 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SUBS X9, X11, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4690b8 <.omp_outlined..6+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 46914c <.omp_outlined..6+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X11, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..6#0x469040–	0.09	0.03
▼Loop 700 - par_strength.c:1253-1278 - exec–	0.02	0
○Loop 701 - par_strength.c:1268-1278 - exec	0.07	0.02

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code