OV - exec - Function .omp_outlined..2#0x4664a0

	Function: .omp_outlined..2#0x4664a0	Module: exec	Source: par_strength.c:246-513 [...]	Coverage: 3.58%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 246 - 513

--------------------------------------------------------------------------------

246: #pragma omp parallel private(i,diag,row_scale,row_sum,jA,jS)

247: #endif

248:    {

249:    HYPRE_Int start, stop;

250:    hypre_GetSimpleThreadPartition(&start, &stop, num_variables);

251:    HYPRE_Int jS_diag = 0, jS_offd = 0;

252:

253:    for (i = start; i < stop; i++)

254:    {

255:       S_diag_i[i] = jS_diag;

256:       if (num_cols_offd)

257:       {

258:          S_offd_i[i] = jS_offd;

259:       }

260:

261:       diag = A_diag_data[A_diag_i[i]];

262:

263:       /* compute scaling factor and row sum */

264:       row_scale = 0.0;

265:       row_sum = diag;

266:       if (num_functions > 1)

267:       {

268:          if (diag < 0)

269:          {

270:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

271:             {

272:                if (dof_func[i] == dof_func[A_diag_j[jA]])

273:                {

274:                   row_scale = hypre_max(row_scale, A_diag_data[jA]);

275:                   row_sum += A_diag_data[jA];

276:                }

277:             }

278:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

279:             {

280:                if (dof_func[i] == dof_func_offd[A_offd_j[jA]])

281:                {

282:                   row_scale = hypre_max(row_scale, A_offd_data[jA]);

283:                   row_sum += A_offd_data[jA];

[...]

289:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

290:             {

291:                if (dof_func[i] == dof_func[A_diag_j[jA]])

292:                {

293:                   row_scale = hypre_min(row_scale, A_diag_data[jA]);

294:                   row_sum += A_diag_data[jA];

295:                }

296:             }

297:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

298:             {

299:                if (dof_func[i] == dof_func_offd[A_offd_j[jA]])

300:                {

301:                   row_scale = hypre_min(row_scale, A_offd_data[jA]);

302:                   row_sum += A_offd_data[jA];

[...]

309:          if (diag < 0)

310:          {

311:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

312:             {

313:                row_scale = hypre_max(row_scale, A_diag_data[jA]);

314:                row_sum += A_diag_data[jA];

315:             }

316:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

317:             {

318:                row_scale = hypre_max(row_scale, A_offd_data[jA]);

319:                row_sum += A_offd_data[jA];

320:             }

321:          }

322:          else

323:          {

324:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

325:             {

326:                row_scale = hypre_min(row_scale, A_diag_data[jA]);

327:                row_sum += A_diag_data[jA];

328:             }

329:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

330:             {

331:                row_scale = hypre_min(row_scale, A_offd_data[jA]);

332:                row_sum += A_offd_data[jA];

333:             }

334:          } /* diag >= 0*/

335:       } /* num_functions <= 1 */

336:

337:       jS_diag += A_diag_i[i + 1] - A_diag_i[i] - 1;

338:       jS_offd += A_offd_i[i + 1] - A_offd_i[i];

339:

340:       /* compute row entries of S */

341:       S_temp_diag_j[A_diag_i[i]] = -1;

342:       if ((fabs(row_sum) > fabs(diag)*max_row_sum) && (max_row_sum < 1.0))

343:       {

344:          /* make all dependencies weak */

345:          for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

346:          {

347:             S_temp_diag_j[jA] = -1;

348:          }

349:          jS_diag -= A_diag_i[i + 1] - (A_diag_i[i] + 1);

350:

351:          for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

352:          {

353:             S_temp_offd_j[jA] = -1;

354:          }

355:          jS_offd -= A_offd_i[i + 1] - A_offd_i[i];

356:       }

357:       else

358:       {

359:          if (num_functions > 1)

360:          {

361:             if (diag < 0)

362:             {

363:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

364:                {

365:                   if (A_diag_data[jA] <= strength_threshold * row_scale

366:                       || dof_func[i] != dof_func[A_diag_j[jA]])

367:                   {

368:                      S_temp_diag_j[jA] = -1;

369:                      --jS_diag;

370:                   }

371:                   else

372:                   {

373:                      S_temp_diag_j[jA] = A_diag_j[jA];

374:                   }

375:                }

376:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

377:                {

378:                   if (A_offd_data[jA] <= strength_threshold * row_scale

379:                       || dof_func[i] != dof_func_offd[A_offd_j[jA]])

380:                   {

381:                      S_temp_offd_j[jA] = -1;

382:                      --jS_offd;

383:                   }

384:                   else

385:                   {

386:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

392:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

393:                {

394:                   if (A_diag_data[jA] >= strength_threshold * row_scale

395:                       || dof_func[i] != dof_func[A_diag_j[jA]])

396:                   {

397:                      S_temp_diag_j[jA] = -1;

398:                      --jS_diag;

399:                   }

400:                   else

401:                   {

402:                      S_temp_diag_j[jA] = A_diag_j[jA];

403:                   }

404:                }

405:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

406:                {

407:                   if (A_offd_data[jA] >= strength_threshold * row_scale

408:                       || dof_func[i] != dof_func_offd[A_offd_j[jA]])

409:                   {

410:                      S_temp_offd_j[jA] = -1;

411:                      --jS_offd;

412:                   }

413:                   else

414:                   {

415:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

422:             if (diag < 0)

423:             {

424:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

425:                {

426:                   if (A_diag_data[jA] <= strength_threshold * row_scale)

427:                   {

428:                      S_temp_diag_j[jA] = -1;

429:                      --jS_diag;

430:                   }

431:                   else

432:                   {

433:                      S_temp_diag_j[jA] = A_diag_j[jA];

434:                   }

435:                }

436:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

437:                {

438:                   if (A_offd_data[jA] <= strength_threshold * row_scale)

439:                   {

440:                      S_temp_offd_j[jA] = -1;

441:                      --jS_offd;

442:                   }

443:                   else

444:                   {

445:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

451:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

452:                {

453:                   if (A_diag_data[jA] >= strength_threshold * row_scale)

454:                   {

455:                      S_temp_diag_j[jA] = -1;

456:                      --jS_diag;

457:                   }

458:                   else

459:                   {

460:                      S_temp_diag_j[jA] = A_diag_j[jA];

461:                   }

462:                }

463:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

464:                {

465:                   if (A_offd_data[jA] >= strength_threshold * row_scale)

466:                   {

467:                      S_temp_offd_j[jA] = -1;

468:                      --jS_offd;

469:                   }

470:                   else

471:                   {

472:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

480:    hypre_prefix_sum_pair(&jS_diag, S_diag_i + num_variables, &jS_offd, S_offd_i + num_variables, prefix_sum_workspace);

[...]

492:    for (i = start; i < stop; i++)

493:    {

494:       S_diag_i[i] += jS_diag;

495:       S_offd_i[i] += jS_offd;

496:

497:       jS = S_diag_i[i];

498:       for (jA = A_diag_i[i]; jA < A_diag_i[i+1]; jA++)

499:       {

500:          if (S_temp_diag_j[jA] > -1)

501:          {

502:             S_diag_j[jS]    = S_temp_diag_j[jA];

503:             jS++;

504:          }

505:       }

506:

507:       jS = S_offd_i[i];

508:       for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

509:       {

510:          if (S_temp_offd_j[jA] > -1)

511:          {

512:             S_offd_j[jS]    = S_temp_offd_j[jA];

513:             jS++;

0x4664a0 SUB	SP, SP, #240

0x4664a4 STP	X29, X30, [SP, #144]

0x4664a8 STP	X28, X27, [SP, #160]

0x4664ac STP	X26, X25, [SP, #176]

0x4664b0 STP	X24, X23, [SP, #192]

0x4664b4 STP	X22, X21, [SP, #208]

0x4664b8 STP	X20, X19, [SP, #224]

0x4664bc ADD	X29, SP, #144

0x4664c0 ORR	X22, XZR, X2

0x4664c4 LDR	X2, [X2]

0x4664c8 LDR	X28, [X29, #184]

0x4664cc LDR	X25, [X29, #168]

0x4664d0 SUB	X0, X29, #8

0x4664d4 SUB	X1, X29, #16

0x4664d8 ORR	X19, XZR, X7

0x4664dc ORR	X24, XZR, X6

0x4664e0 LDR	X27, [X29, #152]

0x4664e4 LDR	X26, [X29, #120]

0x4664e8 ORR	X20, XZR, X5

0x4664ec ORR	X23, XZR, X4

0x4664f0 ORR	X21, XZR, X3

0x4664f4 BL	4b0600

0x4664f8 LDP	X9, X11, [X29, #1008]

0x4664fc LDR	X8, [X21]

0x466500 STP	XZR, XZR, [X29, #992]

0x466504 CMP	X11, X9

0x466508 B.GE	467120

0x46650c LDP	X10, X9, [X29, #136]

0x466510 LDP	X14, X13, [X29, #104]

0x466514 LDR	X3, [X29, #176]

0x466518 MOVI	D2, #0

0x46651c FMOV	D3, #1.0000000

0x466520 LDR	X7, [X29, #160]

0x466524 LDR	X17, [X24]

0x466528 LDR	X12, [X29, #128]

0x46652c STP	X20, X19, [SP, #40]

0x466530 LDR	X18, [X19]

0x466534 LDR	X15, [X29, #96]

0x466538 LDR	X16, [X20]

0x46653c LDR	X0, [X26]

0x466540 LDR	X6, [X27]

0x466544 STR	X28, [SP, #8]

0x466548 MOVN	X28, #0

0x46654c STR	X21, [SP, #32]

0x466550 STP	X27, X26, [SP, #16]

0x466554 LDR	X1, [X9]

0x466558 LDR	X5, [X13]

0x46655c LDR	D0, [X7]

0x466560 LDR	D1, [X3]

0x466564 ADD	X3, X17, #16

0x466568 LDR	X19, [X10]

0x46656c LDR	X2, [X14]

0x466570 LDR	X4, [X12]

0x466574 LDR	X7, [X25]

0x466578 STP	X3, X19, [X29, #968]

0x46657c ADD	X3, X1, #16

0x466580 STUR	X5, [X29, #472]

0x466584 STUR	X3, [X29, #448]

0x466588 ADD	X3, X5, #8

0x46658c STR	X3, [SP, #72]

0x466590 ADD	X5, X17, #8

0x466594 ADD	X3, X19, #8

0x466598 STP	X3, X5, [SP, #56]

0x46659c B	4665bc

    (610) 0x4665a0 SUB	X3, X19, X3

    (610) 0x4665a4 LDUR	X19, [X29, #480]

    (610) 0x4665a8 ADD	X3, X3, X19

    (610) 0x4665ac STUR	X3, [X29, #480]

    (610) 0x4665b0 LDUR	X3, [X29, #496]

    (610) 0x4665b4 CMP	X11, X3

    (610) 0x4665b8 B.GE	467114

    (610) 0x4665bc ORR	X21, XZR, X11

    (610) 0x4665c0 LDUR	X11, [X29, #488]

    (610) 0x4665c4 STR	X11, [X8, X21,LSL #3]

    (610) 0x4665c8 LDR	X11, [X23]

    (610) 0x4665cc CBZ	X11, 4665d8

    (610) 0x4665d0 LDUR	X11, [X29, #480]

    (610) 0x4665d4 STR	X11, [X16, X21,LSL #3]

    (610) 0x4665d8 LDR	X24, [X18, X21,LSL #3]

    (610) 0x4665dc LDR	X3, [X15]

    (610) 0x4665e0 ADD	X11, X21, #1

    (610) 0x4665e4 MOVI	D4, #0

    (610) 0x4665e8 LDR	X30, [X18, X11,LSL #3]

    (610) 0x4665ec LDR	D5, [X17, X24,LSL #3]

    (610) 0x4665f0 ADD	X26, X24, #1

    (610) 0x4665f4 CMP	X3, #2

    (610) 0x4665f8 B.LT	466640

    (610) 0x4665fc FCMP	D5, #0

    (610) 0x466600 B.PL	4667a4

    (610) 0x466604 FMOV	D6, D5

    (610) 0x466608 CMP	X26, X30

    (610) 0x46660c B.GE	466960

    (610) 0x466610 LDR	X27, [X2, X21,LSL #3]

    (610) 0x466614 ORN	W3, WZR, W24

    (610) 0x466618 MOVI	D4, #0

    (610) 0x46661c SUB	X19, X30, #2

    (610) 0x466620 ADD	W3, W30, W3

    (610) 0x466624 TBNZ	W3, #0, 466924

    (610) 0x466628 FMOV	D6, D5

    (610) 0x46662c CMP	X19, X24

    (610) 0x466630 B.EQ	466960

    (610) 0x466634 B	4669fc

0x466638 HINT	#0

0x46663c HINT	#0

    (610) 0x466640 FCMP	D5, #0

    (610) 0x466644 B.PL	4667e0

    (610) 0x466648 FMOV	D6, D5

    (610) 0x46664c CMP	X26, X30

    (610) 0x466650 B.GE	466700

    (610) 0x466654 ORN	W3, WZR, W24

    (610) 0x466658 SUB	X19, X30, X24

    (610) 0x46665c MOVI	D4, #0

    (610) 0x466660 FMOV	D6, D5

    (610) 0x466664 SUB	X19, X19, #2

    (610) 0x466668 ADD	W3, W30, W3

    (610) 0x46666c ANDS	X20, X3, #4160

    (610) 0x466670 B.EQ	46669c

    (610) 0x466674 HINT	#0

    (610) 0x466678 HINT	#0

    (610) 0x46667c HINT	#0

      (618) 0x466680 LDR	D7, [X17, X26,LSL #3]

      (618) 0x466684 ADD	X26, X26, #1

      (618) 0x466688 FCMP	D4, D7

      (618) 0x46668c FADD	D6, D6, D7

      (618) 0x466690 FCSEL	D4, D7, D4, #4

      (618) 0x466694 SUBS	X20, X20, #1

      (618) 0x466698 B.NE	466680

    (610) 0x46669c CMP	X19, #3

    (610) 0x4666a0 B.CC	466700

    (610) 0x4666a4 LDUR	X3, [X29, #456]

    (610) 0x4666a8 SUB	X19, X30, X26

    (610) 0x4666ac ADD	X20, X3, X26,LSL #3

    (610) 0x4666b0 HINT	#0

    (610) 0x4666b4 HINT	#0

    (610) 0x4666b8 HINT	#0

    (610) 0x4666bc HINT	#0

      (617) 0x4666c0 LDP	D7, D16, [X20, #1008]

      (617) 0x4666c4 FCMP	D4, D7

      (617) 0x4666c8 FADD	D6, D6, D7

      (617) 0x4666cc FCSEL	D4, D7, D4, #4

      (617) 0x4666d0 FADD	D6, D6, D16

      (617) 0x4666d4 FCMP	D4, D16

      (617) 0x4666d8 FCSEL	D4, D16, D4, #4

      (617) 0x4666dc LDP	D7, D16, [X20], #32

      (617) 0x4666e0 FCMP	D4, D7

      (617) 0x4666e4 FADD	D6, D6, D7

      (617) 0x4666e8 FCSEL	D4, D7, D4, #4

      (617) 0x4666ec FADD	D6, D6, D16

      (617) 0x4666f0 FCMP	D4, D16

      (617) 0x4666f4 FCSEL	D4, D16, D4, #4

      (617) 0x4666f8 SUBS	X19, X19, #4

      (617) 0x4666fc B.NE	4666c0

    (610) 0x466700 LDR	X20, [X0, X21,LSL #3]

    (610) 0x466704 LDR	X19, [X0, X11,LSL #3]

    (610) 0x466708 CMP	X19, X20

    (610) 0x46670c B.LE	466c28

    (610) 0x466710 SUB	W3, W19, W20

    (610) 0x466714 ORR	X26, XZR, X20

    (610) 0x466718 ANDS	X27, X3, #4160

    (610) 0x46671c B.EQ	46673c

      (616) 0x466720 LDR	D7, [X1, X26,LSL #3]

      (616) 0x466724 ADD	X26, X26, #1

      (616) 0x466728 FCMP	D4, D7

      (616) 0x46672c FADD	D6, D6, D7

      (616) 0x466730 FCSEL	D4, D7, D4, #4

      (616) 0x466734 SUBS	X27, X27, #1

      (616) 0x466738 B.NE	466720

    (610) 0x46673c ORN	X3, XZR, X20

    (610) 0x466740 ADD	X3, X19, X3

    (610) 0x466744 CMP	X3, #3

    (610) 0x466748 B.CC	466c28

    (610) 0x46674c LDUR	X3, [X29, #448]

    (610) 0x466750 SUB	X19, X19, X26

    (610) 0x466754 ADD	X20, X3, X26,LSL #3

    (610) 0x466758 HINT	#0

    (610) 0x46675c HINT	#0

      (615) 0x466760 LDP	D7, D16, [X20, #1008]

      (615) 0x466764 FCMP	D4, D7

      (615) 0x466768 FADD	D6, D6, D7

      (615) 0x46676c FCSEL	D4, D7, D4, #4

      (615) 0x466770 FADD	D6, D6, D16

      (615) 0x466774 FCMP	D4, D16

      (615) 0x466778 FCSEL	D4, D16, D4, #4

      (615) 0x46677c LDP	D7, D16, [X20], #32

      (615) 0x466780 FCMP	D4, D7

      (615) 0x466784 FADD	D6, D6, D7

      (615) 0x466788 FCSEL	D4, D7, D4, #4

      (615) 0x46678c FADD	D6, D6, D16

      (615) 0x466790 FCMP	D4, D16

      (615) 0x466794 FCSEL	D4, D16, D4, #4

      (615) 0x466798 SUBS	X19, X19, #4

      (615) 0x46679c B.NE	466760

    (610) 0x4667a0 B	466c28

    (610) 0x4667a4 FMOV	D6, D5

    (610) 0x4667a8 CMP	X26, X30

    (610) 0x4667ac B.GE	4669c8

    (610) 0x4667b0 LDR	X27, [X2, X21,LSL #3]

    (610) 0x4667b4 ORN	W3, WZR, W24

    (610) 0x4667b8 MOVI	D4, #0

    (610) 0x4667bc SUB	X19, X30, #2

    (610) 0x4667c0 ADD	W3, W30, W3

    (610) 0x4667c4 TBNZ	W3, #0, 466994

    (610) 0x4667c8 FMOV	D6, D5

    (610) 0x4667cc CMP	X19, X24

    (610) 0x4667d0 B.EQ	4669c8

    (610) 0x4667d4 B	466b54

0x4667d8 HINT	#0

0x4667dc HINT	#0

    (610) 0x4667e0 FMOV	D6, D5

    (610) 0x4667e4 CMP	X26, X30

    (610) 0x4667e8 B.GE	466880

    (610) 0x4667ec ORN	W3, WZR, W24

    (610) 0x4667f0 SUB	X19, X30, X24

    (610) 0x4667f4 MOVI	D4, #0

    (610) 0x4667f8 FMOV	D6, D5

    (610) 0x4667fc SUB	X19, X19, #2

    (610) 0x466800 ADD	W3, W30, W3

    (610) 0x466804 ANDS	X20, X3, #4160

    (610) 0x466808 B.EQ	466828

      (614) 0x46680c LDR	D7, [X17, X26,LSL #3]

      (614) 0x466810 ADD	X26, X26, #1

      (614) 0x466814 FCMP	D4, D7

      (614) 0x466818 FADD	D6, D6, D7

      (614) 0x46681c FCSEL	D4, D4, D7, #4

      (614) 0x466820 SUBS	X20, X20, #1

      (614) 0x466824 B.NE	46680c

    (610) 0x466828 CMP	X19, #3

    (610) 0x46682c B.CC	466880

    (610) 0x466830 LDUR	X3, [X29, #456]

    (610) 0x466834 SUB	X19, X30, X26

    (610) 0x466838 ADD	X20, X3, X26,LSL #3

    (610) 0x46683c HINT	#0

      (613) 0x466840 LDP	D7, D16, [X20, #1008]

      (613) 0x466844 FCMP	D4, D7

      (613) 0x466848 FADD	D6, D6, D7

      (613) 0x46684c FCSEL	D4, D4, D7, #4

      (613) 0x466850 FADD	D6, D6, D16

      (613) 0x466854 FCMP	D4, D16

      (613) 0x466858 FCSEL	D4, D4, D16, #4

      (613) 0x46685c LDP	D7, D16, [X20], #32

      (613) 0x466860 FCMP	D4, D7

      (613) 0x466864 FADD	D6, D6, D7

      (613) 0x466868 FCSEL	D4, D4, D7, #4

      (613) 0x46686c FADD	D6, D6, D16

      (613) 0x466870 FCMP	D4, D16

      (613) 0x466874 FCSEL	D4, D4, D16, #4

      (613) 0x466878 SUBS	X19, X19, #4

      (613) 0x46687c B.NE	466840

    (610) 0x466880 LDR	X20, [X0, X21,LSL #3]

    (610) 0x466884 LDR	X19, [X0, X11,LSL #3]

    (610) 0x466888 CMP	X19, X20

    (610) 0x46688c B.LE	466c28

    (610) 0x466890 SUB	W3, W19, W20

    (610) 0x466894 ORR	X26, XZR, X20

    (610) 0x466898 ANDS	X27, X3, #4160

    (610) 0x46689c B.EQ	4668bc

      (612) 0x4668a0 LDR	D7, [X1, X26,LSL #3]

      (612) 0x4668a4 ADD	X26, X26, #1

      (612) 0x4668a8 FCMP	D4, D7

      (612) 0x4668ac FADD	D6, D6, D7

      (612) 0x4668b0 FCSEL	D4, D4, D7, #4

      (612) 0x4668b4 SUBS	X27, X27, #1

      (612) 0x4668b8 B.NE	4668a0

    (610) 0x4668bc ORN	X3, XZR, X20

    (610) 0x4668c0 ADD	X3, X19, X3

    (610) 0x4668c4 CMP	X3, #3

    (610) 0x4668c8 B.CC	466c28

    (610) 0x4668cc LDUR	X3, [X29, #448]

    (610) 0x4668d0 SUB	X19, X19, X26

    (610) 0x4668d4 ADD	X20, X3, X26,LSL #3

    (610) 0x4668d8 HINT	#0

    (610) 0x4668dc HINT	#0

      (611) 0x4668e0 LDP	D7, D16, [X20, #1008]

      (611) 0x4668e4 FCMP	D4, D7

      (611) 0x4668e8 FADD	D6, D6, D7

      (611) 0x4668ec FCSEL	D4, D4, D7, #4

      (611) 0x4668f0 FADD	D6, D6, D16

      (611) 0x4668f4 FCMP	D4, D16

      (611) 0x4668f8 FCSEL	D4, D4, D16, #4

      (611) 0x4668fc LDP	D7, D16, [X20], #32

      (611) 0x466900 FCMP	D4, D7

      (611) 0x466904 FADD	D6, D6, D7

      (611) 0x466908 FCSEL	D4, D4, D7, #4

      (611) 0x46690c FADD	D6, D6, D16

      (611) 0x466910 FCMP	D4, D16

      (611) 0x466914 FCSEL	D4, D4, D16, #4

      (611) 0x466918 SUBS	X19, X19, #4

      (611) 0x46691c B.NE	4668e0

    (610) 0x466920 B	466c28

    (610) 0x466924 LDUR	X3, [X29, #472]

    (610) 0x466928 MOVI	D4, #0

    (610) 0x46692c FMOV	D6, D5

    (610) 0x466930 LDR	X3, [X3, X26,LSL #3]

    (610) 0x466934 LDR	X3, [X2, X3,LSL #3]

    (610) 0x466938 CMP	X27, X3

    (610) 0x46693c B.NE	46694c

    (610) 0x466940 LDR	D6, [X17, X26,LSL #3]

    (610) 0x466944 FMAXNM	D4, D6, D2

    (610) 0x466948 FADD	D6, D5, D6

    (610) 0x46694c ADD	X26, X24, #2

    (610) 0x466950 CMP	X19, X24

    (610) 0x466954 B.NE	4669fc

    (610) 0x466958 HINT	#0

    (610) 0x46695c HINT	#0

    (610) 0x466960 LDR	X27, [X0, X21,LSL #3]

    (610) 0x466964 LDR	X19, [X0, X11,LSL #3]

    (610) 0x466968 CMP	X19, X27

    (610) 0x46696c B.LE	466c28

    (610) 0x466970 LDR	X26, [X2, X21,LSL #3]

    (610) 0x466974 LDR	X20, [X9]

    (610) 0x466978 SUB	W3, W19, W27

    (610) 0x46697c TBNZ	W3, #0, 466a94

    (610) 0x466980 ORR	X3, XZR, X27

    (610) 0x466984 ADD	X27, X27, #1

    (610) 0x466988 CMP	X19, X27

    (610) 0x46698c B.NE	466ac8

    (610) 0x466990 B	466c28

    (610) 0x466994 LDUR	X3, [X29, #472]

    (610) 0x466998 MOVI	D4, #0

    (610) 0x46699c FMOV	D6, D5

    (610) 0x4669a0 LDR	X3, [X3, X26,LSL #3]

    (610) 0x4669a4 LDR	X3, [X2, X3,LSL #3]

    (610) 0x4669a8 CMP	X27, X3

    (610) 0x4669ac B.NE	4669bc

    (610) 0x4669b0 LDR	D6, [X17, X26,LSL #3]

    (610) 0x4669b4 FMIN	D4, D6, D2

    (610) 0x4669b8 FADD	D6, D5, D6

    (610) 0x4669bc ADD	X26, X24, #2

    (610) 0x4669c0 CMP	X19, X24

    (610) 0x4669c4 B.NE	466b54

    (610) 0x4669c8 LDR	X27, [X0, X21,LSL #3]

    (610) 0x4669cc LDR	X19, [X0, X11,LSL #3]

    (610) 0x4669d0 CMP	X19, X27

    (610) 0x4669d4 B.LE	466c28

    (610) 0x4669d8 LDR	X26, [X2, X21,LSL #3]

    (610) 0x4669dc LDR	X20, [X9]

    (610) 0x4669e0 SUB	W3, W19, W27

    (610) 0x4669e4 TBNZ	W3, #0, 466bf4

    (610) 0x4669e8 ORR	X3, XZR, X27

    (610) 0x4669ec ADD	X27, X27, #1

    (610) 0x4669f0 CMP	X19, X27

    (610) 0x4669f4 B.EQ	466c28

  (620) 0x4669f8 B	467074

    (610) 0x4669fc LDR	X5, [SP, #72]

    (610) 0x466a00 UBFM	X3, X26, #61, #60

    (610) 0x466a04 SUB	X19, X30, X26

    (610) 0x466a08 ADD	X26, X5, X3

    (610) 0x466a0c LDR	X5, [SP, #64]

    (610) 0x466a10 ADD	X20, X5, X3

    (610) 0x466a14 B	466a30

0x466a18 HINT	#0

0x466a1c HINT	#0

      (623) 0x466a20 SUBS	X19, X19, #2

      (623) 0x466a24 ADD	X26, X26, #16

      (623) 0x466a28 ADD	X20, X20, #16

      (623) 0x466a2c B.EQ	466960

      (623) 0x466a30 LDUR	X3, [X26, #504]

      (623) 0x466a34 LDR	X3, [X2, X3,LSL #3]

      (623) 0x466a38 CMP	X27, X3

      (623) 0x466a3c B.EQ	466a60

      (623) 0x466a40 LDR	X3, [X26]

      (623) 0x466a44 LDR	X3, [X2, X3,LSL #3]

      (623) 0x466a48 CMP	X27, X3

      (623) 0x466a4c B.NE	466a20

      (623) 0x466a50 B	466a80

0x466a54 HINT	#0

0x466a58 HINT	#0

0x466a5c HINT	#0

      (623) 0x466a60 LDUR	D7, [X20, #504]

      (623) 0x466a64 FCMP	D4, D7

      (623) 0x466a68 FADD	D6, D6, D7

      (623) 0x466a6c FCSEL	D4, D7, D4, #4

      (623) 0x466a70 LDR	X3, [X26]

      (623) 0x466a74 LDR	X3, [X2, X3,LSL #3]

      (623) 0x466a78 CMP	X27, X3

      (623) 0x466a7c B.NE	466a20

      (623) 0x466a80 LDR	D7, [X20]

      (623) 0x466a84 FCMP	D4, D7

      (623) 0x466a88 FADD	D6, D6, D7

      (623) 0x466a8c FCSEL	D4, D7, D4, #4

      (623) 0x466a90 B	466a20

    (610) 0x466a94 LDUR	X3, [X29, #464]

    (610) 0x466a98 LDR	X3, [X3, X27,LSL #3]

    (610) 0x466a9c LDR	X3, [X4, X3,LSL #3]

    (610) 0x466aa0 CMP	X26, X3

    (610) 0x466aa4 B.NE	466ab8

    (610) 0x466aa8 LDR	D7, [X20, X27,LSL #3]

    (610) 0x466aac FCMP	D4, D7

    (610) 0x466ab0 FADD	D6, D6, D7

    (610) 0x466ab4 FCSEL	D4, D7, D4, #4

    (610) 0x466ab8 ADD	X3, X27, #1

    (610) 0x466abc ADD	X27, X27, #1

    (610) 0x466ac0 CMP	X19, X27

    (610) 0x466ac4 B.EQ	466c28

    (610) 0x466ac8 LDR	X5, [SP, #56]

    (610) 0x466acc SUB	X27, X19, X3

    (610) 0x466ad0 UBFM	X3, X3, #61, #60

    (610) 0x466ad4 ADD	X19, X5, X3

    (610) 0x466ad8 ADD	X3, X20, X3

    (610) 0x466adc ADD	X20, X3, #8

    (610) 0x466ae0 B	466af4

      (622) 0x466ae4 SUBS	X27, X27, #2

      (622) 0x466ae8 ADD	X19, X19, #16

      (622) 0x466aec ADD	X20, X20, #16

      (622) 0x466af0 B.EQ	466c28

      (622) 0x466af4 LDUR	X3, [X19, #504]

      (622) 0x466af8 LDR	X3, [X4, X3,LSL #3]

      (622) 0x466afc CMP	X26, X3

      (622) 0x466b00 B.EQ	466b20

      (622) 0x466b04 LDR	X3, [X19]

      (622) 0x466b08 LDR	X3, [X4, X3,LSL #3]

      (622) 0x466b0c CMP	X26, X3

      (622) 0x466b10 B.NE	466ae4

      (622) 0x466b14 B	466b40

0x466b18 HINT	#0

0x466b1c HINT	#0

      (622) 0x466b20 LDUR	D7, [X20, #504]

      (622) 0x466b24 FCMP	D4, D7

      (622) 0x466b28 FADD	D6, D6, D7

      (622) 0x466b2c FCSEL	D4, D7, D4, #4

      (622) 0x466b30 LDR	X3, [X19]

      (622) 0x466b34 LDR	X3, [X4, X3,LSL #3]

      (622) 0x466b38 CMP	X26, X3

      (622) 0x466b3c B.NE	466ae4

      (622) 0x466b40 LDR	D7, [X20]

      (622) 0x466b44 FCMP	D4, D7

      (622) 0x466b48 FADD	D6, D6, D7

      (622) 0x466b4c FCSEL	D4, D7, D4, #4

      (622) 0x466b50 B	466ae4

    (610) 0x466b54 LDR	X5, [SP, #72]

    (610) 0x466b58 UBFM	X3, X26, #61, #60

    (610) 0x466b5c SUB	X19, X30, X26

    (610) 0x466b60 ADD	X26, X5, X3

    (610) 0x466b64 LDR	X5, [SP, #64]

    (610) 0x466b68 ADD	X20, X5, X3

    (610) 0x466b6c B	466b90

0x466b70 HINT	#0

0x466b74 HINT	#0

0x466b78 HINT	#0

0x466b7c HINT	#0

      (621) 0x466b80 SUBS	X19, X19, #2

      (621) 0x466b84 ADD	X26, X26, #16

      (621) 0x466b88 ADD	X20, X20, #16

      (621) 0x466b8c B.EQ	4669c8

      (621) 0x466b90 LDUR	X3, [X26, #504]

      (621) 0x466b94 LDR	X3, [X2, X3,LSL #3]

      (621) 0x466b98 CMP	X27, X3

      (621) 0x466b9c B.EQ	466bc0

      (621) 0x466ba0 LDR	X3, [X26]

      (621) 0x466ba4 LDR	X3, [X2, X3,LSL #3]

      (621) 0x466ba8 CMP	X27, X3

      (621) 0x466bac B.NE	466b80

      (621) 0x466bb0 B	466be0

0x466bb4 HINT	#0

0x466bb8 HINT	#0

0x466bbc HINT	#0

      (621) 0x466bc0 LDUR	D7, [X20, #504]

      (621) 0x466bc4 FCMP	D4, D7

      (621) 0x466bc8 FADD	D6, D6, D7

      (621) 0x466bcc FCSEL	D4, D4, D7, #4

      (621) 0x466bd0 LDR	X3, [X26]

      (621) 0x466bd4 LDR	X3, [X2, X3,LSL #3]

      (621) 0x466bd8 CMP	X27, X3

      (621) 0x466bdc B.NE	466b80

      (621) 0x466be0 LDR	D7, [X20]

      (621) 0x466be4 FCMP	D4, D7

      (621) 0x466be8 FADD	D6, D6, D7

      (621) 0x466bec FCSEL	D4, D4, D7, #4

      (621) 0x466bf0 B	466b80

    (610) 0x466bf4 LDUR	X3, [X29, #464]

    (610) 0x466bf8 LDR	X3, [X3, X27,LSL #3]

    (610) 0x466bfc LDR	X3, [X4, X3,LSL #3]

    (610) 0x466c00 CMP	X26, X3

    (610) 0x466c04 B.NE	466c18

    (610) 0x466c08 LDR	D7, [X20, X27,LSL #3]

    (610) 0x466c0c FCMP	D4, D7

    (610) 0x466c10 FADD	D6, D6, D7

    (610) 0x466c14 FCSEL	D4, D4, D7, #4

    (610) 0x466c18 ADD	X3, X27, #1

    (610) 0x466c1c ADD	X27, X27, #1

    (610) 0x466c20 CMP	X19, X27

    (610) 0x466c24 B.NE	467074

    (610) 0x466c28 ORN	X3, XZR, X24

    (610) 0x466c2c LDUR	X19, [X29, #488]

    (610) 0x466c30 FCMP	D0, D3

    (610) 0x466c34 ADD	X3, X30, X3

    (610) 0x466c38 ADD	X3, X3, X19

    (610) 0x466c3c STUR	X3, [X29, #488]

    (610) 0x466c40 LDR	X3, [X0, X11,LSL #3]

    (610) 0x466c44 LDR	X19, [X0, X21,LSL #3]

    (610) 0x466c48 SUB	X3, X3, X19

    (610) 0x466c4c LDUR	X19, [X29, #480]

    (610) 0x466c50 ADD	X3, X3, X19

    (610) 0x466c54 STUR	X3, [X29, #480]

    (610) 0x466c58 LDR	X3, [X18, X21,LSL #3]

    (610) 0x466c5c STR	X28, [X6, X3,LSL #3]

    (610) 0x466c60 B.PL	466ce4

    (610) 0x466c64 FABS	D7, D5

    (610) 0x466c68 FABS	D6, D6

    (610) 0x466c6c FMUL	D7, D0, D7

    (610) 0x466c70 FCMP	D6, D7

    (610) 0x466c74 B.LE	466ce4

    (610) 0x466c78 LDR	X3, [X18, X21,LSL #3]

    (610) 0x466c7c ADD	X19, X3, #1

    (610) 0x466c80 LDR	X3, [X18, X11,LSL #3]

    (610) 0x466c84 CMP	X19, X3

    (610) 0x466c88 B.GE	466ca8

      (633) 0x466c8c STR	X28, [X6, X19,LSL #3]

      (633) 0x466c90 ADD	X19, X19, #1

      (633) 0x466c94 LDR	X3, [X18, X11,LSL #3]

      (633) 0x466c98 CMP	X19, X3

      (633) 0x466c9c B.LT	466c8c

    (610) 0x466ca0 LDR	X19, [X18, X21,LSL #3]

    (610) 0x466ca4 ADD	X19, X19, #1

    (610) 0x466ca8 LDUR	X20, [X29, #488]

    (610) 0x466cac SUB	X3, X19, X3

    (610) 0x466cb0 ADD	X3, X3, X20

    (610) 0x466cb4 STUR	X3, [X29, #488]

    (610) 0x466cb8 LDR	X19, [X0, X21,LSL #3]

    (610) 0x466cbc LDR	X3, [X0, X11,LSL #3]

    (610) 0x466cc0 CMP	X19, X3

    (610) 0x466cc4 B.GE	4665a0

      (632) 0x466cc8 STR	X28, [X7, X19,LSL #3]

      (632) 0x466ccc ADD	X19, X19, #1

      (632) 0x466cd0 LDR	X3, [X0, X11,LSL #3]

      (632) 0x466cd4 CMP	X19, X3

      (632) 0x466cd8 B.LT	466cc8

    (610) 0x466cdc LDR	X19, [X0, X21,LSL #3]

    (610) 0x466ce0 B	4665a0

    (610) 0x466ce4 LDR	X3, [X18, X21,LSL #3]

    (610) 0x466ce8 LDR	X19, [X15]

    (610) 0x466cec ADD	X24, X3, #1

    (610) 0x466cf0 LDR	X3, [X18, X11,LSL #3]

    (610) 0x466cf4 CMP	X19, #2

    (610) 0x466cf8 B.LT	466e00

    (610) 0x466cfc FCMP	D5, #0

    (610) 0x466d00 B.PL	466ecc

    (610) 0x466d04 CMP	X24, X3

    (610) 0x466d08 B.GE	466d74

    (610) 0x466d0c LDR	X19, [X14]

    (610) 0x466d10 LDR	X20, [X13]

    (610) 0x466d14 FMUL	D5, D1, D4

    (610) 0x466d18 B	466d40

0x466d1c HINT	#0

      (631) 0x466d20 STR	X28, [X6, X24,LSL #3]

      (631) 0x466d24 LDUR	X3, [X29, #488]

      (631) 0x466d28 SUB	X3, X3, #1

      (631) 0x466d2c STUR	X3, [X29, #488]

      (631) 0x466d30 LDR	X3, [X18, X11,LSL #3]

      (631) 0x466d34 ADD	X24, X24, #1

      (631) 0x466d38 CMP	X24, X3

      (631) 0x466d3c B.GE	466d74

      (631) 0x466d40 LDR	D6, [X17, X24,LSL #3]

      (631) 0x466d44 FCMP	D6, D5

      (631) 0x466d48 B.LS	466d20

      (631) 0x466d4c LDR	X3, [X20, X24,LSL #3]

      (631) 0x466d50 LDR	X26, [X19, X21,LSL #3]

      (631) 0x466d54 LDR	X27, [X19, X3,LSL #3]

      (631) 0x466d58 CMP	X26, X27

      (631) 0x466d5c B.NE	466d20

      (631) 0x466d60 STR	X3, [X6, X24,LSL #3]

      (631) 0x466d64 LDR	X3, [X18, X11,LSL #3]

      (631) 0x466d68 ADD	X24, X24, #1

      (631) 0x466d6c CMP	X24, X3

      (631) 0x466d70 B.LT	466d40

    (610) 0x466d74 LDR	X19, [X0, X21,LSL #3]

    (610) 0x466d78 LDR	X3, [X0, X11,LSL #3]

    (610) 0x466d7c CMP	X19, X3

    (610) 0x466d80 B.GE	4665b0

    (610) 0x466d84 LDR	X20, [X14]

    (610) 0x466d88 LDR	X24, [X12]

    (610) 0x466d8c LDR	X26, [X10]

    (610) 0x466d90 FMUL	D4, D1, D4

    (610) 0x466d94 LDR	X27, [X25]

    (610) 0x466d98 B	466dc0

0x466d9c HINT	#0

      (630) 0x466da0 STR	X28, [X27, X19,LSL #3]

      (630) 0x466da4 LDUR	X3, [X29, #480]

      (630) 0x466da8 SUB	X3, X3, #1

      (630) 0x466dac STUR	X3, [X29, #480]

      (630) 0x466db0 LDR	X3, [X0, X11,LSL #3]

      (630) 0x466db4 ADD	X19, X19, #1

      (630) 0x466db8 CMP	X19, X3

      (630) 0x466dbc B.GE	4665b0

      (630) 0x466dc0 LDR	D5, [X1, X19,LSL #3]

      (630) 0x466dc4 FCMP	D5, D4

      (630) 0x466dc8 B.LS	466da0

      (630) 0x466dcc LDR	X3, [X26, X19,LSL #3]

      (630) 0x466dd0 LDR	X30, [X20, X21,LSL #3]

      (630) 0x466dd4 LDR	X5, [X24, X3,LSL #3]

      (630) 0x466dd8 CMP	X30, X5

      (630) 0x466ddc B.NE	466da0

      (630) 0x466de0 STR	X3, [X27, X19,LSL #3]

      (630) 0x466de4 LDR	X3, [X0, X11,LSL #3]

      (630) 0x466de8 ADD	X19, X19, #1

      (630) 0x466dec CMP	X19, X3

      (630) 0x466df0 B.LT	466dc0

    (610) 0x466df4 B	4665b0

0x466df8 HINT	#0

0x466dfc HINT	#0

    (610) 0x466e00 FCMP	D5, #0

    (610) 0x466e04 B.PL	466fb8

    (610) 0x466e08 CMP	X24, X3

    (610) 0x466e0c B.GE	466e64

    (610) 0x466e10 LDR	X19, [X13]

    (610) 0x466e14 FMUL	D5, D1, D4

    (610) 0x466e18 B	466e38

0x466e1c HINT	#0

      (627) 0x466e20 LDR	X3, [X19, X24,LSL #3]

      (627) 0x466e24 STR	X3, [X6, X24,LSL #3]

      (627) 0x466e28 LDR	X3, [X18, X11,LSL #3]

      (627) 0x466e2c ADD	X24, X24, #1

      (627) 0x466e30 CMP	X24, X3

      (627) 0x466e34 B.GE	466e64

      (627) 0x466e38 LDR	D6, [X17, X24,LSL #3]

      (627) 0x466e3c FCMP	D6, D5

      (627) 0x466e40 B.HI	466e20

      (627) 0x466e44 STR	X28, [X6, X24,LSL #3]

      (627) 0x466e48 LDUR	X3, [X29, #488]

      (627) 0x466e4c SUB	X3, X3, #1

      (627) 0x466e50 STUR	X3, [X29, #488]

      (627) 0x466e54 LDR	X3, [X18, X11,LSL #3]

      (627) 0x466e58 ADD	X24, X24, #1

      (627) 0x466e5c CMP	X24, X3

      (627) 0x466e60 B.LT	466e38

    (610) 0x466e64 LDR	X19, [X0, X21,LSL #3]

    (610) 0x466e68 LDR	X3, [X0, X11,LSL #3]

    (610) 0x466e6c CMP	X19, X3

    (610) 0x466e70 B.GE	4665b0

    (610) 0x466e74 LDR	X20, [X25]

    (610) 0x466e78 LDR	X21, [X10]

    (610) 0x466e7c FMUL	D4, D1, D4

    (610) 0x466e80 B	466e9c

      (626) 0x466e84 LDR	X3, [X21, X19,LSL #3]

      (626) 0x466e88 STR	X3, [X20, X19,LSL #3]

      (626) 0x466e8c LDR	X3, [X0, X11,LSL #3]

      (626) 0x466e90 ADD	X19, X19, #1

      (626) 0x466e94 CMP	X19, X3

      (626) 0x466e98 B.GE	4665b0

      (626) 0x466e9c LDR	D5, [X1, X19,LSL #3]

      (626) 0x466ea0 FCMP	D5, D4

      (626) 0x466ea4 B.HI	466e84

      (626) 0x466ea8 STR	X28, [X20, X19,LSL #3]

      (626) 0x466eac LDUR	X3, [X29, #480]

      (626) 0x466eb0 SUB	X3, X3, #1

      (626) 0x466eb4 STUR	X3, [X29, #480]

      (626) 0x466eb8 LDR	X3, [X0, X11,LSL #3]

      (626) 0x466ebc ADD	X19, X19, #1

      (626) 0x466ec0 CMP	X19, X3

      (626) 0x466ec4 B.LT	466e9c

    (610) 0x466ec8 B	4665b0

    (610) 0x466ecc CMP	X24, X3

    (610) 0x466ed0 B.GE	466f38

    (610) 0x466ed4 LDR	X19, [X14]

    (610) 0x466ed8 LDR	X20, [X13]

    (610) 0x466edc FMUL	D5, D1, D4

    (610) 0x466ee0 B	466f04

      (629) 0x466ee4 STR	X28, [X6, X24,LSL #3]

      (629) 0x466ee8 LDUR	X3, [X29, #488]

      (629) 0x466eec SUB	X3, X3, #1

      (629) 0x466ef0 STUR	X3, [X29, #488]

      (629) 0x466ef4 LDR	X3, [X18, X11,LSL #3]

      (629) 0x466ef8 ADD	X24, X24, #1

      (629) 0x466efc CMP	X24, X3

      (629) 0x466f00 B.GE	466f38

      (629) 0x466f04 LDR	D6, [X17, X24,LSL #3]

      (629) 0x466f08 FCMP	D6, D5

      (629) 0x466f0c B.GE	466ee4

      (629) 0x466f10 LDR	X3, [X20, X24,LSL #3]

      (629) 0x466f14 LDR	X5, [X19, X21,LSL #3]

      (629) 0x466f18 LDR	X26, [X19, X3,LSL #3]

      (629) 0x466f1c CMP	X5, X26

      (629) 0x466f20 B.NE	466ee4

      (629) 0x466f24 STR	X3, [X6, X24,LSL #3]

      (629) 0x466f28 LDR	X3, [X18, X11,LSL #3]

      (629) 0x466f2c ADD	X24, X24, #1

      (629) 0x466f30 CMP	X24, X3

      (629) 0x466f34 B.LT	466f04

    (610) 0x466f38 LDR	X19, [X0, X21,LSL #3]

    (610) 0x466f3c LDR	X3, [X0, X11,LSL #3]

    (610) 0x466f40 CMP	X19, X3

    (610) 0x466f44 B.GE	4665b0

    (610) 0x466f48 LDR	X20, [X14]

    (610) 0x466f4c LDR	X24, [X12]

    (610) 0x466f50 LDR	X26, [X10]

    (610) 0x466f54 FMUL	D4, D1, D4

    (610) 0x466f58 LDR	X27, [X25]

    (610) 0x466f5c B	466f80

      (628) 0x466f60 STR	X28, [X27, X19,LSL #3]

      (628) 0x466f64 LDUR	X3, [X29, #480]

      (628) 0x466f68 SUB	X3, X3, #1

      (628) 0x466f6c STUR	X3, [X29, #480]

      (628) 0x466f70 LDR	X3, [X0, X11,LSL #3]

      (628) 0x466f74 ADD	X19, X19, #1

      (628) 0x466f78 CMP	X19, X3

      (628) 0x466f7c B.GE	4665b0

      (628) 0x466f80 LDR	D5, [X1, X19,LSL #3]

      (628) 0x466f84 FCMP	D5, D4

      (628) 0x466f88 B.GE	466f60

      (628) 0x466f8c LDR	X3, [X26, X19,LSL #3]

      (628) 0x466f90 LDR	X5, [X20, X21,LSL #3]

      (628) 0x466f94 LDR	X30, [X24, X3,LSL #3]

      (628) 0x466f98 CMP	X5, X30

      (628) 0x466f9c B.NE	466f60

      (628) 0x466fa0 STR	X3, [X27, X19,LSL #3]

      (628) 0x466fa4 LDR	X3, [X0, X11,LSL #3]

      (628) 0x466fa8 ADD	X19, X19, #1

      (628) 0x466fac CMP	X19, X3

      (628) 0x466fb0 B.LT	466f80

    (610) 0x466fb4 B	4665b0

    (610) 0x466fb8 FMUL	D4, D1, D4

    (610) 0x466fbc CMP	X24, X3

    (610) 0x466fc0 B.GE	467010

    (610) 0x466fc4 LDR	X19, [X13]

    (610) 0x466fc8 B	466fe4

      (625) 0x466fcc LDR	X3, [X19, X24,LSL #3]

      (625) 0x466fd0 STR	X3, [X6, X24,LSL #3]

      (625) 0x466fd4 LDR	X3, [X18, X11,LSL #3]

      (625) 0x466fd8 ADD	X24, X24, #1

      (625) 0x466fdc CMP	X24, X3

      (625) 0x466fe0 B.GE	467010

      (625) 0x466fe4 LDR	D5, [X17, X24,LSL #3]

      (625) 0x466fe8 FCMP	D5, D4

      (625) 0x466fec B.LT	466fcc

      (625) 0x466ff0 STR	X28, [X6, X24,LSL #3]

      (625) 0x466ff4 LDUR	X3, [X29, #488]

      (625) 0x466ff8 SUB	X3, X3, #1

      (625) 0x466ffc STUR	X3, [X29, #488]

      (625) 0x467000 LDR	X3, [X18, X11,LSL #3]

      (625) 0x467004 ADD	X24, X24, #1

      (625) 0x467008 CMP	X24, X3

      (625) 0x46700c B.LT	466fe4

    (610) 0x467010 LDR	X19, [X0, X21,LSL #3]

    (610) 0x467014 LDR	X3, [X0, X11,LSL #3]

    (610) 0x467018 CMP	X19, X3

    (610) 0x46701c B.GE	4665b0

    (610) 0x467020 LDR	X20, [X25]

    (610) 0x467024 LDR	X21, [X10]

    (610) 0x467028 B	467044

      (624) 0x46702c LDR	X3, [X21, X19,LSL #3]

      (624) 0x467030 STR	X3, [X20, X19,LSL #3]

      (624) 0x467034 LDR	X3, [X0, X11,LSL #3]

      (624) 0x467038 ADD	X19, X19, #1

      (624) 0x46703c CMP	X19, X3

      (624) 0x467040 B.GE	4665b0

      (624) 0x467044 LDR	D5, [X1, X19,LSL #3]

      (624) 0x467048 FCMP	D5, D4

      (624) 0x46704c B.LT	46702c

      (624) 0x467050 STR	X28, [X20, X19,LSL #3]

      (624) 0x467054 LDUR	X3, [X29, #480]

      (624) 0x467058 SUB	X3, X3, #1

      (624) 0x46705c STUR	X3, [X29, #480]

      (624) 0x467060 LDR	X3, [X0, X11,LSL #3]

      (624) 0x467064 ADD	X19, X19, #1

      (624) 0x467068 CMP	X19, X3

      (624) 0x46706c B.LT	467044

    (610) 0x467070 B	4665b0

  (620) 0x467074 LDR	X5, [SP, #56]

  (620) 0x467078 SUB	X27, X19, X3

  (620) 0x46707c UBFM	X3, X3, #61, #60

  (620) 0x467080 ADD	X19, X5, X3

  (620) 0x467084 ADD	X3, X20, X3

  (620) 0x467088 ADD	X20, X3, #8

  (620) 0x46708c B	4670b0

0x467090 HINT	#0

0x467094 HINT	#0

0x467098 HINT	#0

0x46709c HINT	#0

  (620) 0x4670a0 SUBS	X27, X27, #2

  (620) 0x4670a4 ADD	X19, X19, #16

  (620) 0x4670a8 ADD	X20, X20, #16

  (620) 0x4670ac B.EQ	466c28

  (620) 0x4670b0 LDUR	X3, [X19, #504]

  (620) 0x4670b4 LDR	X3, [X4, X3,LSL #3]

  (620) 0x4670b8 CMP	X26, X3

  (620) 0x4670bc B.EQ	4670e0

  (620) 0x4670c0 LDR	X3, [X19]

  (620) 0x4670c4 LDR	X3, [X4, X3,LSL #3]

  (620) 0x4670c8 CMP	X26, X3

  (620) 0x4670cc B.NE	4670a0

  (620) 0x4670d0 B	467100

0x4670d4 HINT	#0

0x4670d8 HINT	#0

0x4670dc HINT	#0

(619) 0x4670e0 LDUR	D7, [X20, #504]

(619) 0x4670e4 FCMP	D4, D7

(619) 0x4670e8 FADD	D6, D6, D7

(619) 0x4670ec FCSEL	D4, D4, D7, #4

(619) 0x4670f0 LDR	X3, [X19]

(619) 0x4670f4 LDR	X3, [X4, X3,LSL #3]

(619) 0x4670f8 CMP	X26, X3

(619) 0x4670fc B.NE	4670a0

  (620) 0x467100 LDR	D7, [X20]

  (620) 0x467104 FCMP	D4, D7

  (620) 0x467108 FADD	D6, D6, D7

  (620) 0x46710c FCSEL	D4, D4, D7, #4

  (620) 0x467110 B	4670a0

0x467114 LDP	X20, X19, [SP, #40]

0x467118 LDP	X26, X21, [SP, #24]

0x46711c LDP	X28, X27, [SP, #8]

0x467120 LDR	X9, [X22]

0x467124 LDR	X4, [X28]

0x467128 SUB	X0, X29, #24

0x46712c SUB	X2, X29, #32

0x467130 UBFM	X9, X9, #61, #60

0x467134 ADD	X1, X8, X9

0x467138 LDR	X8, [X20]

0x46713c ADD	X3, X8, X9

0x467140 BL	4b1270

0x467144 LDP	X8, X10, [X29, #1008]

0x467148 CMP	X10, X8

0x46714c B.GE	467244

0x467150 LDP	X9, X8, [X29, #192]

0x467154 LDR	X11, [X21]

0x467158 LDR	X12, [X20]

0x46715c LDR	X13, [X19]

0x467160 LDR	X14, [X27]

0x467164 LDR	X15, [X26]

0x467168 LDR	X16, [X25]

0x46716c B	46718c

0x467170 HINT	#0

0x467174 HINT	#0

0x467178 HINT	#0

0x46717c HINT	#0

  (607) 0x467180 LDUR	X17, [X29, #496]

  (607) 0x467184 CMP	X10, X17

  (607) 0x467188 B.GE	467244

  (607) 0x46718c ORR	X17, XZR, X10

  (607) 0x467190 LDUR	X10, [X29, #488]

  (607) 0x467194 LDR	X18, [X11, X17,LSL #3]

  (607) 0x467198 ADD	X10, X18, X10

  (607) 0x46719c STR	X10, [X11, X17,LSL #3]

  (607) 0x4671a0 LDUR	X10, [X29, #480]

  (607) 0x4671a4 LDR	X18, [X12, X17,LSL #3]

  (607) 0x4671a8 ADD	X10, X18, X10

  (607) 0x4671ac STR	X10, [X12, X17,LSL #3]

  (607) 0x4671b0 ADD	X10, X17, #1

  (607) 0x4671b4 LDR	X18, [X13, X17,LSL #3]

  (607) 0x4671b8 LDR	X0, [X13, X10,LSL #3]

  (607) 0x4671bc CMP	X18, X0

  (607) 0x4671c0 B.GE	467204

(608) 0x4671c4 LDR	X1, [X11, X17,LSL #3]

(608) 0x4671c8 LDR	X2, [X9]

(608) 0x4671cc B	4671ec

0x4671d0 HINT	#0

0x4671d4 HINT	#0

0x4671d8 HINT	#0

0x4671dc HINT	#0

(608) 0x4671e0 ADD	X18, X18, #1

(608) 0x4671e4 CMP	X18, X0

(608) 0x4671e8 B.GE	467204

(608) 0x4671ec LDR	X3, [X14, X18,LSL #3]

(608) 0x4671f0 TBNZ	X3, #63, 4671e0

(608) 0x4671f4 STR	X3, [X2, X1,LSL #3]

(608) 0x4671f8 ADD	X1, X1, #1

(608) 0x4671fc LDR	X0, [X13, X10,LSL #3]

(608) 0x467200 B	4671e0

  (607) 0x467204 LDR	X18, [X15, X17,LSL #3]

  (607) 0x467208 LDR	X0, [X15, X10,LSL #3]

  (607) 0x46720c CMP	X18, X0

  (607) 0x467210 B.GE	467180

  (607) 0x467214 LDR	X17, [X12, X17,LSL #3]

  (607) 0x467218 LDR	X1, [X8]

  (607) 0x46721c B	46722c

    (609) 0x467220 ADD	X18, X18, #1

    (609) 0x467224 CMP	X18, X0

    (609) 0x467228 B.GE	467180

    (609) 0x46722c LDR	X2, [X16, X18,LSL #3]

    (609) 0x467230 TBNZ	X2, #63, 467220

    (609) 0x467234 STR	X2, [X1, X17,LSL #3]

    (609) 0x467238 ADD	X17, X17, #1

    (609) 0x46723c LDR	X0, [X15, X10,LSL #3]

    (609) 0x467240 B	467220

0x467244 LDP	X20, X19, [SP, #224]

0x467248 LDP	X22, X21, [SP, #208]

0x46724c LDP	X24, X23, [SP, #192]

0x467250 LDP	X26, X25, [SP, #176]

0x467254 LDP	X28, X27, [SP, #160]

0x467258 LDP	X29, X30, [SP, #144]

0x46725c ADD	SP, SP, #240

0x467260 RET

0x467264 HINT	#0

0x467268 HINT	#0

0x46726c HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	par_strength.c:246-513
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:246-283,289-302,309-386,392-415,422-445,451-472,480,492-513.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 20.67 to 0.67 cycles (31.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 20.67 to 5.17 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.67 to 1.00 cycles (20.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 480 bytes. The binary function is storing 216 bytes.

General properties

nb instructions	136
loop length	544
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	6.50	6.50	6.50	6.50	0.50	0.50	0.50	0.50	20.67	20.67	20.67	8.00	8.00
cycles	3.50	3.50	6.50	6.50	6.50	6.50	0.50	0.50	0.50	0.50	20.67	20.67	20.67	8.00	8.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.88
Overall L1	20.67

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.67 cycles. At this rate:

24% of peak load performance is reached (23.23 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
21% of peak store performance is reached (10.45 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4664a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X2, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X0, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X1, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X24, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X27, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X20, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X23, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b0600 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X9, X11, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP XZR, XZR, [X29, #992]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X11, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 467120 <.omp_outlined..2+0xc80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X10, X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X14, X13, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X3, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVI D2, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D3, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR X7, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X20, X19, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X28, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVN X28, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, X26, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X1, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D0, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D1, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X3, X17, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X19, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X3, X19, [X29, #968]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, X1, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X5, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X3, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X3, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X5, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X19, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X3, X5, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4665bc <.omp_outlined..2+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDP X20, X19, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X21, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X0, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X2, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X9, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b1270 <hypre_prefix_sum_pair>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X10, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 467244 <.omp_outlined..2+0xda4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X9, X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X11, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 46718c <.omp_outlined..2+0xcec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDP X20, X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Source file and lines	par_strength.c:246-513
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.67 to 1.00 cycles (20.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 480 bytes. The binary function is storing 216 bytes.

General properties

nb instructions	136
loop length	544
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	6.50	6.50	6.50	6.50	0.50	0.50	0.50	0.50	20.67	20.67	20.67	8.00	8.00
cycles	3.50	3.50	6.50	6.50	6.50	6.50	0.50	0.50	0.50	0.50	20.67	20.67	20.67	8.00	8.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.88
Overall L1	20.67

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.67 cycles. At this rate:

24% of peak load performance is reached (23.23 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
21% of peak store performance is reached (10.45 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4664a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X2, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X0, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X1, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X24, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X27, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X20, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X23, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b0600 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X9, X11, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP XZR, XZR, [X29, #992]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X11, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 467120 <.omp_outlined..2+0xc80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X10, X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X14, X13, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X3, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVI D2, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D3, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR X7, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X20, X19, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X28, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVN X28, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, X26, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X1, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D0, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D1, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X3, X17, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X19, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X3, X19, [X29, #968]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, X1, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X5, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X3, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X3, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X5, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X19, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X3, X5, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4665bc <.omp_outlined..2+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDP X20, X19, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X21, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X0, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X2, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X9, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b1270 <hypre_prefix_sum_pair>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X10, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 467244 <.omp_outlined..2+0xda4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X9, X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X11, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 46718c <.omp_outlined..2+0xcec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDP X20, X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..2#0x4664a0–	3.58	1.36
▼Loop 608 - par_strength.c:492-513 - exec–	1.45	0.47
▼Loop 607 - par_strength.c:492-513 - exec–	0.07	0.02
○Loop 609 - par_strength.c:508-513 - exec	0	0
▼Loop 619 - par_strength.c:253-472 - exec–	0	0
▼Loop 620 - par_strength.c:253-472 - exec–	0	0
▼Loop 610 - par_strength.c:253-472 - exec–	0.19	0.06
○Loop 625 - par_strength.c:451-460 - exec	1.82	0.59
○Loop 613 - par_strength.c:324-327 - exec	0.05	0.02
○Loop 617 - par_strength.c:311-314 - exec	0	0
○Loop 632 - par_strength.c:351-353 - exec	0	0
○Loop 623 - par_strength.c:270-275 - exec	0	0
○Loop 622 - par_strength.c:278-283 - exec	0	0
○Loop 614 - par_strength.c:324-327 - exec	0	0.01
○Loop 626 - par_strength.c:436-445 - exec	0	0
○Loop 611 - par_strength.c:329-332 - exec	0	0
○Loop 628 - par_strength.c:405-415 - exec	0	0
○Loop 616 - par_strength.c:316-319 - exec	0	0
○Loop 612 - par_strength.c:329-332 - exec	0	0
○Loop 629 - par_strength.c:392-402 - exec	0	0
○Loop 618 - par_strength.c:311-314 - exec	0	0
○Loop 631 - par_strength.c:363-373 - exec	0	0
○Loop 633 - par_strength.c:345-347 - exec	0	0
○Loop 621 - par_strength.c:289-294 - exec	0	0
○Loop 630 - par_strength.c:376-386 - exec	0	0
○Loop 627 - par_strength.c:424-433 - exec	0	0
○Loop 624 - par_strength.c:463-472 - exec	0	0
○Loop 615 - par_strength.c:316-319 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code