OV - exec - Function .omp_outlined..21#0x49d090

	Function: .omp_outlined..21#0x49d090	Module: exec	Source: IJMatrix_parcsr.c:3240-3484 [...]	Coverage: 3.64%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 3240 - 3484

--------------------------------------------------------------------------------

3240: #pragma omp parallel

[...]

3256:          num_threads = hypre_NumActiveThreads();

3257:          my_thread_num = hypre_GetThreadNum();

3258:

3259:          len = nrows/num_threads;

3260:          rest = nrows - len*num_threads;

3261:

3262:          if (my_thread_num < rest)

3263:          {

3264:             ns = my_thread_num*(len+1);

3265:             ne = (my_thread_num+1)*(len+1);

3266:          }

3267:          else

3268:          {

3269:             ns = my_thread_num*len+rest;

3270:             ne = (my_thread_num+1)*len+rest;

3271:          }

3272:

3273:          value_start[my_thread_num] = 0;

3274:          for (ii=ns; ii < ne; ii++)

3275:             value_start[my_thread_num] += ncols[ii];

3276:

3277: #ifdef HYPRE_USING_OPENMP

3278: #pragma omp barrier

3279: #endif

3280:          if (my_thread_num == 0)

3281:          {

3282:             for (i=0; i < max_num_threads; i++)

3283:                value_start[i+1] += value_start[i];

3284:          }

3285: #ifdef HYPRE_USING_OPENMP

3286: #pragma omp barrier

3287: #endif

3288:          indx = 0;

3289:          if (my_thread_num)

3290:             indx = value_start[my_thread_num-1];

3291:          for (ii=ns; ii < ne; ii++)

3292:          {

3293:             row = rows[ii];

3294:             n = ncols[ii];

3295:             /* processor owns the row */

3296:             if (row >= row_partitioning[pstart] && row < row_partitioning[pstart+1])

3297:             {

3298:                row_local = row - row_partitioning[pstart];

3299:                /* compute local row number */

3300:                if (need_aux)

3301:                {

3302:                   local_j = aux_j[row_local];

3303:                   local_data = aux_data[row_local];

3304:    	          space = row_space[row_local];

3305:    	          old_size = row_length[row_local];

3306:    	          size = space - old_size;

3307:    	          if (size < n)

3308:       	          {

3309:       	             size = n - size;

3310:       	             tmp_j = hypre_CTAlloc(HYPRE_Int,size);

3311:       	             tmp_data = hypre_CTAlloc(HYPRE_Complex,size);

3312:       	          }

3313:       	          tmp_indx = 0;

3314:       	          not_found = 1;

3315:       	          size = old_size;

3316:                   for (i=0; i < n; i++)

3317:       	          {

3318:       	             for (j=0; j < old_size; j++)

3319:       	             {

3320:       	                if (local_j[j] == cols[indx])

3321:       	                {

3322:                            local_data[j] = values[indx];

[...]

3329:       	                if (size < space)

3330:       	                {

3331:       	                   local_j[size] = cols[indx];

3332:       	                   local_data[size++] = values[indx];

3333:       	                }

3334:       	                else

3335:       	                {

3336:       	                   tmp_j[tmp_indx] = cols[indx];

3337:       	                   tmp_data[tmp_indx++] = values[indx];

3338:       	                }

3339:       	             }

3340:       	             not_found = 1;

3341:         	     indx++;

3342:       	          }

3343:

3344:                   row_length[row_local] = size+tmp_indx;

3345:

3346:                   if (tmp_indx)

3347:                   {

3348:    	             aux_j[row_local] = hypre_TReAlloc(aux_j[row_local],HYPRE_Int,

3349:                                                     size+tmp_indx);

3350:    	             aux_data[row_local] = hypre_TReAlloc(aux_data[row_local],

3351:                                                        HYPRE_Complex,size+tmp_indx);

3352:                      row_space[row_local] = size+tmp_indx;

[...]

3359:    	          for (i=0; i < tmp_indx; i++)

3360:    	          {

3361:    	             local_j[cnt] = tmp_j[i];

3362:    	             local_data[cnt++] = tmp_data[i];

3363: 	          }

3364:

3365: 	          if (tmp_j)

3366: 	          {

3367: 	             hypre_TFree(tmp_j);

3368: 	             hypre_TFree(tmp_data);

[...]

3376: 	          offd_indx = hypre_AuxParCSRMatrixIndxOffd(aux_matrix)[row_local];

3377: 	          diag_indx = hypre_AuxParCSRMatrixIndxDiag(aux_matrix)[row_local];

[...]

3383:   	          for (i=0; i < n; i++)

3384: 	          {

3385: 	             if (cols[indx] < col_0 || cols[indx] > col_n)

3386:                      /* insert into offd */

3387: 	             {

3388: 	                for (j=offd_i[row_local]; j < offd_indx; j++)

3389: 	                {

3390: 		           if (offd_j[j] == cols[indx])

[...]

3399: 	                   if (cnt_offd < offd_space)

3400: 	                   {

3401: 	                      offd_j[cnt_offd] = cols[indx];

3402: 	                      offd_data[cnt_offd++] = values[indx];

3403: 	                   }

3404: 	                   else

3405: 	 	           {

3406:                               hypre_error(HYPRE_ERROR_GENERIC);

3407: #ifdef HYPRE_USING_OPENMP

3408: #pragma omp atomic

3409: #endif

3410:                               error_flag++;

3411: 	    	              if (print_level)

[...]

3422: 	                for (j=diag_i[row_local]; j < diag_indx; j++)

3423: 	                {

3424: 		           if (diag_j[j] == cols[indx])

[...]

3433: 	                   if (cnt_diag < diag_space)

3434: 	                   {

3435: 	                      diag_j[cnt_diag] = cols[indx];

3436: 	                      diag_data[cnt_diag++] = values[indx];

3437: 	                   }

3438: 	                   else

3439: 	 	           {

3440:                               hypre_error(HYPRE_ERROR_GENERIC);

3441: #ifdef HYPRE_USING_OPENMP

3442: #pragma omp atomic

3443: #endif

3444:                               error_flag++;

3445: 	    	              if (print_level)

[...]

3454: 	             indx++;

3455: 	          }

3456:

3457:                   hypre_AuxParCSRMatrixIndxDiag(aux_matrix)[row_local] = cnt_diag;

3458:                   hypre_AuxParCSRMatrixIndxOffd(aux_matrix)[row_local] = cnt_offd;

[...]

3466:                indx +=  n;

3467:    	       if (aux_matrix)

3468:                {

3469:                   col_indx = 0;

3470:                   for (i=0; i < off_proc_i_indx; i=i+2)

3471:                   {

3472: 	             row_len = off_proc_i[i+1];

3473: 	             if (off_proc_i[i] == row)

3474: 		     {

3475: 		        for (j=0; j < n; j++)

3476: 		        {

3477: 			   cnt1 = col_indx;

3478: 			   for (k=0; k < row_len; k++)

3479: 			   {

3480: 			      if (off_proc_j[cnt1] == cols[j])

3481: 			      {

3482:                                  off_proc_j[cnt1++] = -1;

3483:                		         /*cancel_indx++;*/

3484: 	                         offproc_cnt[my_thread_num]++;

0x49d090 SUB	SP, SP, #352

0x49d094 STP	X29, X30, [SP, #256]

0x49d098 STP	X28, X27, [SP, #272]

0x49d09c STP	X26, X25, [SP, #288]

0x49d0a0 STP	X24, X23, [SP, #304]

0x49d0a4 STP	X22, X21, [SP, #320]

0x49d0a8 STP	X20, X19, [SP, #336]

0x49d0ac ADD	X29, SP, #256

0x49d0b0 ORR	X28, XZR, X7

0x49d0b4 STR	X6, [SP, #128]

0x49d0b8 ORR	X24, XZR, X5

0x49d0bc STUR	X4, [X29, #416]

0x49d0c0 ORR	X23, XZR, X3

0x49d0c4 ORR	X26, XZR, X2

0x49d0c8 ORR	X25, XZR, X0

0x49d0cc BL	4b05c0

0x49d0d0 ORR	X27, XZR, X0

0x49d0d4 BL	4b05e0

0x49d0d8 LDR	X8, [X26]

0x49d0dc ORR	X22, XZR, X0

0x49d0e0 CNTW	X17, ALL

0x49d0e4 SDIV	X10, X8, X27

0x49d0e8 MSUB	X11, X10, X27, X8

0x49d0ec ADD	X8, X0, #1

0x49d0f0 ADD	X13, X10, #1

0x49d0f4 MADD	X14, X13, X0, XZR

0x49d0f8 MADD	X12, X10, X8, X11

0x49d0fc MADD	X8, X13, X8, XZR

0x49d100 CMP	X0, X11

0x49d104 MADD	X9, X10, X0, X11

0x49d108 CSEL	X16, X12, X8, #10

0x49d10c LDR	X12, [X23]

0x49d110 CSEL	X26, X9, X14, #10

0x49d114 CMP	X26, X16

0x49d118 ADD	X8, X12, X0,LSL #3

0x49d11c STR	XZR, [X8]

0x49d120 B.GE	49d1f8

0x49d124 LDUR	X9, [X29, #416]

0x49d128 CMP	X22, X11

0x49d12c CSEL	X11, X22, X11, #11

0x49d130 CMP	X17, #16

0x49d134 MADD	X10, X22, X10, X11

0x49d138 MOVZ	W11, #16

0x49d13c CSEL	X11, X17, X11, #8

0x49d140 LDR	X9, [X9]

0x49d144 SUB	X10, X16, X10

0x49d148 CMP	X10, X11

0x49d14c B.CC	49d1d4

0x49d150 ADD	X11, X12, X22,LSL #3

0x49d154 ADD	X13, X9, X16,LSL #3

0x49d158 ADD	X11, X11, #8

0x49d15c ADD	X12, X9, X26,LSL #3

0x49d160 CMP	X8, X13

0x49d164 CCMP	X12, X11, #2, #3

0x49d168 B.CC	49d1d4

0x49d16c UDIV	X11, X10, X17

0x49d170 UBFM	X15, X26, #61, #60

0x49d174 DUP	Z0.D, #0

0x49d178 ORR	X12, XZR, XZR

0x49d17c PTRUE	P0.D, ALL

0x49d180 ADD	X14, X9, X15

0x49d184 ADDVL	X15, X15, #1

0x49d188 ORR	Z1.D, Z0.D, Z0.D

0x49d18c ADD	X15, X9, X15

0x49d190 MADD	X13, X11, X17, XZR

0x49d194 SUB	X11, X10, X13

0x49d198 ADD	X10, X26, X13

0x49d19c HINT	#0

(579) 0x49d1a0 LD1D	{Z2.D}, P0/Z, [X14, X12,LSL #3]

(579) 0x49d1a4 LD1D	{Z3.D}, P0/Z, [X15, X12,LSL #3]

(579) 0x49d1a8 ADD	X12, X12, X17

(579) 0x49d1ac CMP	X13, X12

(579) 0x49d1b0 ADD	Z0.D, Z2.D, Z0.D

(579) 0x49d1b4 ADD	Z1.D, Z3.D, Z1.D

(579) 0x49d1b8 B.NE	49d1a0

0x49d1bc ADD	Z0.D, Z1.D, Z0.D

0x49d1c0 UADDV	D0, P0, Z0.D

0x49d1c4 FMOV	X12, D0

0x49d1c8 STR	X12, [X8]

0x49d1cc CBNZ	X11, 49d1e0

0x49d1d0 B	49d1f8

0x49d1d4 ORR	X12, XZR, XZR

0x49d1d8 ORR	X10, XZR, X26

0x49d1dc HINT	#0

(578) 0x49d1e0 LDR	X11, [X9, X10,LSL #3]

(578) 0x49d1e4 ADD	X10, X10, #1

(578) 0x49d1e8 CMP	X10, X16

(578) 0x49d1ec ADD	X12, X11, X12

(578) 0x49d1f0 STR	X12, [X8]

(578) 0x49d1f4 B.LT	49d1e0

0x49d1f8 LDR	W25, [X25]

0x49d1fc ADRP	X0,

0x49d200 ADD	X0, X0, #3784

0x49d204 STUR	X16, [X29, #408]

0x49d208 ORR	W1, WZR, W25

0x49d20c BL	40f900

0x49d210 CBNZ	X22, 49d248

0x49d214 LDR	X8, [X24]

0x49d218 CMP	X8, #1

0x49d21c B.LT	49d248

0x49d220 LDR	X8, [X23]

0x49d224 ORR	X10, XZR, XZR

0x49d228 LDR	X9, [X8], #8

(577) 0x49d22c LDR	X11, [X8, X10,LSL #3]

(577) 0x49d230 ADD	X9, X11, X9

(577) 0x49d234 STR	X9, [X8, X10,LSL #3]

(577) 0x49d238 ADD	X10, X10, #1

(577) 0x49d23c LDR	X11, [X24]

(577) 0x49d240 CMP	X10, X11

(577) 0x49d244 B.LT	49d22c

0x49d248 ORR	W1, WZR, W25

0x49d24c ADRP	X0,

0x49d250 ADD	X0, X0, #3808

0x49d254 BL	40f900

0x49d258 CBZ	X22, 49d27c

0x49d25c LDR	X8, [X23]

0x49d260 ADD	X8, X8, X22,LSL #3

0x49d264 LDUR	X24, [X8, #504]

0x49d268 LDP	X30, X7, [X29, #920]

0x49d26c LDR	X23, [SP, #128]

0x49d270 CMP	X26, X30

0x49d274 B.LT	49d290

0x49d278 B	49db14

0x49d27c ORR	X24, XZR, XZR

0x49d280 LDP	X30, X7, [X29, #920]

0x49d284 LDR	X23, [SP, #128]

0x49d288 CMP	X26, X30

0x49d28c B.GE	49db14

0x49d290 LDR	X8, [X29, #256]

0x49d294 LDR	X9, [X29, #192]

0x49d298 LDP	X21, X19, [X29, #264]

0x49d29c MOVN	X27, #0

0x49d2a0 STUR	XZR, [X29, #464]

0x49d2a4 STP	X28, X8, [SP, #112]

0x49d2a8 LDP	X8, X5, [X29, #240]

0x49d2ac STR	X8, [SP, #72]

0x49d2b0 LDR	X8, [X29, #232]

0x49d2b4 STR	X8, [SP, #64]

0x49d2b8 LDR	X8, [X29, #224]

0x49d2bc STR	X8, [SP, #24]

0x49d2c0 LDR	X8, [X29, #216]

0x49d2c4 STR	X8, [SP, #16]

0x49d2c8 LDR	X8, [X29, #208]

0x49d2cc STR	X8, [SP, #56]

0x49d2d0 LDR	X8, [X29, #200]

0x49d2d4 STR	X8, [SP, #48]

0x49d2d8 LDR	X8, [X29, #184]

0x49d2dc STP	X8, X9, [X29, #1000]

0x49d2e0 LDR	X8, [X29, #176]

0x49d2e4 LDR	X9, [X29, #120]

0x49d2e8 STR	X8, [SP, #40]

0x49d2ec LDR	X8, [X29, #168]

0x49d2f0 STR	X9, [SP, #96]

0x49d2f4 LDR	X9, [X29, #112]

0x49d2f8 STR	X8, [SP, #32]

0x49d2fc LDP	X8, X11, [X29, #152]

0x49d300 STUR	X9, [X29, #400]

0x49d304 STR	X8, [SP, #88]

0x49d308 LDP	X8, X6, [X29, #136]

0x49d30c STUR	X11, [X29, #448]

0x49d310 STUR	X8, [X29, #424]

0x49d314 LDR	X8, [X29, #128]

0x49d318 STP	X5, X6, [X29, #984]

0x49d31c STR	X8, [SP, #104]

0x49d320 RDVL	X8, #1

0x49d324 UBFM	X8, X8, #4, #63

0x49d328 UBFM	X8, X8, #59, #58

0x49d32c STR	X8, [SP, #8]

0x49d330 LDP	X13, X8, [X29, #96]

0x49d334 STUR	X8, [X29, #392]

0x49d338 STP	X21, X13, [X29, #944]

0x49d33c B	49d378

  (571) 0x49d340 LDR	X28, [SP, #112]

  (571) 0x49d344 LDUR	X21, [X29, #432]

    (569) 0x49d348 ORR	X0, XZR, X2

    (569) 0x49d34c BL	4ae530

  (571) 0x49d350 LDUR	X0, [X29, #464]

  (571) 0x49d354 BL	4ae530

  (571) 0x49d358 LDUR	X6, [X29, #480]

  (571) 0x49d35c STUR	XZR, [X29, #464]

    (570) 0x49d360 LDP	X30, X7, [X29, #920]

    (570) 0x49d364 LDUR	X5, [X29, #472]

      (562) 0x49d368 LDP	X13, X11, [X29, #952]

        (561) 0x49d36c ADD	X26, X26, #1

        (561) 0x49d370 CMP	X26, X30

        (561) 0x49d374 B.GE	49db14

        (561) 0x49d378 LDR	X8, [X23]

        (561) 0x49d37c LDR	X9, [X13]

        (561) 0x49d380 LDR	X25, [X8, X26,LSL #3]

        (561) 0x49d384 LDR	X8, [X7]

        (561) 0x49d388 LDR	X20, [X8, X26,LSL #3]

        (561) 0x49d38c LDR	X8, [X28]

        (561) 0x49d390 LDR	X10, [X8, X9,LSL #3]

        (561) 0x49d394 SUBS	X16, X25, X10

        (561) 0x49d398 B.LT	49d460

        (561) 0x49d39c ADD	X8, X8, X9,LSL #3

        (561) 0x49d3a0 LDR	X8, [X8, #8]

        (561) 0x49d3a4 CMP	X25, X8

        (561) 0x49d3a8 B.GE	49d460

        (561) 0x49d3ac LDUR	X8, [X29, #392]

        (561) 0x49d3b0 STUR	X26, [X29, #456]

        (561) 0x49d3b4 LDR	X8, [X8]

        (561) 0x49d3b8 CBZ	X8, 49d5ac

    (570) 0x49d3bc LDUR	X8, [X29, #400]

    (570) 0x49d3c0 LDR	X8, [X8]

    (570) 0x49d3c4 LDR	X25, [X8, X16,LSL #3]

    (570) 0x49d3c8 LDR	X8, [SP, #96]

    (570) 0x49d3cc LDR	X8, [X8]

    (570) 0x49d3d0 LDR	X23, [X8, X16,LSL #3]

    (570) 0x49d3d4 LDR	X8, [SP, #104]

    (570) 0x49d3d8 LDR	X8, [X8]

    (570) 0x49d3dc LDR	X17, [X8, X16,LSL #3]

    (570) 0x49d3e0 LDUR	X8, [X29, #424]

    (570) 0x49d3e4 LDR	X8, [X8]

    (570) 0x49d3e8 LDR	X26, [X8, X16,LSL #3]

    (570) 0x49d3ec SUB	X8, X17, X26

    (570) 0x49d3f0 SUBS	X21, X20, X8

    (570) 0x49d3f4 B.LE	49d71c

    (570) 0x49d3f8 ORR	X0, XZR, X21

    (570) 0x49d3fc MOVZ	W1, #8

    (570) 0x49d400 STUR	X16, [X29, #464]

    (570) 0x49d404 STR	X17, [SP, #80]

    (570) 0x49d408 BL	4ae430

    (570) 0x49d40c ORR	X28, XZR, X0

    (570) 0x49d410 ORR	X0, XZR, X21

    (570) 0x49d414 MOVZ	W1, #8

    (570) 0x49d418 BL	4ae430

    (570) 0x49d41c LDR	X17, [SP, #80]

    (570) 0x49d420 ORR	X2, XZR, X28

    (570) 0x49d424 LDUR	X16, [X29, #464]

    (570) 0x49d428 LDR	X28, [SP, #112]

    (570) 0x49d42c LDUR	X6, [X29, #480]

    (570) 0x49d430 LDUR	X21, [X29, #432]

    (570) 0x49d434 CMP	X20, #0

    (570) 0x49d438 STUR	X0, [X29, #464]

    (570) 0x49d43c B.GT	49d734

    (570) 0x49d440 LDUR	X8, [X29, #424]

    (570) 0x49d444 LDR	X23, [SP, #128]

    (570) 0x49d448 LDR	X8, [X8]

    (570) 0x49d44c STR	X26, [X8, X16,LSL #3]

    (570) 0x49d450 LDUR	X26, [X29, #456]

    (570) 0x49d454 CBNZ	X2, 49d348

    (570) 0x49d458 B	49d360

0x49d45c HINT	#0

        (561) 0x49d460 LDR	X8, [X11]

        (561) 0x49d464 LDR	X12, [X5]

        (561) 0x49d468 ADD	X24, X20, X24

        (561) 0x49d46c CMP	X8, #0

        (561) 0x49d470 CCMP	X12, #1, #8, #1

        (561) 0x49d474 B.LT	49d36c

        (561) 0x49d478 CMP	X20, #1

        (561) 0x49d47c B.LT	49d36c

      (562) 0x49d480 LDR	X10, [SP, #120]

      (562) 0x49d484 ORR	X8, XZR, XZR

      (562) 0x49d488 ORR	X9, XZR, XZR

      (562) 0x49d48c LDR	X10, [X10]

      (562) 0x49d490 B	49d4b4

0x49d494 HINT	#0

0x49d498 HINT	#0

0x49d49c HINT	#0

        (563) 0x49d4a0 LDR	X12, [X5]

        (563) 0x49d4a4 ADD	X8, X11, X8

        (563) 0x49d4a8 ADD	X9, X9, #2

        (563) 0x49d4ac CMP	X9, X12

        (563) 0x49d4b0 B.GE	49d368

        (563) 0x49d4b4 UBFM	X13, X9, #61, #60

        (563) 0x49d4b8 ORR	X11, X13, #4157

        (563) 0x49d4bc LDR	X13, [X10, X13]

        (563) 0x49d4c0 LDR	X11, [X10, X11]

        (563) 0x49d4c4 CMP	X13, X25

        (563) 0x49d4c8 B.NE	49d4a4

        (563) 0x49d4cc CMP	X11, #1

        (563) 0x49d4d0 B.LT	49d4a4

        (563) 0x49d4d4 LDR	X13, [X21]

        (563) 0x49d4d8 LDR	X14, [X6]

        (563) 0x49d4dc ORR	X12, XZR, XZR

        (563) 0x49d4e0 AND	X15, X11, #8127

        (563) 0x49d4e4 B	49d4f4

          (564) 0x49d4e8 ADD	X12, X12, #1

          (564) 0x49d4ec CMP	X12, X20

          (564) 0x49d4f0 B.EQ	49d4a0

          (564) 0x49d4f4 LDR	X16, [X19]

          (564) 0x49d4f8 ORR	X17, XZR, X8

          (564) 0x49d4fc CMP	X11, #1

          (564) 0x49d500 B.NE	49d52c

          (564) 0x49d504 TBZ	W11, #0, 49d4e8

          (564) 0x49d508 LDR	X18, [X13, X17,LSL #3]

          (564) 0x49d50c LDR	X0, [X14, X12,LSL #3]

          (564) 0x49d510 CMP	X18, X0

          (564) 0x49d514 B.NE	49d4e8

          (564) 0x49d518 STR	X27, [X13, X17,LSL #3]

          (564) 0x49d51c LDR	X17, [X16, X22,LSL #3]

          (564) 0x49d520 ADD	X17, X17, #1

          (564) 0x49d524 STR	X17, [X16, X22,LSL #3]

          (564) 0x49d528 B	49d4e8

          (564) 0x49d52c ORR	X18, XZR, X15

          (564) 0x49d530 ORR	X17, XZR, X8

          (564) 0x49d534 B	49d54c

0x49d538 HINT	#0

0x49d53c HINT	#0

            (565) 0x49d540 ADD	X17, X17, #2

            (565) 0x49d544 SUBS	X18, X18, #2

            (565) 0x49d548 B.EQ	49d504

            (565) 0x49d54c LDR	X0, [X13, X17,LSL #3]

            (565) 0x49d550 LDR	X1, [X14, X12,LSL #3]

            (565) 0x49d554 CMP	X0, X1

            (565) 0x49d558 B.NE	49d584

            (565) 0x49d55c STR	X27, [X13, X17,LSL #3]

            (565) 0x49d560 LDR	X0, [X16, X22,LSL #3]

            (565) 0x49d564 ADD	X0, X0, #1

            (565) 0x49d568 STR	X0, [X16, X22,LSL #3]

            (565) 0x49d56c ADD	X0, X13, X17,LSL #3

            (565) 0x49d570 LDR	X2, [X14, X12,LSL #3]

            (565) 0x49d574 LDR	X1, [X0, #8]

            (565) 0x49d578 CMP	X1, X2

            (565) 0x49d57c B.NE	49d540

            (565) 0x49d580 B	49d598

            (565) 0x49d584 ADD	X0, X13, X17,LSL #3

            (565) 0x49d588 LDR	X2, [X14, X12,LSL #3]

            (565) 0x49d58c LDR	X1, [X0, #8]

            (565) 0x49d590 CMP	X1, X2

            (565) 0x49d594 B.NE	49d540

            (565) 0x49d598 STR	X27, [X0, #8]

            (565) 0x49d59c LDR	X0, [X16, X22,LSL #3]

            (565) 0x49d5a0 ADD	X0, X0, #1

            (565) 0x49d5a4 STR	X0, [X16, X22,LSL #3]

            (565) 0x49d5a8 B	49d540

        (561) 0x49d5ac LDR	X8, [X11]

        (561) 0x49d5b0 UBFM	X12, X16, #61, #60

        (561) 0x49d5b4 CMP	X20, #1

        (561) 0x49d5b8 LDP	X10, X9, [X8, #56]

        (561) 0x49d5bc LDR	X8, [X9, X12]

        (561) 0x49d5c0 LDR	X9, [X10, X12]

        (561) 0x49d5c4 B.LT	49d934

        (561) 0x49d5c8 LDP	X11, X13, [SP, #32]

        (561) 0x49d5cc ORR	X28, XZR, X16

        (561) 0x49d5d0 LDP	X16, X18, [SP, #64]

        (561) 0x49d5d4 LDR	X17, [SP, #88]

        (561) 0x49d5d8 ADD	X14, X12, #8

        (561) 0x49d5dc ORR	X10, XZR, XZR

        (561) 0x49d5e0 ORR	X26, XZR, X8

        (561) 0x49d5e4 LDR	X15, [X6]

        (561) 0x49d5e8 LDP	X0, X1, [SP, #48]

        (561) 0x49d5ec ORR	X21, XZR, X9

        (561) 0x49d5f0 LDR	X11, [X11]

        (561) 0x49d5f4 LDR	X13, [X13]

        (561) 0x49d5f8 LDR	X16, [X16]

        (561) 0x49d5fc LDR	X17, [X17]

        (561) 0x49d600 LDR	X18, [X18]

        (561) 0x49d604 LDR	X0, [X0]

        (561) 0x49d608 LDR	X1, [X1]

        (561) 0x49d60c LDR	X12, [X11, X14]

        (561) 0x49d610 LDR	X14, [X13, X14]

        (561) 0x49d614 B	49d63c

0x49d618 HINT	#0

0x49d61c HINT	#0

          (566) 0x49d620 LDR	D0, [X17, X24,LSL #3]

          (566) 0x49d624 LDP	X5, X6, [X29, #984]

          (566) 0x49d628 STR	D0, [X3]

          (566) 0x49d62c ADD	X10, X10, #1

          (566) 0x49d630 ADD	X24, X24, #1

          (566) 0x49d634 CMP	X10, X20

          (566) 0x49d638 B.EQ	49da80

          (566) 0x49d63c LDP	X3, X4, [X29, #1000]

          (566) 0x49d640 LDR	X2, [X15, X24,LSL #3]

          (566) 0x49d644 LDR	X3, [X3]

          (566) 0x49d648 LDR	X4, [X4]

          (566) 0x49d64c CMP	X2, X3

          (566) 0x49d650 CCMP	X2, X4, #0, #10

          (566) 0x49d654 B.LE	49d6c0

          (566) 0x49d658 LDR	X4, [X13, X28,LSL #3]

          (566) 0x49d65c CMP	X4, X8

          (566) 0x49d660 B.GE	49d6a0

          (566) 0x49d664 UBFM	X5, X4, #61, #60

          (566) 0x49d668 SUB	X4, X8, X4

          (566) 0x49d66c ADD	X3, X1, X5

          (566) 0x49d670 ADD	X5, X0, X5

          (566) 0x49d674 HINT	#0

          (566) 0x49d678 HINT	#0

          (566) 0x49d67c HINT	#0

            (568) 0x49d680 LDR	X6, [X5]

            (568) 0x49d684 CMP	X6, X2

            (568) 0x49d688 B.EQ	49d620

            (568) 0x49d68c ADD	X3, X3, #8

            (568) 0x49d690 SUBS	X4, X4, #1

            (568) 0x49d694 ADD	X5, X5, #8

            (568) 0x49d698 B.NE	49d680

          (566) 0x49d69c LDP	X5, X6, [X29, #984]

          (566) 0x49d6a0 CMP	X26, X14

          (566) 0x49d6a4 B.GE	49d9fc

          (566) 0x49d6a8 LDR	D0, [X17, X24,LSL #3]

          (566) 0x49d6ac STR	X2, [X0, X26,LSL #3]

          (566) 0x49d6b0 STR	D0, [X1, X26,LSL #3]

          (566) 0x49d6b4 ADD	X26, X26, #1

          (566) 0x49d6b8 B	49d62c

0x49d6bc HINT	#0

          (566) 0x49d6c0 LDR	X4, [X11, X28,LSL #3]

          (566) 0x49d6c4 CMP	X4, X9

          (566) 0x49d6c8 B.GE	49d700

          (566) 0x49d6cc UBFM	X5, X4, #61, #60

          (566) 0x49d6d0 SUB	X4, X9, X4

          (566) 0x49d6d4 ADD	X3, X18, X5

          (566) 0x49d6d8 ADD	X5, X16, X5

          (566) 0x49d6dc HINT	#0

            (567) 0x49d6e0 LDR	X6, [X5]

            (567) 0x49d6e4 CMP	X6, X2

            (567) 0x49d6e8 B.EQ	49d620

            (567) 0x49d6ec ADD	X3, X3, #8

            (567) 0x49d6f0 SUBS	X4, X4, #1

            (567) 0x49d6f4 ADD	X5, X5, #8

            (567) 0x49d6f8 B.NE	49d6e0

          (566) 0x49d6fc LDP	X5, X6, [X29, #984]

          (566) 0x49d700 CMP	X21, X12

          (566) 0x49d704 B.GE	49da38

          (566) 0x49d708 LDR	D0, [X17, X24,LSL #3]

          (566) 0x49d70c STR	X2, [X16, X21,LSL #3]

          (566) 0x49d710 STR	D0, [X18, X21,LSL #3]

          (566) 0x49d714 ADD	X21, X21, #1

          (566) 0x49d718 B	49d62c

    (570) 0x49d71c LDUR	X21, [X29, #432]

    (570) 0x49d720 LDUR	X0, [X29, #464]

    (570) 0x49d724 ORR	X2, XZR, XZR

    (570) 0x49d728 CMP	X20, #0

    (570) 0x49d72c STUR	X0, [X29, #464]

    (570) 0x49d730 B.LE	49d440

  (571) 0x49d734 LDR	X10, [SP, #88]

  (571) 0x49d738 LDR	X9, [X6]

  (571) 0x49d73c ORR	X21, XZR, XZR

  (571) 0x49d740 ORR	X8, XZR, XZR

  (571) 0x49d744 LDR	X10, [X10]

  (571) 0x49d748 ORR	X28, XZR, X26

  (571) 0x49d74c B	49d780

0x49d750 HINT	#0

0x49d754 HINT	#0

0x49d758 HINT	#0

0x49d75c HINT	#0

  (571) 0x49d760 LDR	D0, [X10, X24,LSL #3]

  (571) 0x49d764 STR	X11, [X2, X21,LSL #3]

  (571) 0x49d768 STR	D0, [X0, X21,LSL #3]

  (571) 0x49d76c ADD	X21, X21, #1

  (571) 0x49d770 ADD	X8, X8, #1

  (571) 0x49d774 ADD	X24, X24, #1

  (571) 0x49d778 CMP	X8, X20

  (571) 0x49d77c B.EQ	49d7ec

  (571) 0x49d780 LDR	X11, [X9, X24,LSL #3]

  (571) 0x49d784 CMP	X26, #1

  (571) 0x49d788 B.LT	49d7bc

(572) 0x49d78c ORR	X13, XZR, X25

(572) 0x49d790 ORR	X14, XZR, X26

(572) 0x49d794 ORR	X12, XZR, X23

(572) 0x49d798 HINT	#0

(572) 0x49d79c HINT	#0

  (573) 0x49d7a0 LDR	X15, [X13]

  (573) 0x49d7a4 CMP	X15, X11

  (573) 0x49d7a8 B.EQ	49d7e0

  (573) 0x49d7ac ADD	X12, X12, #8

  (573) 0x49d7b0 SUBS	X14, X14, #1

  (573) 0x49d7b4 ADD	X13, X13, #8

  (573) 0x49d7b8 B.NE	49d7a0

  (571) 0x49d7bc CMP	X28, X17

  (571) 0x49d7c0 B.GE	49d760

  (571) 0x49d7c4 LDR	D0, [X10, X24,LSL #3]

  (571) 0x49d7c8 STR	X11, [X25, X28,LSL #3]

  (571) 0x49d7cc STR	D0, [X23, X28,LSL #3]

  (571) 0x49d7d0 ADD	X28, X28, #1

  (571) 0x49d7d4 B	49d770

0x49d7d8 HINT	#0

0x49d7dc HINT	#0

(572) 0x49d7e0 LDR	D0, [X10, X24,LSL #3]

(572) 0x49d7e4 STR	D0, [X12]

(572) 0x49d7e8 B	49d770

  (571) 0x49d7ec LDUR	X8, [X29, #424]

  (571) 0x49d7f0 ADD	X23, X28, X21

  (571) 0x49d7f4 LDR	X8, [X8]

  (571) 0x49d7f8 STR	X23, [X8, X16,LSL #3]

  (571) 0x49d7fc CBZ	X21, 49d91c

  (571) 0x49d800 LDUR	X25, [X29, #400]

  (571) 0x49d804 UBFM	X20, X23, #61, #60

  (571) 0x49d808 STR	X2, [SP, #80]

  (571) 0x49d80c ORR	X26, XZR, X16

  (571) 0x49d810 ORR	X1, XZR, X20

  (571) 0x49d814 LDR	X8, [X25]

  (571) 0x49d818 LDR	X0, [X8, X16,LSL #3]

  (571) 0x49d81c BL	4ae4a0

  (571) 0x49d820 LDR	X8, [X25]

  (571) 0x49d824 LDR	X25, [SP, #96]

  (571) 0x49d828 ORR	X1, XZR, X20

  (571) 0x49d82c STR	X0, [X8, X26,LSL #3]

  (571) 0x49d830 LDR	X8, [X25]

  (571) 0x49d834 LDR	X0, [X8, X26,LSL #3]

  (571) 0x49d838 BL	4ae4a0

  (571) 0x49d83c LDR	X8, [X25]

  (571) 0x49d840 CMP	X21, #1

  (571) 0x49d844 STR	X0, [X8, X26,LSL #3]

  (571) 0x49d848 LDR	X8, [SP, #104]

  (571) 0x49d84c LDR	X8, [X8]

  (571) 0x49d850 STR	X23, [X8, X26,LSL #3]

  (571) 0x49d854 B.LT	49d940

  (571) 0x49d858 LDUR	X8, [X29, #400]

  (571) 0x49d85c CNTW	X0, ALL

  (571) 0x49d860 LDR	X23, [SP, #128]

  (571) 0x49d864 LDR	X2, [SP, #80]

  (571) 0x49d868 MOVZ	W10, #12

  (571) 0x49d86c PTRUE	P0.D, ALL

  (571) 0x49d870 CMP	X0, #12

  (571) 0x49d874 CSEL	X10, X0, X10, #8

  (571) 0x49d878 LDR	X8, [X8]

  (571) 0x49d87c CMP	X21, X10

  (571) 0x49d880 LDR	X9, [X8, X26,LSL #3]

  (571) 0x49d884 LDR	X8, [X25]

  (571) 0x49d888 LDR	X8, [X8, X26,LSL #3]

  (571) 0x49d88c LDP	X26, X1, [X29, #968]

  (571) 0x49d890 B.CC	49d8b8

  (571) 0x49d894 UBFM	X14, X28, #61, #60

  (571) 0x49d898 LDR	X12, [SP, #8]

  (571) 0x49d89c ADD	X10, X14, X9

  (571) 0x49d8a0 ADD	X11, X14, X8

  (571) 0x49d8a4 SUB	X10, X10, X2

  (571) 0x49d8a8 SUB	X11, X11, X1

  (571) 0x49d8ac CMP	X10, X12

  (571) 0x49d8b0 CCMP	X11, X12, #0, #2

  (571) 0x49d8b4 B.CS	49daa8

  (571) 0x49d8b8 ORR	X10, XZR, XZR

  (571) 0x49d8bc SUB	W11, W21, W10

  (571) 0x49d8c0 ANDS	X12, X11, #4160

  (571) 0x49d8c4 B.EQ	49d960

  (571) 0x49d8c8 UBFM	X14, X28, #61, #60

  (571) 0x49d8cc UBFM	X16, X10, #61, #60

  (571) 0x49d8d0 ORR	X11, XZR, XZR

  (571) 0x49d8d4 ADD	X13, X8, X14

  (571) 0x49d8d8 ADD	X14, X9, X14

  (571) 0x49d8dc ADD	X15, X1, X16

  (571) 0x49d8e0 ADD	X16, X2, X16

    (575) 0x49d8e4 LDR	D0, [X15, X11,LSL #3]

    (575) 0x49d8e8 LDR	X17, [X16, X11,LSL #3]

    (575) 0x49d8ec STR	X17, [X14, X11,LSL #3]

    (575) 0x49d8f0 STR	D0, [X13, X11,LSL #3]

    (575) 0x49d8f4 ADD	X11, X11, #1

    (575) 0x49d8f8 CMP	X12, X11

    (575) 0x49d8fc B.NE	49d8e4

  (571) 0x49d900 ADD	X28, X28, X11

  (571) 0x49d904 ADD	X12, X10, X11

  (571) 0x49d908 ORN	X10, XZR, X10

  (571) 0x49d90c ADD	X10, X21, X10

  (571) 0x49d910 CMP	X10, #3

  (571) 0x49d914 B.CC	49d340

  (571) 0x49d918 B	49d974

  (571) 0x49d91c LDR	X28, [SP, #112]

  (571) 0x49d920 LDR	X23, [SP, #128]

  (571) 0x49d924 LDUR	X26, [X29, #456]

  (571) 0x49d928 LDUR	X21, [X29, #432]

  (571) 0x49d92c CBNZ	X2, 49d348

  (571) 0x49d930 B	49d360

        (561) 0x49d934 ORR	X21, XZR, X9

        (561) 0x49d938 ORR	X26, XZR, X8

        (561) 0x49d93c B	49da8c

  (571) 0x49d940 LDR	X28, [SP, #112]

  (571) 0x49d944 LDR	X23, [SP, #128]

  (571) 0x49d948 LDUR	X26, [X29, #456]

  (571) 0x49d94c LDUR	X21, [X29, #432]

  (571) 0x49d950 LDUR	X6, [X29, #480]

  (571) 0x49d954 LDR	X2, [SP, #80]

  (571) 0x49d958 CBNZ	X2, 49d348

  (571) 0x49d95c B	49d360

  (571) 0x49d960 ORR	X12, XZR, X10

  (571) 0x49d964 ORN	X10, XZR, X10

  (571) 0x49d968 ADD	X10, X21, X10

  (571) 0x49d96c CMP	X10, #3

  (571) 0x49d970 B.CC	49d340

  (571) 0x49d974 UBFM	X11, X12, #61, #60

  (571) 0x49d978 UBFM	X13, X28, #61, #60

  (571) 0x49d97c SUB	X12, X21, X12

  (571) 0x49d980 ADD	X10, X2, X11

  (571) 0x49d984 ADD	X11, X1, X11

  (571) 0x49d988 ADD	X9, X9, X13

  (571) 0x49d98c ADD	X10, X10, #16

  (571) 0x49d990 ADD	X8, X8, X13

  (571) 0x49d994 ADD	X11, X11, #16

  (571) 0x49d998 ADD	X9, X9, #16

  (571) 0x49d99c ADD	X8, X8, #16

    (574) 0x49d9a0 LDUR	D0, [X11, #496]

    (574) 0x49d9a4 LDUR	X13, [X10, #496]

    (574) 0x49d9a8 SUBS	X12, X12, #4

    (574) 0x49d9ac STUR	X13, [X9, #496]

    (574) 0x49d9b0 LDUR	X13, [X10, #504]

    (574) 0x49d9b4 STUR	D0, [X8, #496]

    (574) 0x49d9b8 LDUR	D0, [X11, #504]

    (574) 0x49d9bc STUR	X13, [X9, #504]

    (574) 0x49d9c0 LDR	X13, [X10]

    (574) 0x49d9c4 STUR	D0, [X8, #504]

    (574) 0x49d9c8 LDR	D0, [X11]

    (574) 0x49d9cc STR	X13, [X9]

    (574) 0x49d9d0 LDR	X13, [X10, #8]

    (574) 0x49d9d4 ADD	X10, X10, #32

    (574) 0x49d9d8 STR	X13, [X9, #8]

    (574) 0x49d9dc ADD	X9, X9, #32

    (574) 0x49d9e0 STR	D0, [X8]

    (574) 0x49d9e4 LDR	D0, [X11, #8]

    (574) 0x49d9e8 ADD	X11, X11, #32

    (574) 0x49d9ec STR	D0, [X8, #8]

    (574) 0x49d9f0 ADD	X8, X8, #32

    (574) 0x49d9f4 B.NE	49d9a0

  (571) 0x49d9f8 B	49d340

        (561) 0x49d9fc ORR	X3, XZR, XZR

        (561) 0x49da00 ADRP	X0,

        (561) 0x49da04 ADD	X0, X0, #2739

        (561) 0x49da08 MOVZ	W1, #3406

        (561) 0x49da0c MOVZ	W2, #1

        (561) 0x49da10 BL	4b0fc0

        (561) 0x49da14 LDR	X8, [SP, #16]

        (561) 0x49da18 MOVZ	W9, #1

        (561) 0x49da1c ADRP	X0,

        (561) 0x49da20 ADD	X0, X0, #3075

        (561) 0x49da24 LDADD	X9, X8, [X8]

        (561) 0x49da28 LDR	X8, [SP, #24]

        (561) 0x49da2c LDR	X8, [X8]

        (561) 0x49da30 CBNZ	X8, 49da70

        (561) 0x49da34 B	49da78

        (561) 0x49da38 ORR	X3, XZR, XZR

        (561) 0x49da3c ADRP	X0,

        (561) 0x49da40 ADD	X0, X0, #2739

        (561) 0x49da44 MOVZ	W1, #3440

        (561) 0x49da48 MOVZ	W2, #1

        (561) 0x49da4c BL	4b0fc0

        (561) 0x49da50 LDR	X8, [SP, #16]

        (561) 0x49da54 MOVZ	W9, #1

        (561) 0x49da58 ADRP	X0,

        (561) 0x49da5c ADD	X0, X0, #3113

        (561) 0x49da60 LDADD	X9, X8, [X8]

        (561) 0x49da64 LDR	X8, [SP, #24]

        (561) 0x49da68 LDR	X8, [X8]

        (561) 0x49da6c CBZ	X8, 49da78

        (561) 0x49da70 ORR	X1, XZR, X25

        (561) 0x49da74 BL	4ae640

        (561) 0x49da78 LDP	X30, X7, [X29, #920]

        (561) 0x49da7c LDP	X5, X6, [X29, #984]

        (561) 0x49da80 LDP	X13, X11, [X29, #952]

        (561) 0x49da84 ORR	X16, XZR, X28

        (561) 0x49da88 LDR	X28, [SP, #112]

        (561) 0x49da8c LDR	X8, [X11]

        (561) 0x49da90 LDP	X9, X8, [X8, #56]

        (561) 0x49da94 STR	X21, [X9, X16,LSL #3]

        (561) 0x49da98 STR	X26, [X8, X16,LSL #3]

        (561) 0x49da9c LDUR	X26, [X29, #456]

        (561) 0x49daa0 LDUR	X21, [X29, #432]

        (561) 0x49daa4 B	49d36c

  (571) 0x49daa8 UDIV	X10, X21, X0

  (571) 0x49daac ADD	X13, X9, X14

  (571) 0x49dab0 ADD	X14, X8, X14

  (571) 0x49dab4 ORR	X12, XZR, XZR

  (571) 0x49dab8 ADDVL	X17, X2, #1

  (571) 0x49dabc ADDVL	X18, X1, #1

  (571) 0x49dac0 ADDVL	X15, X14, #1

  (571) 0x49dac4 ADDVL	X16, X13, #1

  (571) 0x49dac8 MADD	X10, X10, X0, XZR

  (571) 0x49dacc SUB	X11, X21, X10

  (571) 0x49dad0 ADD	X28, X28, X10

  (571) 0x49dad4 HINT	#0

  (571) 0x49dad8 HINT	#0

  (571) 0x49dadc HINT	#0

    (576) 0x49dae0 LD1D	{Z0.D}, P0/Z, [X2, X12,LSL #3]

    (576) 0x49dae4 LD1D	{Z1.D}, P0/Z, [X17, X12,LSL #3]

    (576) 0x49dae8 ST1D	{Z0.D}, P0, [X13, X12,LSL #3]

    (576) 0x49daec ST1D	{Z1.D}, P0, [X16, X12,LSL #3]

    (576) 0x49daf0 LD1D	{Z0.D}, P0/Z, [X1, X12,LSL #3]

    (576) 0x49daf4 LD1D	{Z1.D}, P0/Z, [X18, X12,LSL #3]

    (576) 0x49daf8 ST1D	{Z0.D}, P0, [X14, X12,LSL #3]

    (576) 0x49dafc ST1D	{Z1.D}, P0, [X15, X12,LSL #3]

    (576) 0x49db00 ADD	X12, X12, X0

    (576) 0x49db04 CMP	X10, X12

    (576) 0x49db08 B.NE	49dae0

  (571) 0x49db0c CBNZ	X11, 49d8bc

  (571) 0x49db10 B	49d340

0x49db14 LDP	X20, X19, [SP, #336]

0x49db18 LDP	X22, X21, [SP, #320]

0x49db1c LDP	X24, X23, [SP, #304]

0x49db20 LDP	X26, X25, [SP, #288]

0x49db24 LDP	X28, X27, [SP, #272]

0x49db28 LDP	X29, X30, [SP, #256]

0x49db2c ADD	SP, SP, #352

0x49db30 RET

0x49db34 HINT	#0

0x49db38 HINT	#0

0x49db3c HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	IJMatrix_parcsr.c:3240-3484
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3240,3256-3322,3329-3352,3359-3368,3376-3377,3383-3390,3399-3411,3422-3424,3433-3445,3454-3458,3466-3484.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 40.00 to 1.50 cycles (26.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 29% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 40.00 to 23.33 cycles (1.71x speedup).

Details

6% of VPU instructions are used in vector version (process two or more data elements in vector registers):

11% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
4% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 40.00 to 2.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 404 bytes. The binary function is storing 336 bytes.

General properties

nb instructions	178
loop length	712
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

19.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	8.50	8.50	17.75	17.75	17.75	17.75	2.00	2.00	0.00	0.00	23.33	23.33	23.33	16.00	16.00
cycles	8.50	8.50	17.75	17.75	17.75	17.75	2.00	2.00	0.00	0.00	23.33	23.33	23.33	16.00	16.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-40.00

Cycles summary

Front-end	19.63
Overall L1	23.33-40.00

Vectorization ratios

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	0%
div/sqrt	0%
other	4%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 40.00 cycles. At this rate:

10% of peak load performance is reached (10.10 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (8.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 49d090

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X28, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X6, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X24, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X4, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b05c0 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X27, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b05e0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SDIV X10, X8, X27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MSUB X11, X10, X27, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X8, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X14, X13, X0, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X12, X10, X8, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X8, X13, X8, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X0, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MADD X9, X10, X0, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CSEL X16, X12, X8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CSEL X26, X9, X14, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X26, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ADD X8, X12, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR XZR, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.GE 49d1f8 <.omp_outlined..21+0x168>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X22, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X11, X22, X11, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X17, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MADD X10, X22, X10, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ W11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X11, X17, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X10, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X10, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 49d1d4 <.omp_outlined..21+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X11, X12, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X9, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X9, X26,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X12, X11, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.CC 49d1d4 <.omp_outlined..21+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X11, X10, X17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
UBFM X15, X26, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z0.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
ORR X12, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X14, X9, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X15, X15, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR Z1.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
ADD X15, X9, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X13, X11, X17, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X11, X10, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X26, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
ADD Z0.D, Z1.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
UADDV D0, P0, Z0.D
FMOV X12, D0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1
STR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBNZ X11, 49d1e0 <.omp_outlined..21+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 49d1f8 <.omp_outlined..21+0x168>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X12, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X10, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
LDR W25, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <4ee1fc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3784	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X16, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f900 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBNZ X22, 49d248 <.omp_outlined..21+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 49d248 <.omp_outlined..21+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X8], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4ee24c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3808	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f900 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X22, 49d27c <.omp_outlined..21+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X8, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X24, [X8, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X30, X7, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X23, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X26, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 49d290 <.omp_outlined..21+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 49db14 <.omp_outlined..21+0xa84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X24, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X30, X7, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X23, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X26, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 49db14 <.omp_outlined..21+0xa84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X21, X19, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MOVN X27, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR XZR, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X5, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X8, X9, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X11, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X9, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X6, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X11, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X5, X6, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
RDVL X8, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X8, X8, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X8, X8, #59, #58	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X13, X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X21, X13, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 49d378 <.omp_outlined..21+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Source file and lines	IJMatrix_parcsr.c:3240-3484
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

6% of VPU instructions are used in vector version (process two or more data elements in vector registers):

11% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
4% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 40.00 to 2.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 404 bytes. The binary function is storing 336 bytes.

General properties

nb instructions	178
loop length	712
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

19.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	8.50	8.50	17.75	17.75	17.75	17.75	2.00	2.00	0.00	0.00	23.33	23.33	23.33	16.00	16.00
cycles	8.50	8.50	17.75	17.75	17.75	17.75	2.00	2.00	0.00	0.00	23.33	23.33	23.33	16.00	16.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-40.00

Cycles summary

Front-end	19.63
Overall L1	23.33-40.00

Vectorization ratios

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	0%
div/sqrt	0%
other	4%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 40.00 cycles. At this rate:

10% of peak load performance is reached (10.10 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (8.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 49d090

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X28, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X6, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X24, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X4, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b05c0 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X27, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b05e0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTW X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SDIV X10, X8, X27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MSUB X11, X10, X27, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X8, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X14, X13, X0, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X12, X10, X8, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X8, X13, X8, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X0, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MADD X9, X10, X0, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CSEL X16, X12, X8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CSEL X26, X9, X14, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X26, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ADD X8, X12, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR XZR, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.GE 49d1f8 <.omp_outlined..21+0x168>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X22, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X11, X22, X11, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X17, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MADD X10, X22, X10, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ W11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X11, X17, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X10, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X10, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 49d1d4 <.omp_outlined..21+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X11, X12, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X9, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X9, X26,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X12, X11, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.CC 49d1d4 <.omp_outlined..21+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X11, X10, X17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
UBFM X15, X26, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z0.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
ORR X12, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X14, X9, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X15, X15, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR Z1.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
ADD X15, X9, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X13, X11, X17, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X11, X10, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X26, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
ADD Z0.D, Z1.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
UADDV D0, P0, Z0.D
FMOV X12, D0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1
STR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBNZ X11, 49d1e0 <.omp_outlined..21+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 49d1f8 <.omp_outlined..21+0x168>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X12, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X10, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
LDR W25, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <4ee1fc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3784	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X16, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f900 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBNZ X22, 49d248 <.omp_outlined..21+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 49d248 <.omp_outlined..21+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X8], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4ee24c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3808	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f900 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X22, 49d27c <.omp_outlined..21+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X8, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X24, [X8, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X30, X7, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X23, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X26, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 49d290 <.omp_outlined..21+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 49db14 <.omp_outlined..21+0xa84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X24, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X30, X7, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X23, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X26, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 49db14 <.omp_outlined..21+0xa84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X21, X19, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MOVN X27, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR XZR, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X5, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X8, X9, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X11, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X9, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X6, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X11, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X5, X6, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
RDVL X8, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X8, X8, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X8, X8, #59, #58	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X13, X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X21, X13, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 49d378 <.omp_outlined..21+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..21#0x49d090–	3.64	1.38
○Loop 579 - IJMatrix_parcsr.c:3275-3275 - exec	0.01	0
▼Loop 572 - IJMatrix_parcsr.c:3291-3484 - exec–	0	0
○Loop 573 - IJMatrix_parcsr.c:3318-3320 - exec	0	0
▼Loop 571 - IJMatrix_parcsr.c:3291-3484 - exec–	0	0
○Loop 576 - IJMatrix_parcsr.c:3359-3362 - exec	0	0
▼Loop 570 - IJMatrix_parcsr.c:3291-3484 - exec–	0	0
▼Loop 562 - IJMatrix_parcsr.c:3291-3484 - exec–	0	0
▼Loop 561 - IJMatrix_parcsr.c:3291-3475 - exec–	0.04	0.01
▼Loop 566 - IJMatrix_parcsr.c:3383-3454 - exec–	3.6	1.17
○Loop 568 - IJMatrix_parcsr.c:3388-3390 - exec	0	0
○Loop 567 - IJMatrix_parcsr.c:3422-3424 - exec	0	0
▼Loop 563 - IJMatrix_parcsr.c:3470-3484 - exec–	0	0
▼Loop 564 - IJMatrix_parcsr.c:3475-3484 - exec–	0	0
○Loop 565 - IJMatrix_parcsr.c:3478-3484 - exec	0	0
○Loop 569 - IJMatrix_parcsr.c:3367-3367 - exec	0	0
○Loop 575 - IJMatrix_parcsr.c:3359-3362 - exec	0	0
○Loop 574 - IJMatrix_parcsr.c:3359-3362 - exec	0	0
○Loop 578 - IJMatrix_parcsr.c:3274-3275 - exec	0	0
○Loop 577 - IJMatrix_parcsr.c:3282-3283 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code