OV - exec - Function .omp_outlined..9#0x4887f0

	Function: .omp_outlined..9#0x4887f0	Module: exec	Source: par_csr_matop.c:829-995 [...]	Coverage: 0.94%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 829 - 995

--------------------------------------------------------------------------------

829: #pragma omp parallel

[...]

840:     ii = hypre_GetThreadNum();

841:     num_threads = hypre_NumActiveThreads();

842:     size = num_rows_diag_A/num_threads;

843:     rest = num_rows_diag_A - size*num_threads;

844:     if (ii < rest)

845:     {

846:        ns = ii*size+ii;

847:        ne = (ii+1)*size+ii+1;

848:     }

849:     else

850:     {

851:        ns = ii*size+rest;

852:        ne = (ii+1)*size+rest;

853:     }

854:     jj_count_diag = C_diag_i[ns];

855:     jj_count_offd = C_offd_i[ns];

856:     if (num_cols_diag_B || num_cols_offd_C)

857:     B_marker = hypre_CTAlloc(HYPRE_Int, num_cols_diag_B+num_cols_offd_C);

858:     for (i1 = 0; i1 < num_cols_diag_B+num_cols_offd_C; i1++)

859:       B_marker[i1] = -1;

[...]

865:     for (i1 = ns; i1 < ne; i1++)

[...]

874:       if ( allsquare )

875:       {

876:          B_marker[i1] = jj_count_diag;

877:          C_diag_data[jj_count_diag] = zero;

878:          C_diag_j[jj_count_diag] = i1;

879:          jj_count_diag++;

[...]

886:       if (num_cols_offd_A)

887:       {

888:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

889:          {

890:             i2 = A_offd_j[jj2];

891:             a_entry = A_offd_data[jj2];

[...]

897:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

898:             {

899:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

907:                if (B_marker[i3] < jj_row_begin_offd)

908:                {

909:                   B_marker[i3] = jj_count_offd;

910:                   C_offd_data[jj_count_offd] = a_entry*B_ext_offd_data[jj3];

911:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

912:                   jj_count_offd++;

913:                }

914:                else

915:                   C_offd_data[B_marker[i3]] += a_entry*B_ext_offd_data[jj3];

916:             }

917:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

918:             {

919:                i3 = B_ext_diag_j[jj3];

920:                if (B_marker[i3] < jj_row_begin_diag)

921:                {

922:                   B_marker[i3] = jj_count_diag;

923:                   C_diag_data[jj_count_diag] = a_entry*B_ext_diag_data[jj3];

924:                   C_diag_j[jj_count_diag] = i3;

925:                   jj_count_diag++;

926:                }

927:                else

928:                   C_diag_data[B_marker[i3]] += a_entry*B_ext_diag_data[jj3];

[...]

937:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

938:       {

939:          i2 = A_diag_j[jj2];

940:          a_entry = A_diag_data[jj2];

[...]

946:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

947:          {

948:             i3 = B_diag_j[jj3];

[...]

956:             if (B_marker[i3] < jj_row_begin_diag)

957:             {

958:                B_marker[i3] = jj_count_diag;

959:                C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3];

960:                C_diag_j[jj_count_diag] = i3;

961:                jj_count_diag++;

962:             }

963:             else

964:             {

965:                C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3];

966:             }

967:          }

968:          if (num_cols_offd_B)

969:          {

970:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

971:             {

972:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

980:                if (B_marker[i3] < jj_row_begin_offd)

981:                {

982:                   B_marker[i3] = jj_count_offd;

983:                   C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3];

984:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

985:                   jj_count_offd++;

986:                }

987:                else

988:                {

989:                   C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3];

[...]

995:     hypre_TFree(B_marker);

0x4887f0 SUB	SP, SP, #320

0x4887f4 STP	X29, X30, [SP, #224]

0x4887f8 STP	X28, X27, [SP, #240]

0x4887fc STP	X26, X25, [SP, #256]

0x488800 STP	X24, X23, [SP, #272]

0x488804 STP	X22, X21, [SP, #288]

0x488808 STP	X20, X19, [SP, #304]

0x48880c ADD	X29, SP, #224

0x488810 LDR	X8, [X29, #296]

0x488814 STUR	X7, [X29, #432]

0x488818 ORR	X19, XZR, X6

0x48881c ORR	X20, XZR, X5

0x488820 STUR	X8, [X29, #448]

0x488824 LDR	X8, [X29, #288]

0x488828 ORR	X21, XZR, X4

0x48882c ORR	X22, XZR, X3

0x488830 ORR	X26, XZR, X2

0x488834 STR	X8, [SP, #80]

0x488838 LDR	X8, [X29, #280]

0x48883c STR	X8, [SP, #72]

0x488840 LDR	X8, [X29, #272]

0x488844 STR	X8, [SP, #64]

0x488848 LDP	X8, X28, [X29, #256]

0x48884c STUR	X8, [X29, #456]

0x488850 LDR	X8, [X29, #248]

0x488854 STR	X8, [SP, #56]

0x488858 LDR	X8, [X29, #240]

0x48885c STR	X8, [SP, #8]

0x488860 LDR	X8, [X29, #216]

0x488864 LDP	X27, X24, [X29, #224]

0x488868 STR	X8, [SP, #104]

0x48886c LDR	X8, [X29, #208]

0x488870 STR	X8, [SP, #96]

0x488874 LDR	X8, [X29, #200]

0x488878 STR	X8, [SP, #48]

0x48887c LDR	X8, [X29, #192]

0x488880 STR	X8, [SP, #32]

0x488884 LDR	X8, [X29, #184]

0x488888 STUR	X8, [X29, #488]

0x48888c LDR	X8, [X29, #176]

0x488890 STR	X8, [SP, #88]

0x488894 LDR	X8, [X29, #168]

0x488898 STUR	X8, [X29, #480]

0x48889c LDR	X8, [X29, #160]

0x4888a0 STR	X8, [SP, #40]

0x4888a4 LDR	X8, [X29, #152]

0x4888a8 STR	X8, [SP, #24]

0x4888ac LDP	X8, X9, [X29, #136]

0x4888b0 STP	X9, X8, [X29, #976]

0x4888b4 LDR	X8, [X29, #128]

0x4888b8 STR	X8, [SP, #16]

0x4888bc LDP	X8, X9, [X29, #112]

0x4888c0 STUR	X8, [X29, #496]

0x4888c4 LDP	X25, X8, [X29, #96]

0x4888c8 STP	X8, X9, [X29, #928]

0x4888cc BL	4b05e0

0x4888d0 ORR	X23, XZR, X0

0x4888d4 BL	4b05c0

0x4888d8 LDR	X8, [X26]

0x4888dc ADD	X10, X23, #1

0x4888e0 ORR	X13, XZR, X19

0x4888e4 SDIV	X9, X8, X0

0x4888e8 MSUB	X8, X9, X0, X8

0x4888ec CMP	X23, X8

0x4888f0 MADD	X11, X9, X23, X8

0x4888f4 MADD	X8, X9, X10, X8

0x4888f8 ADD	X9, X9, #1

0x4888fc MADD	X12, X9, X23, XZR

0x488900 MADD	X9, X9, X10, XZR

0x488904 CSEL	X8, X8, X9, #10

0x488908 CSEL	X26, X11, X12, #10

0x48890c LDR	X9, [X19]

0x488910 STUR	X8, [X29, #440]

0x488914 LDR	X8, [X22]

0x488918 LDR	X22, [X8, X26,LSL #3]

0x48891c LDR	X8, [X21]

0x488920 LDR	X19, [X8, X26,LSL #3]

0x488924 LDR	X8, [X20]

0x488928 ORR	X10, X8, X9

0x48892c CBNZ	X10, 488938

0x488930 ORR	X0, XZR, XZR

0x488934 B	488998

0x488938 ADD	X0, X9, X8

0x48893c MOVZ	W1, #8

0x488940 ORR	X21, XZR, X13

0x488944 BL	4ae430

0x488948 LDR	X8, [X20]

0x48894c LDR	X9, [X21]

0x488950 ADD	X8, X9, X8

0x488954 CMP	X8, #1

0x488958 B.LT	488998

0x48895c ORR	X12, XZR, X21

0x488960 LDP	X30, X21, [SP, #88]

0x488964 ORR	X8, XZR, XZR

0x488968 MOVN	X9, #0

(467) 0x48896c STR	X9, [X0, X8,LSL #3]

(467) 0x488970 ADD	X8, X8, #1

(467) 0x488974 LDR	X10, [X20]

(467) 0x488978 LDR	X11, [X12]

(467) 0x48897c ADD	X10, X11, X10

(467) 0x488980 CMP	X8, X10

(467) 0x488984 B.LT	48896c

0x488988 LDUR	X8, [X29, #440]

0x48898c CMP	X26, X8

0x488990 B.LT	4889a8

0x488994 B	488d78

0x488998 LDP	X30, X21, [SP, #88]

0x48899c LDUR	X8, [X29, #440]

0x4889a0 CMP	X26, X8

0x4889a4 B.GE	488d78

0x4889a8 LDR	X8, [X25]

0x4889ac LDR	X16, [X27]

0x4889b0 LDR	X17, [X24]

0x4889b4 ORR	X2, XZR, X22

0x4889b8 STUR	X8, [X29, #408]

0x4889bc LDUR	X8, [X29, #496]

0x4889c0 LDR	X8, [X8]

0x4889c4 STR	X8, [SP, #112]

0x4889c8 LDR	X8, [SP, #16]

0x4889cc LDUR	X9, [X29, #472]

0x4889d0 LDR	X8, [X8]

0x4889d4 LDR	X10, [X9]

0x4889d8 LDUR	X9, [X29, #464]

0x4889dc ADD	X1, X8, #8

0x4889e0 LDR	X9, [X9]

0x4889e4 STP	X9, X10, [X29, #976]

0x4889e8 LDR	X9, [SP, #24]

0x4889ec LDR	X13, [X9]

0x4889f0 LDR	X9, [SP, #32]

0x4889f4 LDR	X14, [X9]

0x4889f8 LDR	X9, [SP, #104]

0x4889fc STR	X8, [SP, #104]

0x488a00 LDR	X15, [X9]

0x488a04 LDR	X9, [SP, #8]

0x488a08 LDR	X18, [X9]

0x488a0c B	488a38

0x488a10 HINT	#0

0x488a14 HINT	#0

0x488a18 HINT	#0

0x488a1c HINT	#0

(461) 0x488a20 LDP	X30, X21, [SP, #88]

  (460) 0x488a24 LDUR	X8, [X29, #440]

  (460) 0x488a28 ORR	X19, XZR, X3

  (460) 0x488a2c ORR	X22, XZR, X2

  (460) 0x488a30 CMP	X26, X8

  (460) 0x488a34 B.GE	488d78

  (460) 0x488a38 LDUR	X8, [X29, #432]

  (460) 0x488a3c LDR	X8, [X8]

  (460) 0x488a40 CBZ	X8, 488a64

  (460) 0x488a44 LDUR	X8, [X29, #416]

  (460) 0x488a48 ADD	X2, X22, #1

  (460) 0x488a4c STR	X22, [X0, X26,LSL #3]

  (460) 0x488a50 LDR	D0, [X8]

  (460) 0x488a54 LDUR	X8, [X29, #408]

  (460) 0x488a58 STR	D0, [X8, X22,LSL #3]

  (460) 0x488a5c LDR	X8, [SP, #112]

  (460) 0x488a60 STR	X26, [X8, X22,LSL #3]

  (460) 0x488a64 LDUR	X8, [X29, #424]

  (460) 0x488a68 LDR	X8, [X8]

  (460) 0x488a6c CBZ	X8, 488be0

  (460) 0x488a70 LDR	X8, [SP, #104]

  (460) 0x488a74 LDR	X4, [X8, X26,LSL #3]

  (460) 0x488a78 LDR	X8, [X1, X26,LSL #3]

  (460) 0x488a7c CMP	X4, X8

  (460) 0x488a80 B.GE	488c00

  (460) 0x488a84 LDR	X8, [SP, #40]

  (460) 0x488a88 ORR	X3, XZR, X19

  (460) 0x488a8c LDR	X5, [X8]

  (460) 0x488a90 LDR	X8, [SP, #48]

  (460) 0x488a94 LDR	X6, [X8]

  (460) 0x488a98 B	488ab0

0x488a9c HINT	#0

    (464) 0x488aa0 LDR	X8, [X1, X26,LSL #3]

    (464) 0x488aa4 ADD	X4, X4, #1

    (464) 0x488aa8 CMP	X4, X8

    (464) 0x488aac B.GE	488be4

    (464) 0x488ab0 LDUR	X8, [X29, #472]

    (464) 0x488ab4 LDR	X7, [X8, X4,LSL #3]

    (464) 0x488ab8 LDUR	X8, [X29, #464]

    (464) 0x488abc LDR	D0, [X8, X4,LSL #3]

    (464) 0x488ac0 ADD	X8, X7, #1

    (464) 0x488ac4 LDR	X9, [X13, X7,LSL #3]

    (464) 0x488ac8 LDR	X24, [X13, X8,LSL #3]

    (464) 0x488acc CMP	X9, X24

    (464) 0x488ad0 B.GE	488b50

    (464) 0x488ad4 LDUR	X11, [X29, #480]

    (464) 0x488ad8 LDR	X10, [X30]

    (464) 0x488adc LDR	X27, [X11]

    (464) 0x488ae0 LDUR	X11, [X29, #488]

    (464) 0x488ae4 LDR	X23, [X11]

    (464) 0x488ae8 B	488b08

      (466) 0x488aec LDR	D1, [X10, X9,LSL #3]

      (466) 0x488af0 LDR	D2, [X27, X12,LSL #3]

      (466) 0x488af4 FMADD	D1, D0, D1, D2

      (466) 0x488af8 STR	D1, [X27, X12,LSL #3]

      (466) 0x488afc ADD	X9, X9, #1

      (466) 0x488b00 CMP	X9, X24

      (466) 0x488b04 B.GE	488b50

      (466) 0x488b08 LDR	X11, [X20]

      (466) 0x488b0c LDR	X12, [X5, X9,LSL #3]

      (466) 0x488b10 ADD	X11, X12, X11

      (466) 0x488b14 LDR	X12, [X0, X11,LSL #3]

      (466) 0x488b18 CMP	X12, X19

      (466) 0x488b1c B.GE	488aec

      (466) 0x488b20 STR	X3, [X0, X11,LSL #3]

      (466) 0x488b24 LDR	D1, [X10, X9,LSL #3]

      (466) 0x488b28 LDR	X12, [X20]

      (466) 0x488b2c SUB	X11, X11, X12

      (466) 0x488b30 FMUL	D1, D0, D1

      (466) 0x488b34 STR	X11, [X23, X3,LSL #3]

      (466) 0x488b38 LDR	X24, [X13, X8,LSL #3]

      (466) 0x488b3c STR	D1, [X27, X3,LSL #3]

      (466) 0x488b40 ADD	X3, X3, #1

      (466) 0x488b44 ADD	X9, X9, #1

      (466) 0x488b48 CMP	X9, X24

      (466) 0x488b4c B.LT	488b08

    (464) 0x488b50 LDR	X9, [X14, X7,LSL #3]

    (464) 0x488b54 LDR	X23, [X14, X8,LSL #3]

    (464) 0x488b58 CMP	X9, X23

    (464) 0x488b5c B.GE	488aa0

    (464) 0x488b60 LDUR	X11, [X29, #496]

    (464) 0x488b64 LDR	X10, [X21]

    (464) 0x488b68 LDR	X7, [X25]

    (464) 0x488b6c LDR	X24, [X11]

    (464) 0x488b70 B	488b9c

0x488b74 HINT	#0

0x488b78 HINT	#0

0x488b7c HINT	#0

      (465) 0x488b80 LDR	D1, [X10, X9,LSL #3]

      (465) 0x488b84 LDR	D2, [X7, X12,LSL #3]

      (465) 0x488b88 FMADD	D1, D0, D1, D2

      (465) 0x488b8c STR	D1, [X7, X12,LSL #3]

      (465) 0x488b90 ADD	X9, X9, #1

      (465) 0x488b94 CMP	X9, X23

      (465) 0x488b98 B.GE	488aa0

      (465) 0x488b9c LDR	X11, [X6, X9,LSL #3]

      (465) 0x488ba0 LDR	X12, [X0, X11,LSL #3]

      (465) 0x488ba4 CMP	X12, X22

      (465) 0x488ba8 B.GE	488b80

      (465) 0x488bac LDR	D1, [X10, X9,LSL #3]

      (465) 0x488bb0 STR	X2, [X0, X11,LSL #3]

      (465) 0x488bb4 STR	X11, [X24, X2,LSL #3]

      (465) 0x488bb8 LDR	X23, [X14, X8,LSL #3]

      (465) 0x488bbc FMUL	D1, D0, D1

      (465) 0x488bc0 STR	D1, [X7, X2,LSL #3]

      (465) 0x488bc4 ADD	X2, X2, #1

      (465) 0x488bc8 ADD	X9, X9, #1

      (465) 0x488bcc CMP	X9, X23

      (465) 0x488bd0 B.LT	488b9c

    (464) 0x488bd4 B	488aa0

0x488bd8 HINT	#0

0x488bdc HINT	#0

  (460) 0x488be0 ORR	X3, XZR, X19

  (460) 0x488be4 LDR	X4, [X15, X26,LSL #3]

  (460) 0x488be8 ADD	X26, X26, #1

  (460) 0x488bec LDR	X8, [X15, X26,LSL #3]

  (460) 0x488bf0 CMP	X4, X8

  (460) 0x488bf4 B.GE	488a24

(461) 0x488bf8 B	488c18

0x488bfc HINT	#0

  (460) 0x488c00 ORR	X3, XZR, X19

  (460) 0x488c04 LDR	X4, [X15, X26,LSL #3]

  (460) 0x488c08 ADD	X26, X26, #1

  (460) 0x488c0c LDR	X8, [X15, X26,LSL #3]

  (460) 0x488c10 CMP	X4, X8

  (460) 0x488c14 B.GE	488a24

(461) 0x488c18 LDR	X8, [SP, #56]

(461) 0x488c1c LDR	X5, [X8]

(461) 0x488c20 LDR	X8, [SP, #64]

(461) 0x488c24 LDR	X6, [X8]

(461) 0x488c28 LDR	X8, [SP, #72]

(461) 0x488c2c LDR	X7, [X8]

(461) 0x488c30 LDR	X8, [SP, #80]

(461) 0x488c34 LDR	X30, [X8]

(461) 0x488c38 B	488c50

0x488c3c HINT	#0

(461) 0x488c40 LDR	X8, [X15, X26,LSL #3]

(461) 0x488c44 ADD	X4, X4, #1

(461) 0x488c48 CMP	X4, X8

(461) 0x488c4c B.GE	488a20

(461) 0x488c50 LDR	X9, [X16, X4,LSL #3]

(461) 0x488c54 LDR	D0, [X17, X4,LSL #3]

(461) 0x488c58 ADD	X8, X9, #1

(461) 0x488c5c LDR	X10, [X18, X9,LSL #3]

(461) 0x488c60 LDR	X27, [X18, X8,LSL #3]

(461) 0x488c64 CMP	X10, X27

(461) 0x488c68 B.GE	488cd8

(461) 0x488c6c LDUR	X11, [X29, #456]

(461) 0x488c70 LDR	X24, [X25]

(461) 0x488c74 LDR	X23, [X11]

(461) 0x488c78 LDUR	X11, [X29, #496]

(461) 0x488c7c LDR	X11, [X11]

(461) 0x488c80 B	488ca0

  (463) 0x488c84 LDR	D1, [X23, X10,LSL #3]

  (463) 0x488c88 LDR	D2, [X24, X21,LSL #3]

  (463) 0x488c8c FMADD	D1, D0, D1, D2

  (463) 0x488c90 STR	D1, [X24, X21,LSL #3]

  (463) 0x488c94 ADD	X10, X10, #1

  (463) 0x488c98 CMP	X10, X27

  (463) 0x488c9c B.GE	488cd8

  (463) 0x488ca0 LDR	X12, [X5, X10,LSL #3]

  (463) 0x488ca4 LDR	X21, [X0, X12,LSL #3]

  (463) 0x488ca8 CMP	X21, X22

  (463) 0x488cac B.GE	488c84

  (463) 0x488cb0 LDR	D1, [X23, X10,LSL #3]

  (463) 0x488cb4 STR	X2, [X0, X12,LSL #3]

  (463) 0x488cb8 STR	X12, [X11, X2,LSL #3]

  (463) 0x488cbc LDR	X27, [X18, X8,LSL #3]

  (463) 0x488cc0 FMUL	D1, D0, D1

  (463) 0x488cc4 STR	D1, [X24, X2,LSL #3]

  (463) 0x488cc8 ADD	X2, X2, #1

  (463) 0x488ccc ADD	X10, X10, #1

  (463) 0x488cd0 CMP	X10, X27

  (463) 0x488cd4 B.LT	488ca0

(461) 0x488cd8 LDR	X10, [X28]

(461) 0x488cdc CBZ	X10, 488c40

(461) 0x488ce0 LDR	X9, [X6, X9,LSL #3]

(461) 0x488ce4 LDR	X24, [X6, X8,LSL #3]

(461) 0x488ce8 CMP	X9, X24

(461) 0x488cec B.GE	488c40

(461) 0x488cf0 LDUR	X11, [X29, #480]

(461) 0x488cf4 LDUR	X10, [X29, #448]

(461) 0x488cf8 LDR	X27, [X11]

(461) 0x488cfc LDUR	X11, [X29, #488]

(461) 0x488d00 LDR	X10, [X10]

(461) 0x488d04 LDR	X23, [X11]

(461) 0x488d08 B	488d28

  (462) 0x488d0c LDR	D1, [X10, X9,LSL #3]

  (462) 0x488d10 LDR	D2, [X27, X12,LSL #3]

  (462) 0x488d14 FMADD	D1, D0, D1, D2

  (462) 0x488d18 STR	D1, [X27, X12,LSL #3]

  (462) 0x488d1c ADD	X9, X9, #1

  (462) 0x488d20 CMP	X9, X24

  (462) 0x488d24 B.GE	488c40

  (462) 0x488d28 LDR	X12, [X30, X9,LSL #3]

  (462) 0x488d2c LDR	X11, [X20]

  (462) 0x488d30 LDR	X12, [X7, X12,LSL #3]

  (462) 0x488d34 ADD	X11, X12, X11

  (462) 0x488d38 LDR	X12, [X0, X11,LSL #3]

  (462) 0x488d3c CMP	X12, X19

  (462) 0x488d40 B.GE	488d0c

  (462) 0x488d44 STR	X3, [X0, X11,LSL #3]

  (462) 0x488d48 LDR	D1, [X10, X9,LSL #3]

  (462) 0x488d4c LDR	X12, [X20]

  (462) 0x488d50 SUB	X11, X11, X12

  (462) 0x488d54 FMUL	D1, D0, D1

  (462) 0x488d58 STR	X11, [X23, X3,LSL #3]

  (462) 0x488d5c LDR	X24, [X6, X8,LSL #3]

  (462) 0x488d60 STR	D1, [X27, X3,LSL #3]

  (462) 0x488d64 ADD	X3, X3, #1

  (462) 0x488d68 ADD	X9, X9, #1

  (462) 0x488d6c CMP	X9, X24

  (462) 0x488d70 B.LT	488d28

(461) 0x488d74 B	488c40

0x488d78 LDP	X20, X19, [SP, #304]

0x488d7c LDP	X22, X21, [SP, #288]

0x488d80 LDP	X24, X23, [SP, #272]

0x488d84 LDP	X26, X25, [SP, #256]

0x488d88 LDP	X28, X27, [SP, #240]

0x488d8c LDP	X29, X30, [SP, #224]

0x488d90 ADD	SP, SP, #320

0x488d94 B	4ae530

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	par_csr_matop.c:829-995
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:829,840-859,865,874-879,886-891,897-899,907-928,937-940,946-948,956-972,980-989,995.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 30.33 to 10.00 cycles (3.03x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 30.33 to 1.50 cycles (20.22x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 576 bytes. The binary function is storing 328 bytes.

General properties

nb instructions	149
loop length	596
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

17.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	9.50	9.50	9.50	9.50	0.00	0.00	0.00	0.00	30.33	30.33	30.33	16.00	16.00
cycles	5.50	5.50	9.50	9.50	9.50	9.50	0.00	0.00	0.00	0.00	30.33	30.33	30.33	16.00	16.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	17.13
Overall L1	30.33

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 30.33 cycles. At this rate:

19% of peak load performance is reached (18.99 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (10.81 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4887f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #320	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X7, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X21, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X28, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X27, X24, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X9, X8, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X25, X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X8, X9, [X29, #928]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4b05e0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b05c0 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X13, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV X9, X8, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MSUB X8, X9, X0, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X23, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MADD X11, X9, X23, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X8, X9, X10, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X12, X9, X23, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X9, X9, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CSEL X8, X8, X9, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X26, X11, X12, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X8, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X19, [X8, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X10, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBNZ X10, 488938 <.omp_outlined..9+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 488998 <.omp_outlined..9+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 488998 <.omp_outlined..9+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X12, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X30, X21, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X26, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4889a8 <.omp_outlined..9+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 488d78 <.omp_outlined..9+0x588>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X30, X21, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X26, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 488d78 <.omp_outlined..9+0x588>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X2, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X9, X10, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 488a38 <.omp_outlined..9+0x248>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDP X20, X19, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #320	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4ae530 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	par_csr_matop.c:829-995
Module	exec

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 30.33 to 1.50 cycles (20.22x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 576 bytes. The binary function is storing 328 bytes.

General properties

nb instructions	149
loop length	596
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

17.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	9.50	9.50	9.50	9.50	0.00	0.00	0.00	0.00	30.33	30.33	30.33	16.00	16.00
cycles	5.50	5.50	9.50	9.50	9.50	9.50	0.00	0.00	0.00	0.00	30.33	30.33	30.33	16.00	16.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	17.13
Overall L1	30.33

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 30.33 cycles. At this rate:

19% of peak load performance is reached (18.99 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (10.81 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4887f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #320	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X7, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X21, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X28, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X27, X24, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X9, X8, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X25, X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X8, X9, [X29, #928]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4b05e0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b05c0 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X13, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV X9, X8, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MSUB X8, X9, X0, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X23, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MADD X11, X9, X23, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X8, X9, X10, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X12, X9, X23, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X9, X9, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CSEL X8, X8, X9, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X26, X11, X12, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X8, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X19, [X8, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X10, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBNZ X10, 488938 <.omp_outlined..9+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 488998 <.omp_outlined..9+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 488998 <.omp_outlined..9+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X12, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X30, X21, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X26, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4889a8 <.omp_outlined..9+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 488d78 <.omp_outlined..9+0x588>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X30, X21, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X26, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 488d78 <.omp_outlined..9+0x588>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X2, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X9, X10, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 488a38 <.omp_outlined..9+0x248>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDP X20, X19, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #320	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4ae530 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼.omp_outlined..9#0x4887f0–	0.94	0.36
▼Loop 461 - par_csr_matop.c:865-989 - exec–	0.21	0.07
○Loop 463 - par_csr_matop.c:946-965 - exec	0.72	0.23
▼Loop 460 - par_csr_matop.c:865-937 - exec–	0.01	0.01
▼Loop 464 - par_csr_matop.c:888-928 - exec–	0	0
○Loop 466 - par_csr_matop.c:897-915 - exec	0	0
○Loop 465 - par_csr_matop.c:917-928 - exec	0	0
○Loop 462 - par_csr_matop.c:970-989 - exec	0	0
○Loop 467 - par_csr_matop.c:858-859 - exec	0	0

Report Configuration

Vectorization

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

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Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code