OV - exec - Function .omp_outlined.#0x4a1da0

	Function: .omp_outlined.#0x4a1da0	Module: exec	Source: csr_matop.c:185-302 [...]	Coverage: 0.75%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c: 185 - 302

--------------------------------------------------------------------------------

185: #pragma omp parallel private(ia, ib, ic, ja, jb, num_nonzeros, row_start, counter, a_entry, b_entry)

[...]

192:     ii = hypre_GetThreadNum();

193:     num_threads = hypre_NumActiveThreads();

194:

195:    size = nrows_A/num_threads;

196:    rest = nrows_A - size*num_threads;

197:     if (ii < rest)

198:     {

199:        ns = ii*size+ii;

200:        ne = (ii+1)*size+ii+1;

201:     }

202:     else

203:     {

204:        ns = ii*size+rest;

205:        ne = (ii+1)*size+rest;

206:     }

207:

208:     B_marker = hypre_CTAlloc(HYPRE_Int, ncols_B);

209:

210:     for (ib = 0; ib < ncols_B; ib++)

211:       B_marker[ib] = -1;

212:

213:     num_nonzeros = 0;

214:     for (ic = ns; ic < ne; ic++)

215:     {

216:         C_i[ic] = num_nonzeros;

217: 	if (allsquare)

218:         {

219:            B_marker[ic] = ic;

220:            num_nonzeros++;

221:         }

222: 	for (ia = A_i[ic]; ia < A_i[ic+1]; ia++)

223: 	{

224: 	   ja = A_j[ia];

225: 	   for (ib = B_i[ja]; ib < B_i[ja+1]; ib++)

226: 	   {

227: 	      jb = B_j[ib];

228: 	      if (B_marker[jb] != ic)

229: 	      {

230: 	 	 B_marker[jb] = ic;

231: 		 num_nonzeros++;

232: 	      }

233: 	   }

234:    	}

235:    }

236:    jj_count[ii] = num_nonzeros;

237:

238: #ifdef HYPRE_USING_OPENMP

239: #pragma omp barrier

240: #endif

241:

242:     if (ii)

243:     {

244:        jj = jj_count[0];

245:        for (i1 = 1; i1 < ii; i1++)

246:           jj += jj_count[i1];

247:

248:        for (i1 = ns; i1 < ne; i1++)

249:           C_i[i1] += jj;

250:     }

251:     else

252:     {

253:        C_i[nrows_A] = 0;

254:        for (i1 = 0; i1 < num_threads; i1++)

255:           C_i[nrows_A] += jj_count[i1];

256:

257:        C = hypre_CSRMatrixCreate(nrows_A, ncols_B, C_i[nrows_A]);

258:        hypre_CSRMatrixI(C) = C_i;

259:        hypre_CSRMatrixInitialize(C);

260:        C_j = hypre_CSRMatrixJ(C);

261:        C_data = hypre_CSRMatrixData(C);

262:     }

263:

264: #ifdef HYPRE_USING_OPENMP

265: #pragma omp barrier

266: #endif

267:

268:    for (ib = 0; ib < ncols_B; ib++)

269:       B_marker[ib] = -1;

270:

271:    counter = C_i[ns];

272:    for (ic = ns; ic < ne; ic++)

273:    {

274:       row_start = C_i[ic];

275:       if (allsquare)

276:       {

277:          B_marker[ic] = counter;

278:          C_data[counter] = 0;

279:          C_j[counter] = ic;

280:          counter++;

281:       }

282:       for (ia = A_i[ic]; ia < A_i[ic+1]; ia++)

283:       {

284: 	 ja = A_j[ia];

285: 	 a_entry = A_data[ia];

286: 	 for (ib = B_i[ja]; ib < B_i[ja+1]; ib++)

287: 	 {

288: 	    jb = B_j[ib];

289: 	    b_entry = B_data[ib];

290: 	    if (B_marker[jb] < row_start)

291: 	    {

292: 		B_marker[jb] = counter;

293: 		C_j[B_marker[jb]] = jb;

294: 		C_data[B_marker[jb]] = a_entry*b_entry;

295: 		counter++;

296: 	    }

297: 	    else

298: 		C_data[B_marker[jb]] += a_entry*b_entry;

299: 	}

300:       }

301:    }

302:    hypre_TFree(B_marker);

0x4a1da0 SUB	SP, SP, #208

0x4a1da4 STP	X29, X30, [SP, #112]

0x4a1da8 STP	X28, X27, [SP, #128]

0x4a1dac STP	X26, X25, [SP, #144]

0x4a1db0 STP	X24, X23, [SP, #160]

0x4a1db4 STP	X22, X21, [SP, #176]

0x4a1db8 STP	X20, X19, [SP, #192]

0x4a1dbc ADD	X29, SP, #112

0x4a1dc0 STP	X6, X7, [X29, #984]

0x4a1dc4 STUR	X4, [X29, #504]

0x4a1dc8 ORR	X19, XZR, X5

0x4a1dcc ORR	X24, XZR, X3

0x4a1dd0 ORR	X26, XZR, X2

0x4a1dd4 STR	X0, [SP, #56]

0x4a1dd8 LDR	X8, [X29, #152]

0x4a1ddc STR	X8, [SP, #48]

0x4a1de0 LDR	X8, [X29, #144]

0x4a1de4 STR	X8, [SP, #40]

0x4a1de8 LDR	X8, [X29, #120]

0x4a1dec LDP	X23, X22, [X29, #128]

0x4a1df0 STR	X8, [SP, #32]

0x4a1df4 LDP	X25, X8, [X29, #104]

0x4a1df8 STUR	X8, [X29, #488]

0x4a1dfc LDR	X8, [X29, #96]

0x4a1e00 STUR	X8, [X29, #464]

0x4a1e04 BL	4b05e0

0x4a1e08 ORR	X20, XZR, X0

0x4a1e0c BL	4b05c0

0x4a1e10 LDR	X8, [X26]

0x4a1e14 MOVZ	W1, #8

0x4a1e18 SDIV	X11, X8, X0

0x4a1e1c MSUB	X10, X11, X0, X8

0x4a1e20 ADD	X8, X20, #1

0x4a1e24 STR	X11, [SP, #8]

0x4a1e28 STP	X10, X0, [SP, #16]

0x4a1e2c LDR	X0, [X24]

0x4a1e30 CMP	X20, X10

0x4a1e34 MADD	X9, X11, X20, X10

0x4a1e38 MADD	X10, X11, X8, X10

0x4a1e3c ADD	X11, X11, #1

0x4a1e40 STUR	X20, [X29, #496]

0x4a1e44 MADD	X12, X11, X20, XZR

0x4a1e48 MADD	X8, X11, X8, XZR

0x4a1e4c CSEL	X21, X9, X12, #10

0x4a1e50 CSEL	X28, X10, X8, #10

0x4a1e54 BL	4ae430

0x4a1e58 LDR	X8, [X24]

0x4a1e5c ORR	X20, XZR, X0

0x4a1e60 CMP	X8, #1

0x4a1e64 B.LT	4a1e94

0x4a1e68 ORR	X8, XZR, XZR

0x4a1e6c MOVN	X9, #0

0x4a1e70 HINT	#0

0x4a1e74 HINT	#0

0x4a1e78 HINT	#0

0x4a1e7c HINT	#0

(41) 0x4a1e80 STR	X9, [X20, X8,LSL #3]

(41) 0x4a1e84 ADD	X8, X8, #1

(41) 0x4a1e88 LDR	X10, [X24]

(41) 0x4a1e8c CMP	X8, X10

(41) 0x4a1e90 B.LT	4a1e80

0x4a1e94 LDUR	X4, [X29, #496]

0x4a1e98 ORR	X8, XZR, XZR

0x4a1e9c CMP	X21, X28

0x4a1ea0 B.GE	4a1f6c

0x4a1ea4 LDUR	X12, [X29, #464]

0x4a1ea8 LDUR	X9, [X29, #504]

0x4a1eac LDP	X10, X11, [X29, #984]

0x4a1eb0 ORR	X14, XZR, X21

0x4a1eb4 LDR	X12, [X12]

0x4a1eb8 LDR	X9, [X9]

0x4a1ebc LDR	X10, [X10]

0x4a1ec0 LDR	X11, [X11]

0x4a1ec4 ADD	X13, X12, #8

0x4a1ec8 B	4a1ed4

    (38) 0x4a1ecc CMP	X14, X28

    (38) 0x4a1ed0 B.GE	4a1f6c

    (38) 0x4a1ed4 STR	X8, [X9, X14,LSL #3]

    (38) 0x4a1ed8 ORR	X15, XZR, X14

    (38) 0x4a1edc LDR	X14, [X19]

    (38) 0x4a1ee0 CBZ	X14, 4a1eec

    (38) 0x4a1ee4 ADD	X8, X8, #1

    (38) 0x4a1ee8 STR	X15, [X20, X15,LSL #3]

    (38) 0x4a1eec ADD	X14, X15, #1

    (38) 0x4a1ef0 LDR	X16, [X10, X15,LSL #3]

    (38) 0x4a1ef4 LDR	X1, [X10, X14,LSL #3]

    (38) 0x4a1ef8 CMP	X16, X1

    (38) 0x4a1efc B.GE	4a1ecc

  (40) 0x4a1f00 LDR	X17, [X25]

  (40) 0x4a1f04 B	4a1f18

(39) 0x4a1f08 LDR	X1, [X10, X14,LSL #3]

  (40) 0x4a1f0c ADD	X16, X16, #1

  (40) 0x4a1f10 CMP	X16, X1

  (40) 0x4a1f14 B.GE	4a1ecc

  (40) 0x4a1f18 LDR	X18, [X11, X16,LSL #3]

  (40) 0x4a1f1c LDR	X0, [X12, X18,LSL #3]

  (40) 0x4a1f20 LDR	X2, [X13, X18,LSL #3]

  (40) 0x4a1f24 CMP	X0, X2

  (40) 0x4a1f28 B.LT	4a1f4c

  (40) 0x4a1f2c B	4a1f0c

0x4a1f30 HINT	#0

0x4a1f34 HINT	#0

0x4a1f38 HINT	#0

0x4a1f3c HINT	#0

(39) 0x4a1f40 ADD	X0, X0, #1

(39) 0x4a1f44 CMP	X0, X2

(39) 0x4a1f48 B.GE	4a1f08

(39) 0x4a1f4c LDR	X1, [X17, X0,LSL #3]

(39) 0x4a1f50 LDR	X3, [X20, X1,LSL #3]

(39) 0x4a1f54 CMP	X3, X15

(39) 0x4a1f58 B.EQ	4a1f40

(39) 0x4a1f5c STR	X15, [X20, X1,LSL #3]

(39) 0x4a1f60 ADD	X8, X8, #1

(39) 0x4a1f64 LDR	X2, [X13, X18,LSL #3]

(39) 0x4a1f68 B	4a1f40

0x4a1f6c LDUR	X27, [X29, #488]

0x4a1f70 ADRP	X0,

0x4a1f74 ADD	X0, X0, #264

0x4a1f78 LDR	X9, [X27]

0x4a1f7c STR	X8, [X9, X4,LSL #3]

0x4a1f80 LDR	X8, [SP, #56]

0x4a1f84 LDR	W1, [X8]

0x4a1f88 STR	W1, [SP, #56]

0x4a1f8c BL	40f900

0x4a1f90 LDUR	X16, [X29, #496]

0x4a1f94 CBZ	X16, 4a1fcc

0x4a1f98 LDR	X10, [X27]

0x4a1f9c CNTW	X8, ALL

0x4a1fa0 CMP	X16, #2

0x4a1fa4 LDR	X9, [X10]

0x4a1fa8 B.LT	4a2004

0x4a1fac LDR	X26, [SP, #48]

0x4a1fb0 LDR	W1, [SP, #56]

0x4a1fb4 SUB	X11, X16, #1

0x4a1fb8 ORR	X27, XZR, X25

0x4a1fbc CMP	X11, X8

0x4a1fc0 B.CS	4a2014

0x4a1fc4 MOVZ	W11, #1

0x4a1fc8 B	4a2070

0x4a1fcc LDUR	X8, [X29, #504]

0x4a1fd0 LDR	X16, [SP, #24]

0x4a1fd4 LDR	X9, [X26]

0x4a1fd8 ORR	X27, XZR, X25

0x4a1fdc CMP	X16, #1

0x4a1fe0 LDR	X8, [X8]

0x4a1fe4 STR	XZR, [X8, X9,LSL #3]

0x4a1fe8 B.LT	4a219c

0x4a1fec LDUR	X9, [X29, #488]

0x4a1ff0 CMP	X16, #1

0x4a1ff4 LDR	X9, [X9]

0x4a1ff8 B.NE	4a2144

0x4a1ffc ORR	X10, XZR, XZR

0x4a2000 B	4a2184

0x4a2004 LDR	X26, [SP, #48]

0x4a2008 LDR	W1, [SP, #56]

0x4a200c ORR	X27, XZR, X25

0x4a2010 B	4a2090

0x4a2014 UDIV	X12, X11, X8

0x4a2018 PTRUE	P0.D, VL1

0x4a201c DUP	Z0.D, #0

0x4a2020 MOVPRFX	Z1, Z0

0x4a2024 CPY	Z1.D, P0/M, X9

0x4a2028 ADD	X9, X10, #8

0x4a202c ORR	X13, XZR, XZR

0x4a2030 PTRUE	P0.D, ALL

0x4a2034 ADDVL	X15, X9, #1

0x4a2038 MADD	X14, X12, X8, XZR

0x4a203c SUB	X12, X11, X14

0x4a2040 ADD	X11, X14, #1

(36) 0x4a2044 LD1D	{Z2.D}, P0/Z, [X9, X13,LSL #3]

(36) 0x4a2048 LD1D	{Z3.D}, P0/Z, [X15, X13,LSL #3]

(36) 0x4a204c ADD	X13, X13, X8

(36) 0x4a2050 CMP	X14, X13

(36) 0x4a2054 ADD	Z1.D, Z2.D, Z1.D

(36) 0x4a2058 ADD	Z0.D, Z3.D, Z0.D

(36) 0x4a205c B.NE	4a2044

0x4a2060 ADD	Z0.D, Z0.D, Z1.D

0x4a2064 UADDV	D0, P0, Z0.D

0x4a2068 FMOV	X9, D0

0x4a206c CBZ	X12, 4a2090

0x4a2070 SUB	X12, X16, X11

0x4a2074 ADD	X10, X10, X11,LSL #3

0x4a2078 HINT	#0

0x4a207c HINT	#0

(37) 0x4a2080 LDR	X11, [X10], #8

(37) 0x4a2084 SUBS	X12, X12, #1

(37) 0x4a2088 ADD	X9, X11, X9

(37) 0x4a208c B.NE	4a2080

0x4a2090 CMP	X21, X28

0x4a2094 B.GE	4a21e8

0x4a2098 LDP	X11, X12, [SP, #8]

0x4a209c LDUR	X10, [X29, #504]

0x4a20a0 MADD	X11, X16, X11, XZR

0x4a20a4 CMP	X16, X12

0x4a20a8 LDR	X10, [X10]

0x4a20ac CSEL	X12, X16, X12, #11

0x4a20b0 ADD	X11, X11, X12

0x4a20b4 SUB	X13, X28, X11

0x4a20b8 ORR	X11, XZR, X21

0x4a20bc CMP	X13, X8

0x4a20c0 B.CC	4a2128

0x4a20c4 UDIV	X11, X13, X8

0x4a20c8 UBFM	X16, X21, #61, #60

0x4a20cc ORR	X12, XZR, XZR

0x4a20d0 PTRUE	P0.D, ALL

0x4a20d4 ADD	X15, X10, X16

0x4a20d8 ADDVL	X16, X16, #1

0x4a20dc ADD	X16, X10, X16

0x4a20e0 MADD	X14, X11, X8, XZR

0x4a20e4 DUP	Z0.D, X9

0x4a20e8 SUB	X13, X13, X14

0x4a20ec ADD	X11, X21, X14

0x4a20f0 HINT	#0

0x4a20f4 HINT	#0

0x4a20f8 HINT	#0

0x4a20fc HINT	#0

(35) 0x4a2100 LD1D	{Z1.D}, P0/Z, [X15, X12,LSL #3]

(35) 0x4a2104 LD1D	{Z2.D}, P0/Z, [X16, X12,LSL #3]

(35) 0x4a2108 ADD	Z1.D, Z1.D, Z0.D

(35) 0x4a210c ADD	Z2.D, Z2.D, Z0.D

(35) 0x4a2110 ST1D	{Z1.D}, P0, [X15, X12,LSL #3]

(35) 0x4a2114 ST1D	{Z2.D}, P0, [X16, X12,LSL #3]

(35) 0x4a2118 ADD	X12, X12, X8

(35) 0x4a211c CMP	X14, X12

(35) 0x4a2120 B.NE	4a2100

0x4a2124 CBZ	X13, 4a21e8

(34) 0x4a2128 LDR	X8, [X10, X11,LSL #3]

(34) 0x4a212c ADD	X8, X8, X9

(34) 0x4a2130 STR	X8, [X10, X11,LSL #3]

(34) 0x4a2134 ADD	X11, X11, #1

(34) 0x4a2138 CMP	X11, X28

(34) 0x4a213c B.LT	4a2128

0x4a2140 B	4a21e8

0x4a2144 ORR	X10, XZR, XZR

0x4a2148 AND	X11, X16, #8127

(33) 0x4a214c LDR	X14, [X26]

(33) 0x4a2150 ADD	X12, X9, X10,LSL #3

(33) 0x4a2154 ADD	X10, X10, #2

(33) 0x4a2158 CMP	X11, X10

(33) 0x4a215c LDR	X13, [X12]

(33) 0x4a2160 LDR	X15, [X8, X14,LSL #3]

(33) 0x4a2164 ADD	X13, X15, X13

(33) 0x4a2168 STR	X13, [X8, X14,LSL #3]

(33) 0x4a216c LDR	X13, [X26]

(33) 0x4a2170 LDR	X12, [X12, #8]

(33) 0x4a2174 LDR	X14, [X8, X13,LSL #3]

(33) 0x4a2178 ADD	X12, X14, X12

(33) 0x4a217c STR	X12, [X8, X13,LSL #3]

(33) 0x4a2180 B.NE	4a214c

0x4a2184 TBZ	W16, #0, 4a219c

0x4a2188 LDR	X9, [X9, X10,LSL #3]

0x4a218c LDR	X10, [X26]

0x4a2190 LDR	X11, [X8, X10,LSL #3]

0x4a2194 ADD	X9, X11, X9

0x4a2198 STR	X9, [X8, X10,LSL #3]

0x4a219c LDR	X0, [X26]

0x4a21a0 LDR	X1, [X24]

0x4a21a4 LDR	X2, [X8, X0,LSL #3]

0x4a21a8 BL	4a2da0

0x4a21ac LDR	X25, [SP, #32]

0x4a21b0 LDUR	X8, [X29, #504]

0x4a21b4 STR	X0, [X25]

0x4a21b8 LDR	X8, [X8]

0x4a21bc STR	X8, [X0]

0x4a21c0 LDR	X0, [X25]

0x4a21c4 BL	4a2e60

0x4a21c8 LDR	X8, [X25]

0x4a21cc LDR	X26, [SP, #48]

0x4a21d0 LDR	W1, [SP, #56]

0x4a21d4 LDR	X8, [X8, #8]

0x4a21d8 STR	X8, [X23]

0x4a21dc LDR	X8, [X25]

0x4a21e0 LDR	X8, [X8, #48]

0x4a21e4 STR	X8, [X22]

0x4a21e8 ADRP	X0,

0x4a21ec ADD	X0, X0, #288

0x4a21f0 BL	40f900

0x4a21f4 LDR	X8, [X24]

0x4a21f8 CMP	X8, #1

0x4a21fc B.LT	4a221c

0x4a2200 ORR	X8, XZR, XZR

0x4a2204 MOVN	X9, #0

(32) 0x4a2208 STR	X9, [X20, X8,LSL #3]

(32) 0x4a220c ADD	X8, X8, #1

(32) 0x4a2210 LDR	X10, [X24]

(32) 0x4a2214 CMP	X8, X10

(32) 0x4a2218 B.LT	4a2208

0x4a221c CMP	X21, X28

0x4a2220 B.GE	4a2338

0x4a2224 LDUR	X8, [X29, #504]

0x4a2228 LDUR	X15, [X29, #464]

0x4a222c LDP	X12, X13, [X29, #984]

0x4a2230 LDR	X14, [SP, #40]

0x4a2234 LDR	X10, [X22]

0x4a2238 LDR	X11, [X23]

0x4a223c LDR	X8, [X8]

0x4a2240 LDR	X15, [X15]

0x4a2244 LDR	X12, [X12]

0x4a2248 LDR	X13, [X13]

0x4a224c LDR	X14, [X14]

0x4a2250 LDR	X9, [X8, X21,LSL #3]

0x4a2254 ADD	X16, X15, #8

0x4a2258 B	4a2268

0x4a225c HINT	#0

    (27) 0x4a2260 CMP	X21, X28

    (27) 0x4a2264 B.GE	4a2338

    (27) 0x4a2268 LDR	X17, [X8, X21,LSL #3]

    (27) 0x4a226c LDR	X18, [X19]

    (27) 0x4a2270 CBZ	X18, 4a2284

    (27) 0x4a2274 STR	X9, [X20, X21,LSL #3]

    (27) 0x4a2278 STR	XZR, [X10, X9,LSL #3]

    (27) 0x4a227c STR	X21, [X11, X9,LSL #3]

    (27) 0x4a2280 ADD	X9, X9, #1

    (27) 0x4a2284 LDR	X18, [X12, X21,LSL #3]

    (27) 0x4a2288 ADD	X21, X21, #1

    (27) 0x4a228c LDR	X4, [X12, X21,LSL #3]

    (27) 0x4a2290 CMP	X18, X4

    (27) 0x4a2294 B.GE	4a2260

  (28) 0x4a2298 LDR	X0, [X27]

  (28) 0x4a229c LDR	X1, [X26]

  (28) 0x4a22a0 B	4a22b4

  (31) 0x4a22a4 LDR	X4, [X12, X21,LSL #3]

  (28) 0x4a22a8 ADD	X18, X18, #1

  (28) 0x4a22ac CMP	X18, X4

  (28) 0x4a22b0 B.GE	4a2260

  (28) 0x4a22b4 LDR	X2, [X13, X18,LSL #3]

  (28) 0x4a22b8 LDR	X3, [X15, X2,LSL #3]

  (28) 0x4a22bc LDR	X5, [X16, X2,LSL #3]

  (28) 0x4a22c0 CMP	X3, X5

  (28) 0x4a22c4 B.GE	4a22a8

(29) 0x4a22c8 LDR	D0, [X14, X18,LSL #3]

(29) 0x4a22cc LDR	X4, [X22]

(29) 0x4a22d0 LDR	X6, [X23]

(29) 0x4a22d4 B	4a22f8

0x4a22d8 HINT	#0

0x4a22dc HINT	#0

(29) 0x4a22e0 LDR	D2, [X4, X24,LSL #3]

(29) 0x4a22e4 FMADD	D1, D0, D1, D2

(29) 0x4a22e8 STR	D1, [X4, X24,LSL #3]

(29) 0x4a22ec ADD	X3, X3, #1

(29) 0x4a22f0 CMP	X3, X5

(29) 0x4a22f4 B.GE	4a22a4

  (30) 0x4a22f8 LDR	X7, [X0, X3,LSL #3]

  (30) 0x4a22fc LDR	D1, [X1, X3,LSL #3]

  (30) 0x4a2300 LDR	X24, [X20, X7,LSL #3]

  (30) 0x4a2304 CMP	X24, X17

  (30) 0x4a2308 B.GE	4a22e0

  (30) 0x4a230c STR	X9, [X20, X7,LSL #3]

  (30) 0x4a2310 STR	X7, [X6, X9,LSL #3]

  (30) 0x4a2314 FMUL	D1, D0, D1

  (30) 0x4a2318 ADD	X9, X9, #1

  (30) 0x4a231c LDR	X5, [X20, X7,LSL #3]

  (30) 0x4a2320 STR	D1, [X4, X5,LSL #3]

  (30) 0x4a2324 LDR	X5, [X16, X2,LSL #3]

  (30) 0x4a2328 ADD	X3, X3, #1

  (30) 0x4a232c CMP	X3, X5

  (30) 0x4a2330 B.LT	4a22f8

  (31) 0x4a2334 B	4a22a4

0x4a2338 ORR	X0, XZR, X20

0x4a233c LDP	X20, X19, [SP, #192]

0x4a2340 LDP	X22, X21, [SP, #176]

0x4a2344 LDP	X24, X23, [SP, #160]

0x4a2348 LDP	X26, X25, [SP, #144]

0x4a234c LDP	X28, X27, [SP, #128]

0x4a2350 LDP	X29, X30, [SP, #112]

0x4a2354 ADD	SP, SP, #208

0x4a2358 B	4ae530

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	csr_matop.c:185-302
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:185,192-302.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 60.00 to 5.00 cycles (12.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 39% of vector register length is used (average across all VPU instructions).

Details

7% of VPU instructions are used in vector version (process two or more data elements in vector registers):

40% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 60.00 to 3.50 cycles (17.14x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 648 bytes. The binary function is storing 260 bytes.

General properties

nb instructions	229
loop length	916
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

26.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	14.00	14.00	22.25	22.25	22.25	22.25	2.50	2.50	0.00	0.00	32.50	32.17	32.33	12.50	12.50
cycles	14.00	14.00	22.25	22.25	22.25	22.25	2.50	2.50	0.00	0.00	32.50	32.17	32.33	12.50	12.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

15.00-60.00

Cycles summary

Front-end	26.38
Overall L1	32.50-60.00

Vectorization ratios

all	7%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	40%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 60.00 cycles. At this rate:

11% of peak load performance is reached (10.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4a1da0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X6, X7, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X4, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X24, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X0, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X23, X22, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X25, X8, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4b05e0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b05c0 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV X11, X8, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MSUB X10, X11, X0, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X8, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X11, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X10, X0, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X20, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MADD X9, X11, X20, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X10, X11, X8, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X20, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X12, X11, X20, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X8, X11, X8, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CSEL X21, X9, X12, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X28, X10, X8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4a1e94 <.omp_outlined.+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
LDUR X4, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X21, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a1f6c <.omp_outlined.+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X12, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X10, X11, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X14, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a1ed4 <.omp_outlined.+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
LDUR X27, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <4eff70>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #264	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X9, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W1, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f900 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X16, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X16, 4a1fcc <.omp_outlined.+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CNTW X8, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X16, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.LT 4a2004 <.omp_outlined.+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X26, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X11, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X27, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 4a2014 <.omp_outlined.+0x274>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a2070 <.omp_outlined.+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X27, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.LT 4a219c <.omp_outlined.+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.NE 4a2144 <.omp_outlined.+0x3a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a2184 <.omp_outlined.+0x3e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X26, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X27, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a2090 <.omp_outlined.+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X12, X11, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
PTRUE P0.D, VL1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
DUP Z0.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
MOVPRFX Z1, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
CPY Z1.D, P0/M, X9	1	0	0	0	0	1	0	0.50	0.50	0	0	0	0	0	0	0	5	1
ADD X9, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X13, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADDVL X15, X9, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X14, X12, X8, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X12, X11, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
UADDV D0, P0, Z0.D
FMOV X9, D0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1
CBZ X12, 4a2090 <.omp_outlined.+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X12, X16, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X10, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
CMP X21, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a21e8 <.omp_outlined.+0x448>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X12, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDUR X10, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X11, X16, X11, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X16, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CSEL X12, X16, X12, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X13, X28, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X11, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X13, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 4a2128 <.omp_outlined.+0x388>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X11, X13, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
UBFM X16, X21, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X12, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X15, X10, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X16, X16, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X16, X10, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X14, X11, X8, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
DUP Z0.D, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
SUB X13, X13, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X21, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
CBZ X13, 4a21e8 <.omp_outlined.+0x448>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 4a21e8 <.omp_outlined.+0x448>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND X11, X16, #8127	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
TBZ W16, #0, 4a219c <.omp_outlined.+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X9, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X8, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X11, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X9, [X8, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4a2da0 <hypre_CSRMatrixCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4a2e60 <hypre_CSRMatrixInitialize>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADRP X0, <4ef1e8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f900 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4a221c <.omp_outlined.+0x47c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X21, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a2338 <.omp_outlined.+0x598>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X15, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X12, X13, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X14, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a2268 <.omp_outlined.+0x4c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X20, X19, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4ae530 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	csr_matop.c:185-302
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:185,192-302.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 39% of vector register length is used (average across all VPU instructions).

Details

7% of VPU instructions are used in vector version (process two or more data elements in vector registers):

40% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 60.00 to 3.50 cycles (17.14x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 648 bytes. The binary function is storing 260 bytes.

General properties

nb instructions	229
loop length	916
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

26.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	14.00	14.00	22.25	22.25	22.25	22.25	2.50	2.50	0.00	0.00	32.50	32.17	32.33	12.50	12.50
cycles	14.00	14.00	22.25	22.25	22.25	22.25	2.50	2.50	0.00	0.00	32.50	32.17	32.33	12.50	12.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

15.00-60.00

Cycles summary

Front-end	26.38
Overall L1	32.50-60.00

Vectorization ratios

all	7%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	40%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 60.00 cycles. At this rate:

11% of peak load performance is reached (10.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4a1da0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X6, X7, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X4, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X24, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X0, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X23, X22, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X25, X8, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4b05e0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b05c0 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV X11, X8, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MSUB X10, X11, X0, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X8, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X11, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X10, X0, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X20, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MADD X9, X11, X20, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X10, X11, X8, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X20, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X12, X11, X20, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X8, X11, X8, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CSEL X21, X9, X12, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X28, X10, X8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4a1e94 <.omp_outlined.+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
LDUR X4, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X21, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a1f6c <.omp_outlined.+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X12, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X10, X11, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X14, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a1ed4 <.omp_outlined.+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
LDUR X27, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <4eff70>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #264	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X9, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W1, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f900 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X16, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X16, 4a1fcc <.omp_outlined.+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CNTW X8, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X16, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.LT 4a2004 <.omp_outlined.+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X26, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X11, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X27, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 4a2014 <.omp_outlined.+0x274>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a2070 <.omp_outlined.+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X27, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.LT 4a219c <.omp_outlined.+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.NE 4a2144 <.omp_outlined.+0x3a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a2184 <.omp_outlined.+0x3e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X26, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X27, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a2090 <.omp_outlined.+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X12, X11, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
PTRUE P0.D, VL1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
DUP Z0.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
MOVPRFX Z1, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
CPY Z1.D, P0/M, X9	1	0	0	0	0	1	0	0.50	0.50	0	0	0	0	0	0	0	5	1
ADD X9, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X13, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADDVL X15, X9, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X14, X12, X8, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X12, X11, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
UADDV D0, P0, Z0.D
FMOV X9, D0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1
CBZ X12, 4a2090 <.omp_outlined.+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X12, X16, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X10, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
CMP X21, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a21e8 <.omp_outlined.+0x448>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X12, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDUR X10, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X11, X16, X11, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X16, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CSEL X12, X16, X12, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X13, X28, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X11, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X13, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 4a2128 <.omp_outlined.+0x388>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X11, X13, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
UBFM X16, X21, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X12, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X15, X10, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X16, X16, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X16, X10, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X14, X11, X8, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
DUP Z0.D, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
SUB X13, X13, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X21, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
CBZ X13, 4a21e8 <.omp_outlined.+0x448>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 4a21e8 <.omp_outlined.+0x448>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND X11, X16, #8127	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
TBZ W16, #0, 4a219c <.omp_outlined.+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X9, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X8, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X11, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X9, [X8, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4a2da0 <hypre_CSRMatrixCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4a2e60 <hypre_CSRMatrixInitialize>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADRP X0, <4ef1e8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f900 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4a221c <.omp_outlined.+0x47c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X21, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4a2338 <.omp_outlined.+0x598>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X15, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X12, X13, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X14, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a2268 <.omp_outlined.+0x4c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X20, X19, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4ae530 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼.omp_outlined.#0x4a1da0–	0.75	0.28
▼Loop 39 - csr_matop.c:214-231 - exec–	0.24	0.08
▼Loop 40 - csr_matop.c:214-225 - exec–	0.04	0.01
○Loop 38 - csr_matop.c:214-222 - exec	0	0
▼Loop 29 - csr_matop.c:272-298 - exec–	0.05	0.02
○Loop 30 - csr_matop.c:286-295 - exec	0.35	0.11
▼Loop 28 - csr_matop.c:272-286 - exec–	0.06	0.02
○Loop 27 - csr_matop.c:272-282 - exec	0	0
○Loop 31 - csr_matop.c:282-286 - exec	0	0
○Loop 33 - csr_matop.c:254-255 - exec	0	0
○Loop 34 - csr_matop.c:248-249 - exec	0	0
○Loop 35 - csr_matop.c:249-249 - exec	0	0
○Loop 36 - csr_matop.c:246-246 - exec	0	0
○Loop 41 - csr_matop.c:210-211 - exec	0	0.01
○Loop 32 - csr_matop.c:268-269 - exec	0	0
○Loop 37 - csr_matop.c:245-246 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code