OV - exec - Function .omp_outlined.#0x486840

	Function: .omp_outlined.#0x486840	Module: exec	Source: par_csr_matop.c:102-276 [...]	Coverage: 0.74%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 102 - 276

--------------------------------------------------------------------------------

102: #pragma omp parallel private(ii, i1, jj_row_begin_diag, jj_row_begin_offd, jj_count_diag, jj_count_offd, jj2, i2, jj3, i3)

[...]

108:     ii = hypre_GetThreadNum();

109:     if (ii < rest)

110:     {

111:        ns = ii*size+ii;

112:        ne = (ii+1)*size+ii+1;

113:     }

114:     else

115:     {

116:        ns = ii*size+rest;

117:        ne = (ii+1)*size+rest;

118:     }

119:     jj_count_diag = start_indexing;

120:     jj_count_offd = start_indexing;

121:

122:     if (num_cols_diag_B || num_cols_offd_C)

123:     B_marker = hypre_CTAlloc(HYPRE_Int, num_cols_diag_B+num_cols_offd_C);

124:     for (i1 = 0; i1 < num_cols_diag_B+num_cols_offd_C; i1++)

125:       B_marker[i1] = -1;

126:

127:     for (i1 = ns; i1 < ne; i1++)

[...]

135:       if ( allsquare ) {

136:          B_marker[i1] = jj_count_diag;

137:          jj_count_diag++;

[...]

144:       if (num_cols_offd_A)

145:       {

146:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

147:          {

148:             i2 = A_offd_j[jj2];

[...]

154:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

155:             {

156:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

164:                if (B_marker[i3] < jj_row_begin_offd)

165:                {

166:                   B_marker[i3] = jj_count_offd;

167:                   jj_count_offd++;

168:                }

169:             }

170:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

171:             {

172:                i3 = B_ext_diag_j[jj3];

173:

174:                if (B_marker[i3] < jj_row_begin_diag)

175:                {

176:                   B_marker[i3] = jj_count_diag;

177:                   jj_count_diag++;

[...]

187:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

188:       {

189:          i2 = A_diag_j[jj2];

[...]

195:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

196:          {

197:             i3 = B_diag_j[jj3];

[...]

205:             if (B_marker[i3] < jj_row_begin_diag)

206:             {

207:                B_marker[i3] = jj_count_diag;

208:                jj_count_diag++;

[...]

216:          if (num_cols_offd_B)

217:          {

218:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

219:             {

220:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

228:                if (B_marker[i3] < jj_row_begin_offd)

229:                {

230:                   B_marker[i3] = jj_count_offd;

231:                   jj_count_offd++;

[...]

241:       (*C_diag_i)[i1] = jj_row_begin_diag;

242:       (*C_offd_i)[i1] = jj_row_begin_offd;

243:

244:     }

245:     jj_count_diag_array[ii] = jj_count_diag;

246:     jj_count_offd_array[ii] = jj_count_offd;

247:

248:     hypre_TFree(B_marker);

249: #ifdef HYPRE_USING_OPENMP

250: #pragma omp barrier

251: #endif

252:

253:     if (ii)

254:     {

255:        jj_count_diag = jj_count_diag_array[0];

256:        jj_count_offd = jj_count_offd_array[0];

257:        for (i1 = 1; i1 < ii; i1++)

258:        {

259:           jj_count_diag += jj_count_diag_array[i1];

260:           jj_count_offd += jj_count_offd_array[i1];

261:        }

262:

263:        for (i1 = ns; i1 < ne; i1++)

264:        {

265:           (*C_diag_i)[i1] += jj_count_diag;

266:           (*C_offd_i)[i1] += jj_count_offd;

267:        }

268:     }

269:     else

270:     {

271:        (*C_diag_i)[num_rows_diag_A] = 0;

272:        (*C_offd_i)[num_rows_diag_A] = 0;

273:        for (i1 = 0; i1 < num_threads; i1++)

274:        {

275:           (*C_diag_i)[num_rows_diag_A] += jj_count_diag_array[i1];

276:           (*C_offd_i)[num_rows_diag_A] += jj_count_offd_array[i1];

0x486840 SUB	SP, SP, #240

0x486844 STP	X29, X30, [SP, #144]

0x486848 STP	X28, X27, [SP, #160]

0x48684c STP	X26, X25, [SP, #176]

0x486850 STP	X24, X23, [SP, #192]

0x486854 STP	X22, X21, [SP, #208]

0x486858 STP	X20, X19, [SP, #224]

0x48685c ADD	X29, SP, #144

0x486860 LDR	X8, [X29, #240]

0x486864 STUR	X7, [X29, #504]

0x486868 ORR	X23, XZR, X6

0x48686c ORR	X22, XZR, X5

0x486870 STR	X0, [SP, #24]

0x486874 STR	X8, [SP, #40]

0x486878 LDR	X8, [X29, #232]

0x48687c ORR	X24, XZR, X4

0x486880 ORR	X25, XZR, X3

0x486884 ORR	X26, XZR, X2

0x486888 STR	X8, [SP, #32]

0x48688c LDR	X8, [X29, #224]

0x486890 STR	X8, [SP, #64]

0x486894 LDR	X8, [X29, #216]

0x486898 STR	X8, [SP, #56]

0x48689c BL	4b05e0

0x4868a0 LDR	X10, [X26]

0x4868a4 LDR	X11, [X25]

0x4868a8 ADD	X8, X0, #1

0x4868ac LDR	X28, [X24]

0x4868b0 CMP	X0, X10

0x4868b4 MADD	X9, X11, X0, X10

0x4868b8 STP	X11, X10, [SP, #8]

0x4868bc MADD	X10, X11, X8, X10

0x4868c0 ADD	X11, X11, #1

0x4868c4 STR	X0, [SP, #48]

0x4868c8 MADD	X12, X11, X0, XZR

0x4868cc MADD	X8, X11, X8, XZR

0x4868d0 CSEL	X20, X9, X12, #10

0x4868d4 CSEL	X11, X10, X8, #10

0x4868d8 LDR	X8, [X22]

0x4868dc LDR	X9, [X23]

0x4868e0 STUR	X11, [X29, #496]

0x4868e4 ORR	X10, X8, X9

0x4868e8 CBNZ	X10, 486904

0x4868ec ORR	X0, XZR, XZR

0x4868f0 CMP	X20, X11

0x4868f4 B.LT	486954

0x4868f8 ORR	X6, XZR, X28

0x4868fc ORR	X24, XZR, X28

0x486900 B	486bfc

0x486904 ADD	X0, X9, X8

0x486908 MOVZ	W1, #8

0x48690c BL	4ae430

0x486910 LDR	X8, [X22]

0x486914 LDR	X9, [X23]

0x486918 ADD	X8, X9, X8

0x48691c CMP	X8, #1

0x486920 B.LT	486948

0x486924 ORR	X8, XZR, XZR

0x486928 MOVN	X9, #0

(63) 0x48692c STR	X9, [X0, X8,LSL #3]

(63) 0x486930 ADD	X8, X8, #1

(63) 0x486934 LDR	X10, [X22]

(63) 0x486938 LDR	X11, [X23]

(63) 0x48693c ADD	X10, X11, X10

(63) 0x486940 CMP	X8, X10

(63) 0x486944 B.LT	48692c

0x486948 LDUR	X11, [X29, #496]

0x48694c CMP	X20, X11

0x486950 B.GE	4868f8

0x486954 LDP	X8, X9, [X29, #200]

0x486958 LDP	X12, X10, [X29, #144]

0x48695c ORR	X30, XZR, X28

0x486960 ORR	X6, XZR, X28

0x486964 LDP	X15, X16, [X29, #96]

0x486968 STR	X20, [SP]

0x48696c STP	X8, X9, [X29, #984]

0x486970 LDP	X11, X9, [X29, #184]

0x486974 LDR	X8, [X29, #176]

0x486978 STUR	X12, [X29, #448]

0x48697c LDP	X13, X12, [X29, #128]

0x486980 LDR	X16, [X16]

0x486984 LDR	X2, [X10]

0x486988 STP	X8, X9, [X29, #968]

0x48698c LDP	X9, X8, [X29, #160]

0x486990 STR	X13, [SP, #72]

0x486994 LDP	X14, X13, [X29, #112]

0x486998 LDR	X1, [X12]

0x48699c ADD	X23, X16, #8

0x4869a0 STUR	X16, [X29, #488]

0x4869a4 LDR	X4, [X8]

0x4869a8 LDR	X8, [SP, #56]

0x4869ac LDR	X17, [X14]

0x4869b0 LDUR	X14, [X29, #496]

0x4869b4 LDR	X18, [X13]

0x4869b8 LDR	X3, [X9]

0x4869bc LDR	X8, [X8]

0x4869c0 LDR	X5, [X8]

0x4869c4 LDR	X8, [SP, #64]

0x4869c8 LDR	X8, [X8]

0x4869cc LDR	X7, [X8]

0x4869d0 B	486a00

0x4869d4 HINT	#0

0x4869d8 HINT	#0

0x4869dc HINT	#0

    (56) 0x4869e0 LDUR	X14, [X29, #496]

      (55) 0x4869e4 STR	X30, [X5, X20,LSL #3]

      (55) 0x4869e8 STR	X28, [X7, X20,LSL #3]

      (55) 0x4869ec ORR	X28, XZR, X24

      (55) 0x4869f0 ORR	X30, XZR, X6

      (55) 0x4869f4 ORR	X20, XZR, X26

      (55) 0x4869f8 CMP	X26, X14

      (55) 0x4869fc B.EQ	486bf8

      (55) 0x486a00 LDUR	X8, [X29, #504]

      (55) 0x486a04 LDR	X8, [X8]

      (55) 0x486a08 CBZ	X8, 486a14

      (55) 0x486a0c ADD	X6, X30, #1

      (55) 0x486a10 STR	X30, [X0, X20,LSL #3]

      (55) 0x486a14 LDR	X8, [X15]

      (55) 0x486a18 CBZ	X8, 486ae0

      (55) 0x486a1c LDUR	X8, [X29, #488]

      (55) 0x486a20 LDR	X13, [X8, X20,LSL #3]

      (55) 0x486a24 LDR	X8, [X23, X20,LSL #3]

      (55) 0x486a28 CMP	X13, X8

      (55) 0x486a2c B.GE	486ae0

      (55) 0x486a30 LDR	X8, [SP, #72]

      (55) 0x486a34 LDUR	X9, [X29, #448]

      (55) 0x486a38 ORR	X24, XZR, X28

      (55) 0x486a3c LDR	X8, [X8]

      (55) 0x486a40 LDR	X14, [X9]

      (55) 0x486a44 B	486a58

        (59) 0x486a48 LDR	X9, [X23, X20,LSL #3]

        (59) 0x486a4c ADD	X13, X13, #1

        (59) 0x486a50 CMP	X13, X9

        (59) 0x486a54 B.GE	486b00

        (59) 0x486a58 LDR	X10, [X17, X13,LSL #3]

        (59) 0x486a5c ADD	X9, X10, #1

        (59) 0x486a60 LDR	X19, [X18, X10,LSL #3]

        (59) 0x486a64 LDR	X12, [X18, X9,LSL #3]

        (59) 0x486a68 B	486a70

          (61) 0x486a6c ADD	X19, X19, #1

          (61) 0x486a70 CMP	X19, X12

          (61) 0x486a74 B.GE	486aa0

          (61) 0x486a78 LDR	X16, [X22]

          (61) 0x486a7c LDR	X25, [X8, X19,LSL #3]

          (61) 0x486a80 ADD	X25, X16, X25

          (61) 0x486a84 LDR	X16, [X0, X25,LSL #3]

          (61) 0x486a88 CMP	X16, X28

          (61) 0x486a8c B.GE	486a6c

          (61) 0x486a90 STR	X24, [X0, X25,LSL #3]

          (61) 0x486a94 ADD	X24, X24, #1

          (61) 0x486a98 LDR	X12, [X18, X9,LSL #3]

          (61) 0x486a9c B	486a6c

        (59) 0x486aa0 LDR	X10, [X1, X10,LSL #3]

        (59) 0x486aa4 LDR	X12, [X1, X9,LSL #3]

        (59) 0x486aa8 B	486ab0

          (60) 0x486aac ADD	X10, X10, #1

          (60) 0x486ab0 CMP	X10, X12

          (60) 0x486ab4 B.GE	486a48

          (60) 0x486ab8 LDR	X19, [X14, X10,LSL #3]

          (60) 0x486abc LDR	X16, [X0, X19,LSL #3]

          (60) 0x486ac0 CMP	X16, X30

          (60) 0x486ac4 B.GE	486aac

          (60) 0x486ac8 STR	X6, [X0, X19,LSL #3]

          (60) 0x486acc ADD	X6, X6, #1

          (60) 0x486ad0 LDR	X12, [X1, X9,LSL #3]

          (60) 0x486ad4 B	486aac

0x486ad8 HINT	#0

0x486adc HINT	#0

      (55) 0x486ae0 ORR	X24, XZR, X28

      (55) 0x486ae4 ADD	X26, X20, #1

      (55) 0x486ae8 LDR	X27, [X2, X20,LSL #3]

      (55) 0x486aec LDR	X8, [X2, X26,LSL #3]

      (55) 0x486af0 CMP	X27, X8

      (55) 0x486af4 B.GE	4869e4

    (56) 0x486af8 B	486b18

0x486afc HINT	#0

      (55) 0x486b00 LDUR	X14, [X29, #496]

      (55) 0x486b04 ADD	X26, X20, #1

      (55) 0x486b08 LDR	X27, [X2, X20,LSL #3]

      (55) 0x486b0c LDR	X8, [X2, X26,LSL #3]

      (55) 0x486b10 CMP	X27, X8

      (55) 0x486b14 B.GE	4869e4

    (56) 0x486b18 LDUR	X8, [X29, #456]

    (56) 0x486b1c LDR	X13, [X8]

    (56) 0x486b20 LDUR	X8, [X29, #464]

    (56) 0x486b24 LDR	X14, [X8]

    (56) 0x486b28 LDUR	X8, [X29, #472]

    (56) 0x486b2c LDR	X19, [X8]

    (56) 0x486b30 LDUR	X8, [X29, #480]

    (56) 0x486b34 LDR	X8, [X8]

    (56) 0x486b38 B	486b50

0x486b3c HINT	#0

    (56) 0x486b40 LDR	X9, [X2, X26,LSL #3]

    (56) 0x486b44 ADD	X27, X27, #1

    (56) 0x486b48 CMP	X27, X9

    (56) 0x486b4c B.GE	4869e0

    (56) 0x486b50 LDR	X10, [X3, X27,LSL #3]

    (56) 0x486b54 ADD	X9, X10, #1

    (56) 0x486b58 LDR	X12, [X4, X10,LSL #3]

    (56) 0x486b5c LDR	X25, [X4, X9,LSL #3]

    (56) 0x486b60 B	486b68

      (58) 0x486b64 ADD	X12, X12, #1

      (58) 0x486b68 CMP	X12, X25

      (58) 0x486b6c B.GE	486ba0

      (58) 0x486b70 LDR	X16, [X13, X12,LSL #3]

      (58) 0x486b74 LDR	X21, [X0, X16,LSL #3]

      (58) 0x486b78 CMP	X21, X30

      (58) 0x486b7c B.GE	486b64

      (58) 0x486b80 STR	X6, [X0, X16,LSL #3]

      (58) 0x486b84 ADD	X6, X6, #1

      (58) 0x486b88 LDR	X25, [X4, X9,LSL #3]

      (58) 0x486b8c B	486b64

0x486b90 HINT	#0

0x486b94 HINT	#0

0x486b98 HINT	#0

0x486b9c HINT	#0

    (56) 0x486ba0 LDR	X12, [X11]

    (56) 0x486ba4 CBZ	X12, 486b40

  (57) 0x486ba8 LDR	X10, [X14, X10,LSL #3]

  (57) 0x486bac LDR	X12, [X14, X9,LSL #3]

  (57) 0x486bb0 B	486bc4

0x486bb4 HINT	#0

0x486bb8 HINT	#0

0x486bbc HINT	#0

(62) 0x486bc0 ADD	X10, X10, #1

  (57) 0x486bc4 CMP	X10, X12

  (57) 0x486bc8 B.GE	486b40

(62) 0x486bcc LDR	X21, [X8, X10,LSL #3]

(62) 0x486bd0 LDR	X16, [X22]

(62) 0x486bd4 LDR	X21, [X19, X21,LSL #3]

(62) 0x486bd8 ADD	X16, X16, X21

(62) 0x486bdc LDR	X21, [X0, X16,LSL #3]

(62) 0x486be0 CMP	X21, X28

(62) 0x486be4 B.GE	486bc0

(62) 0x486be8 STR	X24, [X0, X16,LSL #3]

(62) 0x486bec ADD	X24, X24, #1

(62) 0x486bf0 LDR	X12, [X14, X9,LSL #3]

(62) 0x486bf4 B	486bc0

0x486bf8 LDR	X20, [SP]

0x486bfc LDP	X22, X21, [SP, #32]

0x486c00 LDR	X19, [SP, #48]

0x486c04 LDR	X8, [X22]

0x486c08 STR	X6, [X8, X19,LSL #3]

0x486c0c LDR	X8, [X21]

0x486c10 STR	X24, [X8, X19,LSL #3]

0x486c14 BL	4ae530

0x486c18 LDR	X8, [SP, #24]

0x486c1c ADRP	X0,

0x486c20 ADD	X0, X0, #2728

0x486c24 LDR	W1, [X8]

0x486c28 BL	40f900

0x486c2c CBZ	X19, 486c60

0x486c30 LDR	X11, [X22]

0x486c34 LDR	X12, [X21]

0x486c38 CNTW	X10, ALL

0x486c3c CMP	X19, #2

0x486c40 LDR	X8, [X11]

0x486c44 LDR	X9, [X12]

0x486c48 B.LT	486da0

0x486c4c SUB	X13, X19, #1

0x486c50 CMP	X13, X10

0x486c54 B.CS	486ce0

0x486c58 MOVZ	W13, #1

0x486c5c B	486d78

0x486c60 LDP	X9, X11, [SP, #56]

0x486c64 LDR	X8, [X29, #248]

0x486c68 LDR	X9, [X9]

0x486c6c LDR	X10, [X8]

0x486c70 LDR	X11, [X11]

0x486c74 LDR	X9, [X9]

0x486c78 LDR	X11, [X11]

0x486c7c STR	XZR, [X9, X10,LSL #3]

0x486c80 LDR	X10, [X29, #256]

0x486c84 LDR	X12, [X8]

0x486c88 STR	XZR, [X11, X12,LSL #3]

0x486c8c LDR	X12, [X10]

0x486c90 CMP	X12, #1

0x486c94 B.LT	486f18

0x486c98 LDR	X13, [X22]

0x486c9c LDR	X14, [X21]

0x486ca0 ORR	X12, XZR, XZR

(50) 0x486ca4 LDR	X16, [X8]

(50) 0x486ca8 LDR	X15, [X13, X12,LSL #3]

(50) 0x486cac LDR	X17, [X9, X16,LSL #3]

(50) 0x486cb0 ADD	X15, X17, X15

(50) 0x486cb4 STR	X15, [X9, X16,LSL #3]

(50) 0x486cb8 LDR	X16, [X8]

(50) 0x486cbc LDR	X15, [X14, X12,LSL #3]

(50) 0x486cc0 ADD	X12, X12, #1

(50) 0x486cc4 LDR	X17, [X11, X16,LSL #3]

(50) 0x486cc8 ADD	X15, X17, X15

(50) 0x486ccc STR	X15, [X11, X16,LSL #3]

(50) 0x486cd0 LDR	X15, [X10]

(50) 0x486cd4 CMP	X12, X15

(50) 0x486cd8 B.LT	486ca4

0x486cdc B	486f18

0x486ce0 UDIV	X14, X13, X10

0x486ce4 DUP	Z0.D, #0

0x486ce8 PTRUE	P0.D, VL1

0x486cec RDVL	X15, #1

0x486cf0 MOVPRFX	Z1, Z0

0x486cf4 CPY	Z1.D, P0/M, X9

0x486cf8 MOVPRFX	Z2, Z0

0x486cfc CPY	Z2.D, P0/M, X8

0x486d00 RDVL	X16, #1

0x486d04 PTRUE	P0.D, ALL

0x486d08 PTRUE	P1.B, ALL

0x486d0c ADD	X8, X11, #8

0x486d10 ADD	X17, X12, #8

0x486d14 UBFM	X15, X15, #4, #63

0x486d18 ORR	Z3.D, Z0.D, Z0.D

0x486d1c UBFM	X15, X15, #59, #58

0x486d20 MADD	X9, X14, X10, XZR

0x486d24 SUB	X14, X13, X9

0x486d28 ADD	X13, X9, #1

(53) 0x486d2c LD1D	{Z4.D}, P0/Z, [X8, MUL VL]

(53) 0x486d30 LD1B	{Z5.B}, P1/Z, [X8, X16]

(53) 0x486d34 ADD	X8, X8, X15

(53) 0x486d38 SUBS	X9, X9, X10

(53) 0x486d3c ADD	Z2.D, Z4.D, Z2.D

(53) 0x486d40 LD1D	{Z4.D}, P0/Z, [X17, MUL VL]

(53) 0x486d44 ADD	Z3.D, Z5.D, Z3.D

(53) 0x486d48 LD1B	{Z5.B}, P1/Z, [X17, X16]

(53) 0x486d4c ADD	X17, X17, X15

(53) 0x486d50 ADD	Z1.D, Z4.D, Z1.D

(53) 0x486d54 ADD	Z0.D, Z5.D, Z0.D

(53) 0x486d58 B.NE	486d2c

0x486d5c ADD	Z2.D, Z3.D, Z2.D

0x486d60 ADD	Z0.D, Z0.D, Z1.D

0x486d64 UADDV	D2, P0, Z2.D

0x486d68 FMOV	X8, D2

0x486d6c UADDV	D0, P0, Z0.D

0x486d70 FMOV	X9, D0

0x486d74 CBZ	X14, 486da0

0x486d78 SUB	X14, X19, X13

0x486d7c UBFM	X13, X13, #61, #60

0x486d80 ADD	X12, X12, X13

0x486d84 ADD	X11, X11, X13

(54) 0x486d88 LDR	X13, [X11], #8

(54) 0x486d8c SUBS	X14, X14, #1

(54) 0x486d90 ADD	X8, X13, X8

(54) 0x486d94 LDR	X13, [X12], #8

(54) 0x486d98 ADD	X9, X13, X9

(54) 0x486d9c B.NE	486d88

0x486da0 LDUR	X14, [X29, #496]

0x486da4 CMP	X20, X14

0x486da8 B.GE	486f18

0x486dac LDP	X11, X12, [SP, #56]

0x486db0 LDP	X15, X13, [SP, #8]

0x486db4 LDR	X11, [X11]

0x486db8 LDR	X12, [X12]

0x486dbc CMP	X19, X13

0x486dc0 CSEL	X13, X19, X13, #11

0x486dc4 CMP	X10, #8

0x486dc8 MADD	X13, X19, X15, X13

0x486dcc LDR	X11, [X11]

0x486dd0 LDR	X12, [X12]

0x486dd4 SUB	X16, X14, X13

0x486dd8 MOVZ	W13, #8

0x486ddc CSEL	X13, X10, X13, #8

0x486de0 CMP	X16, X13

0x486de4 B.CC	486e8c

0x486de8 UBFM	X18, X20, #61, #60

0x486dec UBFM	X15, X14, #61, #60

0x486df0 ADD	X13, X11, X18

0x486df4 ADD	X17, X11, X15

0x486df8 ADD	X15, X12, X15

0x486dfc ADD	X14, X12, X18

0x486e00 CMP	X13, X15

0x486e04 CCMP	X14, X17, #2, #3

0x486e08 B.CC	486e88

0x486e0c UDIV	X17, X16, X10

0x486e10 ADDVL	X0, X18, #1

0x486e14 ORR	X15, XZR, XZR

0x486e18 PTRUE	P0.D, ALL

0x486e1c ADD	X18, X12, X0

0x486e20 ADD	X0, X11, X0

0x486e24 MADD	X17, X17, X10, XZR

0x486e28 DUP	Z0.D, X8

0x486e2c SUB	X16, X16, X17

0x486e30 ADD	X20, X20, X17

0x486e34 DUP	Z1.D, X9

0x486e38 HINT	#0

0x486e3c HINT	#0

(52) 0x486e40 LD1D	{Z2.D}, P0/Z, [X13, X15,LSL #3]

(52) 0x486e44 LD1D	{Z3.D}, P0/Z, [X0, X15,LSL #3]

(52) 0x486e48 ADD	Z2.D, Z2.D, Z0.D

(52) 0x486e4c ADD	Z3.D, Z3.D, Z0.D

(52) 0x486e50 ST1D	{Z2.D}, P0, [X13, X15,LSL #3]

(52) 0x486e54 ST1D	{Z3.D}, P0, [X0, X15,LSL #3]

(52) 0x486e58 LD1D	{Z2.D}, P0/Z, [X14, X15,LSL #3]

(52) 0x486e5c LD1D	{Z3.D}, P0/Z, [X18, X15,LSL #3]

(52) 0x486e60 ADD	Z2.D, Z2.D, Z1.D

(52) 0x486e64 ADD	Z3.D, Z3.D, Z1.D

(52) 0x486e68 ST1D	{Z2.D}, P0, [X14, X15,LSL #3]

(52) 0x486e6c ST1D	{Z3.D}, P0, [X18, X15,LSL #3]

(52) 0x486e70 ADD	X15, X15, X10

(52) 0x486e74 CMP	X17, X15

(52) 0x486e78 B.NE	486e40

0x486e7c LDUR	X14, [X29, #496]

0x486e80 CBNZ	X16, 486e8c

0x486e84 B	486f18

0x486e88 LDUR	X14, [X29, #496]

0x486e8c SUB	W13, W14, W20

0x486e90 ADD	X10, X20, #1

0x486e94 TBZ	W13, #0, 486eb4

0x486e98 LDR	X13, [X11, X20,LSL #3]

0x486e9c ADD	X13, X13, X8

0x486ea0 STR	X13, [X11, X20,LSL #3]

0x486ea4 LDR	X13, [X12, X20,LSL #3]

0x486ea8 ADD	X13, X13, X9

0x486eac STR	X13, [X12, X20,LSL #3]

0x486eb0 ORR	X20, XZR, X10

0x486eb4 CMP	X14, X10

0x486eb8 B.EQ	486f18

0x486ebc UBFM	X10, X20, #61, #60

0x486ec0 ADD	X13, X10, #8

0x486ec4 ADD	X10, X12, X13

0x486ec8 ADD	X11, X11, X13

0x486ecc SUB	X12, X14, X20

0x486ed0 HINT	#0

0x486ed4 HINT	#0

0x486ed8 HINT	#0

0x486edc HINT	#0

(51) 0x486ee0 LDUR	X13, [X11, #504]

(51) 0x486ee4 SUBS	X12, X12, #2

(51) 0x486ee8 ADD	X13, X13, X8

(51) 0x486eec STUR	X13, [X11, #504]

(51) 0x486ef0 LDUR	X13, [X10, #504]

(51) 0x486ef4 ADD	X13, X13, X9

(51) 0x486ef8 STUR	X13, [X10, #504]

(51) 0x486efc LDR	X13, [X11]

(51) 0x486f00 ADD	X13, X13, X8

(51) 0x486f04 STR	X13, [X11], #16

(51) 0x486f08 LDR	X13, [X10]

(51) 0x486f0c ADD	X13, X13, X9

(51) 0x486f10 STR	X13, [X10], #16

(51) 0x486f14 B.NE	486ee0

0x486f18 LDP	X20, X19, [SP, #224]

0x486f1c LDP	X22, X21, [SP, #208]

0x486f20 LDP	X24, X23, [SP, #192]

0x486f24 LDP	X26, X25, [SP, #176]

0x486f28 LDP	X28, X27, [SP, #160]

0x486f2c LDP	X29, X30, [SP, #144]

0x486f30 ADD	SP, SP, #240

0x486f34 RET

0x486f38 HINT	#0

0x486f3c HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	par_csr_matop.c:102-276
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:102,108-127,135-137,144-148,154-156,164-177,187-189,195-197,205-208,216-220,228-231,241-276.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 40.00 to 8.00 cycles (5.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 41% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 40.00 to 33.83 cycles (1.18x speedup).

Details

10% of VPU instructions are used in vector version (process two or more data elements in vector registers):

30% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
3% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 40.00 to 2.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 724 bytes. The binary function is storing 288 bytes.

General properties

nb instructions	257
loop length	1028
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

29.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	12.50	12.50	25.75	25.75	25.75	25.75	5.00	5.00	0.00	0.00	33.83	33.50	33.67	13.50	13.50
cycles	12.50	12.50	25.75	25.75	25.75	25.75	5.00	5.00	0.00	0.00	33.83	33.50	33.67	13.50	13.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-40.00

Cycles summary

Front-end	29.13
Overall L1	33.83-40.00

Vectorization ratios

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	30%
fma	0%
div/sqrt	0%
other	3%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 40.00 cycles. At this rate:

18% of peak load performance is reached (18.10 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (7.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 486840

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X7, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X0, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X24, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4b05e0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X28, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X0, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MADD X9, X11, X0, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STP X11, X10, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X10, X11, X8, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X0, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X12, X11, X0, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X8, X11, X8, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CSEL X20, X9, X12, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X11, X10, X8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X11, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X10, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBNZ X10, 486904 <.omp_outlined.+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X20, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 486954 <.omp_outlined.+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X6, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X24, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 486bfc <.omp_outlined.+0x3bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 486948 <.omp_outlined.+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X11, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X20, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4868f8 <.omp_outlined.+0xb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X12, X10, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X30, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X6, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X15, X16, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X20, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X8, X9, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X11, X9, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X12, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X13, X12, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X8, X9, [X29, #968]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X9, X8, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X13, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X14, X13, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X1, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X23, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X16, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X14, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 486a00 <.omp_outlined.+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDR X20, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X22, X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X19, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X6, [X8, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X24, [X8, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4ae530 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <4eec1c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2728	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 40f900 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X19, 486c60 <.omp_outlined.+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CNTW X10, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X19, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X8, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.LT 486da0 <.omp_outlined.+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X13, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X13, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 486ce0 <.omp_outlined.+0x4a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 486d78 <.omp_outlined.+0x538>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X9, X11, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X8, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X9, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X11, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 486f18 <.omp_outlined.+0x6d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X12, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 486f18 <.omp_outlined.+0x6d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X14, X13, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
DUP Z0.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
PTRUE P0.D, VL1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
RDVL X15, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVPRFX Z1, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
CPY Z1.D, P0/M, X9	1	0	0	0	0	1	0	0.50	0.50	0	0	0	0	0	0	0	5	1
MOVPRFX Z2, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
CPY Z2.D, P0/M, X8	1	0	0	0	0	1	0	0.50	0.50	0	0	0	0	0	0	0	5	1
RDVL X16, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P1.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X8, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X15, X15, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR Z3.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
UBFM X15, X15, #59, #58	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X9, X14, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X14, X13, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD Z2.D, Z3.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
UADDV D2, P0, Z2.D
FMOV X8, D2	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1
UADDV D0, P0, Z0.D
FMOV X9, D0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1
CBZ X14, 486da0 <.omp_outlined.+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X14, X19, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X13, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X11, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X14, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X20, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 486f18 <.omp_outlined.+0x6d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X12, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X15, X13, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X19, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X13, X19, X13, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MADD X13, X19, X15, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X16, X14, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X13, X10, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X16, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 486e8c <.omp_outlined.+0x64c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X18, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X15, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X11, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X11, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X12, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X12, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X13, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X14, X17, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.CC 486e88 <.omp_outlined.+0x648>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X17, X16, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
ADDVL X0, X18, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X15, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X18, X12, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X11, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X17, X17, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
DUP Z0.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
SUB X16, X16, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X20, X20, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z1.D, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
HINT #0
HINT #0
LDUR X14, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X16, 486e8c <.omp_outlined.+0x64c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 486f18 <.omp_outlined.+0x6d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X14, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W13, W14, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
TBZ W13, #0, 486eb4 <.omp_outlined.+0x674>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X11, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X13, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X13, [X11, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X12, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X13, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X13, [X12, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X14, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 486f18 <.omp_outlined.+0x6d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X10, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X11, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X12, X14, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
LDP X20, X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Source file and lines	par_csr_matop.c:102-276
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 40.00 to 8.00 cycles (5.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

10% of VPU instructions are used in vector version (process two or more data elements in vector registers):

30% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
3% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 40.00 to 2.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 724 bytes. The binary function is storing 288 bytes.

General properties

nb instructions	257
loop length	1028
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

29.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	12.50	12.50	25.75	25.75	25.75	25.75	5.00	5.00	0.00	0.00	33.83	33.50	33.67	13.50	13.50
cycles	12.50	12.50	25.75	25.75	25.75	25.75	5.00	5.00	0.00	0.00	33.83	33.50	33.67	13.50	13.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-40.00

Cycles summary

Front-end	29.13
Overall L1	33.83-40.00

Vectorization ratios

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	30%
fma	0%
div/sqrt	0%
other	3%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 40.00 cycles. At this rate:

18% of peak load performance is reached (18.10 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (7.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 486840

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X7, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X0, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X24, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4b05e0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X28, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X0, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MADD X9, X11, X0, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STP X11, X10, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X10, X11, X8, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X0, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X12, X11, X0, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X8, X11, X8, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CSEL X20, X9, X12, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X11, X10, X8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X11, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X10, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBNZ X10, 486904 <.omp_outlined.+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X20, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 486954 <.omp_outlined.+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X6, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X24, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 486bfc <.omp_outlined.+0x3bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 486948 <.omp_outlined.+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X11, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X20, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4868f8 <.omp_outlined.+0xb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X12, X10, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X30, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X6, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X15, X16, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X20, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X8, X9, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X11, X9, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X12, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X13, X12, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X8, X9, [X29, #968]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X9, X8, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X13, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X14, X13, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X1, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X23, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X16, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X14, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 486a00 <.omp_outlined.+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDR X20, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X22, X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X19, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X6, [X8, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X24, [X8, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4ae530 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <4eec1c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2728	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 40f900 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X19, 486c60 <.omp_outlined.+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CNTW X10, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X19, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X8, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.LT 486da0 <.omp_outlined.+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X13, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X13, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 486ce0 <.omp_outlined.+0x4a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 486d78 <.omp_outlined.+0x538>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X9, X11, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X8, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X9, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X11, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 486f18 <.omp_outlined.+0x6d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X12, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 486f18 <.omp_outlined.+0x6d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X14, X13, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
DUP Z0.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
PTRUE P0.D, VL1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
RDVL X15, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVPRFX Z1, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
CPY Z1.D, P0/M, X9	1	0	0	0	0	1	0	0.50	0.50	0	0	0	0	0	0	0	5	1
MOVPRFX Z2, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
CPY Z2.D, P0/M, X8	1	0	0	0	0	1	0	0.50	0.50	0	0	0	0	0	0	0	5	1
RDVL X16, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P1.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X8, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X15, X15, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR Z3.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
UBFM X15, X15, #59, #58	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X9, X14, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X14, X13, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD Z2.D, Z3.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
UADDV D2, P0, Z2.D
FMOV X8, D2	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1
UADDV D0, P0, Z0.D
FMOV X9, D0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1
CBZ X14, 486da0 <.omp_outlined.+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X14, X19, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X13, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X11, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X14, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X20, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 486f18 <.omp_outlined.+0x6d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X12, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X15, X13, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X19, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X13, X19, X13, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MADD X13, X19, X15, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X16, X14, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X13, X10, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X16, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 486e8c <.omp_outlined.+0x64c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X18, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X15, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X11, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X11, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X12, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X12, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X13, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X14, X17, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.CC 486e88 <.omp_outlined.+0x648>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X17, X16, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
ADDVL X0, X18, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X15, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X18, X12, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X11, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X17, X17, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
DUP Z0.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
SUB X16, X16, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X20, X20, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z1.D, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
HINT #0
HINT #0
LDUR X14, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X16, 486e8c <.omp_outlined.+0x64c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 486f18 <.omp_outlined.+0x6d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X14, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W13, W14, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
TBZ W13, #0, 486eb4 <.omp_outlined.+0x674>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X11, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X13, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X13, [X11, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X12, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X13, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X13, [X12, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X14, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 486f18 <.omp_outlined.+0x6d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X10, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X11, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X12, X14, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
LDP X20, X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined.#0x486840–	0.74	0.28
○Loop 52 - par_csr_matop.c:265-266 - exec	0.02	0.01
○Loop 51 - par_csr_matop.c:263-266 - exec	0	0
▼Loop 62 - par_csr_matop.c:127-242 - exec–	0	0
▼Loop 57 - par_csr_matop.c:127-242 - exec–	0	0
▼Loop 56 - par_csr_matop.c:127-242 - exec–	0.22	0.07
○Loop 58 - par_csr_matop.c:195-208 - exec	0.46	0.15
▼Loop 55 - par_csr_matop.c:127-242 - exec–	0.04	0.01
▼Loop 59 - par_csr_matop.c:146-177 - exec–	0	0
○Loop 61 - par_csr_matop.c:154-167 - exec	0	0
○Loop 60 - par_csr_matop.c:170-177 - exec	0	0
○Loop 53 - par_csr_matop.c:259-260 - exec	0	0
○Loop 54 - par_csr_matop.c:257-260 - exec	0	0
○Loop 50 - par_csr_matop.c:273-276 - exec	0	0
○Loop 63 - par_csr_matop.c:124-125 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code