OV - exec - Function .omp_outlined.#0x47b720

	Function: .omp_outlined.#0x47b720	Module: exec	Source: ams.c:3363-3540 [...]	Coverage: 0.23%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3363 - 3540

--------------------------------------------------------------------------------

3363: #pragma omp parallel for private(i,ii,j,k,ns,ne,rest,size,diag,cf_diag) HYPRE_SMP_SCHEDULE

3364: #endif

3365:    for (k = 0; k < num_threads; k++)

3366:    {

3367:       size = num_rows/num_threads;

3368:       rest = num_rows - size*num_threads;

3369:       if (k < rest)

3370:       {

3371:          ns = k*size+k;

3372:          ne = (k+1)*size+k+1;

3373:       }

3374:       else

3375:       {

3376:          ns = k*size+rest;

3377:          ne = (k+1)*size+rest;

3378:       }

3379:

3380:       if (option == 1)

3381:       {

3382:          for (i = ns; i < ne; i++)

3383:          {

3384:             l1_norm[i] = 0.0;

3385:             if (cf_marker == NULL)

3386:             {

3387:                /* Add the l1 norm of the diag part of the ith row */

3388:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3389:                   l1_norm[i] += fabs(A_diag_data[j]);

3390:                /* Add the l1 norm of the offd part of the ith row */

3391:                if (num_cols_offd)

3392:                {

3393:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3394:                      l1_norm[i] += fabs(A_offd_data[j]);

3395:                }

3396:             }

3397:             else

3398:             {

3399:                cf_diag = cf_marker[i];

3400:                /* Add the CF l1 norm of the diag part of the ith row */

3401:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3402:                   if (cf_diag == cf_marker[A_diag_J[j]])

3403:                      l1_norm[i] += fabs(A_diag_data[j]);

3404:                /* Add the CF l1 norm of the offd part of the ith row */

3405:                if (num_cols_offd)

3406:                {

3407:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3408:                      if (cf_diag == cf_marker_offd[A_offd_J[j]])

3409:                         l1_norm[i] += fabs(A_offd_data[j]);

[...]

3416:          for (i = ns; i < ne; i++)

3417:          {

3418:             l1_norm[i] = 0.0;

3419:             if (cf_marker == NULL)

3420:             {

3421:                /* Add the diagonal and the local off-thread part of the ith row */

3422:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3423:                {

3424:                   ii = A_diag_J[j];

3425:                   if (ii == i || ii < ns || ii >= ne)

3426:                      l1_norm[i] += fabs(A_diag_data[j]);

3427:                }

3428:                /* Add the l1 norm of the offd part of the ith row */

3429:                if (num_cols_offd)

3430:                {

3431:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3432:                      l1_norm[i] += fabs(A_offd_data[j]);

3433:                }

3434:             }

3435:             else

3436:             {

3437:                cf_diag = cf_marker[i];

3438:                /* Add the diagonal and the local off-thread part of the ith row */

3439:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3440:                {

3441:                   ii = A_diag_J[j];

3442:                   if ((ii == i || ii < ns || ii >= ne) &&

3443:                       (cf_diag == cf_marker[A_diag_J[j]]))

3444:                      l1_norm[i] += fabs(A_diag_data[j]);

3445:                }

3446:                /* Add the CF l1 norm of the offd part of the ith row */

3447:                if (num_cols_offd)

3448:                {

3449:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3450:                      if (cf_diag == cf_marker_offd[A_offd_J[j]])

3451:                         l1_norm[i] += fabs(A_offd_data[j]);

[...]

3458:          for (i = ns; i < ne; i++)

3459:          {

3460:             l1_norm[i] = 0.0;

3461:             for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3462:                l1_norm[i] += A_diag_data[j] * A_diag_data[j];

3463:             if (num_cols_offd)

3464:                for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3465:                   l1_norm[i] += A_offd_data[j] * A_offd_data[j];

3466:          }

3467:       }

3468:       else if (option == 4)

3469:       {

3470:          for (i = ns; i < ne; i++)

3471:          {

3472:             l1_norm[i] = 0.0;

3473:             if (cf_marker == NULL)

3474:             {

3475:                /* Add the diagonal and the local off-thread part of the ith row */

3476:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3477:                {

3478:                   ii = A_diag_J[j];

3479:                   if (ii == i || ii < ns || ii >= ne)

3480:                   {

3481:                      if (ii == i)

[...]

3493:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3494:                      l1_norm[i] += 0.5*fabs(A_offd_data[j]);

3495:                }

3496:             }

3497:             else

3498:             {

3499:                cf_diag = cf_marker[i];

3500:                /* Add the diagonal and the local off-thread part of the ith row */

3501:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3502:                {

3503:                   ii = A_diag_J[j];

3504:                   if ((ii == i || ii < ns || ii >= ne) &&

3505:                       (cf_diag == cf_marker[A_diag_J[j]]))

3506:                   {

3507:                      if (ii == i)

[...]

3517:                if (num_cols_offd)

3518:                {

3519:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3520:                      if (cf_diag == cf_marker_offd[A_offd_J[j]])

3521:                         l1_norm[i] += 0.5*fabs(A_offd_data[j]);

3522:                }

3523:             }

3524:

3525:             /* Truncate according to Remark 6.2 */

3526:             if (l1_norm[i] <= 4.0/3.0*diag)

3527:                l1_norm[i] = diag;

3528:          }

3529:       }

3530:

3531:       /* Handle negative definite matrices */

3532:       for (i = ns; i < ne; i++)

3533:          if (A_diag_data[A_diag_I[i]] < 0)

3534:             l1_norm[i] = -l1_norm[i];

3535:

3536:       for (i = ns; i < ne; i++)

3537:          /* if (fabs(l1_norm[i]) < DBL_EPSILON) */

3538:          if (fabs(l1_norm[i]) == 0.0)

3539:          {

3540:             hypre_error_in_arg(1);

0x47b720 SUB	SP, SP, #256

0x47b724 STP	D9, D8, [SP, #144]

0x47b728 STP	X29, X30, [SP, #160]

0x47b72c STP	X28, X27, [SP, #176]

0x47b730 STP	X26, X25, [SP, #192]

0x47b734 STP	X24, X23, [SP, #208]

0x47b738 STP	X22, X21, [SP, #224]

0x47b73c STP	X20, X19, [SP, #240]

0x47b740 ADD	X29, SP, #160

0x47b744 LDR	X8, [X2]

0x47b748 STP	X5, X7, [SP, #72]

0x47b74c STR	X6, [SP, #48]

0x47b750 SUBS	X19, X8, #1

0x47b754 STP	X3, X4, [X29, #960]

0x47b758 STUR	X2, [X29, #440]

0x47b75c B.LT	47c8b4

0x47b760 LDR	W20, [X0]

0x47b764 MOVZ	W8, #1

0x47b768 ADRP	X0,

0x47b76c ADD	X0, X0, #784

0x47b770 SUB	X3, X29, #44

0x47b774 STP	X19, XZR, [X29, #992]

0x47b778 STUR	WZR, [X29, #468]

0x47b77c SUB	X4, X29, #24

0x47b780 SUB	X5, X29, #32

0x47b784 SUB	X6, X29, #40

0x47b788 MOVZ	W2, #34

0x47b78c STUR	X8, [X29, #472]

0x47b790 STR	X8, [SP]

0x47b794 MOVZ	W7, #1

0x47b798 ORR	W1, WZR, W20

0x47b79c BL	40f550

0x47b7a0 LDP	X8, X28, [X29, #992]

0x47b7a4 CMP	X8, X19

0x47b7a8 CSEL	X27, X8, X19, #11

0x47b7ac CMP	X28, X27

0x47b7b0 STUR	X27, [X29, #480]

0x47b7b4 B.GT	47c8a4

0x47b7b8 LDR	X8, [X29, #144]

0x47b7bc LDR	X19, [X29, #96]

0x47b7c0 STR	W20, [SP, #20]

0x47b7c4 CNTW	X25, ALL

0x47b7c8 PTRUE	P0.D, ALL

0x47b7cc FMOV	D8, #0.5000000

0x47b7d0 ORR	X20, XZR, #3840

0x47b7d4 MOVK	X20, #16373

0x47b7d8 STR	X8, [SP, #32]

0x47b7dc LDR	X8, [X29, #136]

0x47b7e0 STR	X8, [SP, #24]

0x47b7e4 LDR	X8, [X29, #128]

0x47b7e8 STR	X8, [SP, #40]

0x47b7ec LDP	X8, X26, [X29, #112]

0x47b7f0 STR	X8, [SP, #64]

0x47b7f4 LDR	X8, [X29, #104]

0x47b7f8 STR	X8, [SP, #56]

0x47b7fc B	47b828

  (67) 0x47b800 ORR	X3, XZR, XZR

  (67) 0x47b804 ADRP	X0,

  (67) 0x47b808 ADD	X0, X0, #280

  (67) 0x47b80c MOVZ	W1, #3540

  (67) 0x47b810 MOVZ	W2, #12

  (67) 0x47b814 BL	4b0fc0

  (67) 0x47b818 PTRUE	P0.D, ALL

    (65) 0x47b81c CMP	X28, X27

    (65) 0x47b820 ORR	X28, XZR, X21

    (65) 0x47b824 B.EQ	47c8a0

    (65) 0x47b828 LDP	X9, X8, [X29, #952]

    (65) 0x47b82c ADD	X21, X28, #1

    (65) 0x47b830 LDR	X8, [X8]

    (65) 0x47b834 LDR	X9, [X9]

    (65) 0x47b838 SDIV	X10, X8, X9

    (65) 0x47b83c MSUB	X8, X10, X9, X8

    (65) 0x47b840 CMP	X28, X8

    (65) 0x47b844 MADD	X9, X10, X28, X8

    (65) 0x47b848 MADD	X11, X10, X21, X8

    (65) 0x47b84c ADD	X8, X10, #1

    (65) 0x47b850 MADD	X10, X8, X28, XZR

    (65) 0x47b854 MADD	X12, X8, X21, XZR

    (65) 0x47b858 CSEL	X8, X9, X10, #10

    (65) 0x47b85c LDUR	X10, [X29, #456]

    (65) 0x47b860 CSEL	X9, X11, X12, #10

    (65) 0x47b864 LDR	X10, [X10]

    (65) 0x47b868 CMP	X10, #1

    (65) 0x47b86c B.EQ	47bce0

    (65) 0x47b870 CMP	X10, #2

    (65) 0x47b874 B.EQ	47bb00

    (65) 0x47b878 CMP	X10, #3

    (65) 0x47b87c B.NE	47bf28

    (65) 0x47b880 CMP	X9, X8

    (65) 0x47b884 B.LE	47c7a0

    (65) 0x47b888 LDP	X11, X12, [SP, #72]

    (65) 0x47b88c LDP	X14, X15, [SP, #56]

    (65) 0x47b890 LDR	X13, [X19]

    (65) 0x47b894 UBFM	X16, X8, #61, #60

    (65) 0x47b898 ORR	X10, XZR, XZR

    (65) 0x47b89c ORR	X3, XZR, X8

    (65) 0x47b8a0 ADD	X0, X13, #16

    (65) 0x47b8a4 LDR	X12, [X12]

    (65) 0x47b8a8 LDR	X11, [X11]

    (65) 0x47b8ac LDR	X17, [X26]

    (65) 0x47b8b0 LDR	X14, [X14]

    (65) 0x47b8b4 LDR	X15, [X15]

    (65) 0x47b8b8 ADD	X2, X17, #16

    (65) 0x47b8bc LDR	X1, [X12, X16]

    (65) 0x47b8c0 ADD	X16, X11, X16

    (65) 0x47b8c4 ADD	X18, X16, #8

    (65) 0x47b8c8 B	47b8d8

      (91) 0x47b8cc ADD	X10, X10, #1

      (91) 0x47b8d0 CMP	X3, X9

      (91) 0x47b8d4 B.EQ	47c7a0

      (91) 0x47b8d8 ORR	X4, XZR, X3

      (91) 0x47b8dc STR	XZR, [X11, X3,LSL #3]

      (91) 0x47b8e0 ADD	X3, X3, #1

      (91) 0x47b8e4 ORR	X5, XZR, X1

      (91) 0x47b8e8 MOVI	D0, #0

      (91) 0x47b8ec LDR	X1, [X12, X3,LSL #3]

      (91) 0x47b8f0 CMP	X1, X5

      (91) 0x47b8f4 B.LE	47b99c

      (91) 0x47b8f8 SUB	W6, W1, W5

      (91) 0x47b8fc MOVI	D0, #0

      (91) 0x47b900 ANDS	X7, X6, #4160

      (91) 0x47b904 B.EQ	47b938

      (91) 0x47b908 ORR	X6, XZR, X5

        (96) 0x47b90c LDR	D1, [X13, X6,LSL #3]

        (96) 0x47b910 ADD	X6, X6, #1

        (96) 0x47b914 SUBS	X7, X7, #1

        (96) 0x47b918 FMADD	D0, D1, D1, D0

        (96) 0x47b91c STR	D0, [X11, X4,LSL #3]

        (96) 0x47b920 B.NE	47b90c

      (91) 0x47b924 ORN	X5, XZR, X5

      (91) 0x47b928 ADD	X5, X1, X5

      (91) 0x47b92c CMP	X5, #3

      (91) 0x47b930 B.CS	47b94c

      (91) 0x47b934 B	47b99c

      (91) 0x47b938 ORR	X6, XZR, X5

      (91) 0x47b93c ORN	X5, XZR, X5

      (91) 0x47b940 ADD	X5, X1, X5

      (91) 0x47b944 CMP	X5, #3

      (91) 0x47b948 B.CC	47b99c

      (91) 0x47b94c SUB	X5, X1, X6

      (91) 0x47b950 ADD	X6, X0, X6,LSL #3

      (91) 0x47b954 HINT	#0

      (91) 0x47b958 HINT	#0

      (91) 0x47b95c HINT	#0

        (95) 0x47b960 LDUR	D1, [X6, #496]

        (95) 0x47b964 SUBS	X5, X5, #4

        (95) 0x47b968 FMADD	D0, D1, D1, D0

        (95) 0x47b96c STR	D0, [X11, X4,LSL #3]

        (95) 0x47b970 LDUR	D1, [X6, #504]

        (95) 0x47b974 FMADD	D0, D1, D1, D0

        (95) 0x47b978 STR	D0, [X11, X4,LSL #3]

        (95) 0x47b97c LDR	D1, [X6]

        (95) 0x47b980 FMADD	D0, D1, D1, D0

        (95) 0x47b984 STR	D0, [X11, X4,LSL #3]

        (95) 0x47b988 LDR	D1, [X6, #8]

        (95) 0x47b98c ADD	X6, X6, #32

        (95) 0x47b990 FMADD	D0, D1, D1, D0

        (95) 0x47b994 STR	D0, [X11, X4,LSL #3]

        (95) 0x47b998 B.NE	47b960

      (91) 0x47b99c CBZ	X14, 47b8cc

      (91) 0x47b9a0 LDR	X6, [X15, X4,LSL #3]

      (91) 0x47b9a4 LDR	X5, [X15, X3,LSL #3]

      (91) 0x47b9a8 SUBS	X7, X5, X6

      (91) 0x47b9ac B.LE	47b8cc

      (91) 0x47b9b0 CMP	X25, #12

      (91) 0x47b9b4 MOVZ	W22, #12

      (91) 0x47b9b8 CSEL	X22, X25, X22, #8

      (91) 0x47b9bc CMP	X7, X22

      (91) 0x47b9c0 B.CC	47bae0

      (91) 0x47b9c4 UBFM	X22, X10, #61, #60

      (91) 0x47b9c8 ADD	X30, X17, X5,LSL #3

      (91) 0x47b9cc ADD	X24, X17, X6,LSL #3

      (91) 0x47b9d0 ADD	X23, X16, X22

      (91) 0x47b9d4 ADD	X22, X18, X22

      (91) 0x47b9d8 CMP	X23, X30

      (91) 0x47b9dc CCMP	X24, X22, #2, #3

      (91) 0x47b9e0 B.CC	47bae0

      (91) 0x47b9e4 UDIV	X22, X7, X25

      (91) 0x47b9e8 UBFM	X24, X6, #61, #60

      (91) 0x47b9ec ORR	X30, XZR, XZR

      (91) 0x47b9f0 MADD	X22, X22, X25, XZR

      (91) 0x47b9f4 ADD	X23, X6, X22

      (91) 0x47b9f8 ADD	X6, X17, X24

      (91) 0x47b9fc ADDVL	X24, X24, #1

      (91) 0x47ba00 SUB	X7, X7, X22

      (91) 0x47ba04 ADD	X24, X17, X24

        (94) 0x47ba08 LD1D	{Z1.D}, P0/Z, [X6, X30,LSL #3]

        (94) 0x47ba0c LD1D	{Z2.D}, P0/Z, [X24, X30,LSL #3]

        (94) 0x47ba10 ADD	X30, X30, X25

        (94) 0x47ba14 CMP	X22, X30

        (94) 0x47ba18 FMUL	Z1.D, Z1.D, Z1.D

        (94) 0x47ba1c FMUL	Z2.D, Z2.D, Z2.D

        (94) 0x47ba20 FADDA	D0, P0, D0, Z1.D

        (94) 0x47ba24 FADDA	D0, P0, D0, Z2.D

        (94) 0x47ba28 B.NE	47ba08

      (91) 0x47ba2c STR	D0, [X11, X4,LSL #3]

      (91) 0x47ba30 CBZ	X7, 47b8cc

      (91) 0x47ba34 HINT	#0

      (91) 0x47ba38 HINT	#0

      (91) 0x47ba3c HINT	#0

      (91) 0x47ba40 SUB	W6, W5, W23

      (91) 0x47ba44 ORR	X7, XZR, X23

      (91) 0x47ba48 ANDS	X6, X6, #4160

      (91) 0x47ba4c B.EQ	47ba78

      (91) 0x47ba50 HINT	#0

      (91) 0x47ba54 HINT	#0

      (91) 0x47ba58 HINT	#0

      (91) 0x47ba5c HINT	#0

        (92) 0x47ba60 LDR	D1, [X17, X7,LSL #3]

        (92) 0x47ba64 ADD	X7, X7, #1

        (92) 0x47ba68 SUBS	X6, X6, #1

        (92) 0x47ba6c FMADD	D0, D1, D1, D0

        (92) 0x47ba70 STR	D0, [X11, X4,LSL #3]

        (92) 0x47ba74 B.NE	47ba60

      (91) 0x47ba78 ORN	X6, XZR, X23

      (91) 0x47ba7c ADD	X6, X5, X6

      (91) 0x47ba80 CMP	X6, #3

      (91) 0x47ba84 B.CC	47b8cc

      (91) 0x47ba88 SUB	X5, X5, X7

      (91) 0x47ba8c ADD	X6, X2, X7,LSL #3

      (91) 0x47ba90 HINT	#0

      (91) 0x47ba94 HINT	#0

      (91) 0x47ba98 HINT	#0

      (91) 0x47ba9c HINT	#0

        (93) 0x47baa0 LDUR	D1, [X6, #496]

        (93) 0x47baa4 SUBS	X5, X5, #4

        (93) 0x47baa8 FMADD	D0, D1, D1, D0

        (93) 0x47baac STR	D0, [X11, X4,LSL #3]

        (93) 0x47bab0 LDUR	D1, [X6, #504]

        (93) 0x47bab4 FMADD	D0, D1, D1, D0

        (93) 0x47bab8 STR	D0, [X11, X4,LSL #3]

        (93) 0x47babc LDR	D1, [X6]

        (93) 0x47bac0 FMADD	D0, D1, D1, D0

        (93) 0x47bac4 STR	D0, [X11, X4,LSL #3]

        (93) 0x47bac8 LDR	D1, [X6, #8]

        (93) 0x47bacc ADD	X6, X6, #32

        (93) 0x47bad0 FMADD	D0, D1, D1, D0

        (93) 0x47bad4 STR	D0, [X11, X4,LSL #3]

        (93) 0x47bad8 B.NE	47baa0

      (91) 0x47badc B	47b8cc

      (91) 0x47bae0 ORR	X23, XZR, X6

      (91) 0x47bae4 SUB	W6, W5, W23

      (91) 0x47bae8 ORR	X7, XZR, X23

      (91) 0x47baec ANDS	X6, X6, #4160

      (91) 0x47baf0 B.NE	47ba60

      (91) 0x47baf4 B	47ba78

0x47baf8 HINT	#0

0x47bafc HINT	#0

    (65) 0x47bb00 CMP	X9, X8

    (65) 0x47bb04 B.LE	47c7a0

    (65) 0x47bb08 LDP	X12, X11, [SP, #40]

    (65) 0x47bb0c LDP	X14, X10, [SP, #64]

    (65) 0x47bb10 LDR	X13, [SP, #56]

    (65) 0x47bb14 LDR	X15, [X11]

    (65) 0x47bb18 LDR	X11, [SP, #80]

    (65) 0x47bb1c LDR	X10, [X10]

    (65) 0x47bb20 LDR	X12, [X12]

    (65) 0x47bb24 LDR	X13, [X13]

    (65) 0x47bb28 LDR	X14, [X14]

    (65) 0x47bb2c LDR	X11, [X11]

    (65) 0x47bb30 CBZ	X15, 47c278

    (65) 0x47bb34 LDP	X16, X17, [SP, #24]

    (65) 0x47bb38 LDR	X5, [X11, X8,LSL #3]

    (65) 0x47bb3c ORR	X0, XZR, X8

    (65) 0x47bb40 LDR	X17, [X17]

    (65) 0x47bb44 LDR	X16, [X16]

    (65) 0x47bb48 ADD	X18, X17, #8

    (65) 0x47bb4c B	47bb6c

0x47bb50 HINT	#0

0x47bb54 HINT	#0

0x47bb58 HINT	#0

0x47bb5c HINT	#0

      (82) 0x47bb60 ORR	X5, XZR, X2

      (82) 0x47bb64 CMP	X0, X9

      (82) 0x47bb68 B.EQ	47c7a0

      (82) 0x47bb6c STR	XZR, [X10, X0,LSL #3]

      (82) 0x47bb70 ORR	X1, XZR, X0

      (82) 0x47bb74 MOVI	D0, #0

      (82) 0x47bb78 LDR	X3, [X15, X0,LSL #3]

      (82) 0x47bb7c ADD	X0, X0, #1

      (82) 0x47bb80 LDR	X2, [X11, X0,LSL #3]

      (82) 0x47bb84 CMP	X5, X2

      (82) 0x47bb88 B.GE	47bbec

      (82) 0x47bb8c LDR	X4, [X19]

      (82) 0x47bb90 UBFM	X6, X5, #61, #60

      (82) 0x47bb94 SUB	X5, X2, X5

      (82) 0x47bb98 MOVI	D0, #0

      (82) 0x47bb9c ADD	X4, X4, X6

      (82) 0x47bba0 ADD	X6, X12, X6

      (82) 0x47bba4 B	47bbb8

        (84) 0x47bba8 ADD	X4, X4, #8

        (84) 0x47bbac SUBS	X5, X5, #1

        (84) 0x47bbb0 ADD	X6, X6, #8

        (84) 0x47bbb4 B.EQ	47bbec

        (84) 0x47bbb8 LDR	X7, [X6]

        (84) 0x47bbbc CMP	X7, X1

        (84) 0x47bbc0 CCMP	X7, X8, #8, #1

        (84) 0x47bbc4 CCMP	X7, X9, #0, #10

        (84) 0x47bbc8 B.LT	47bba8

        (84) 0x47bbcc LDR	X7, [X15, X7,LSL #3]

        (84) 0x47bbd0 CMP	X3, X7

        (84) 0x47bbd4 B.NE	47bba8

        (84) 0x47bbd8 LDR	D1, [X4]

        (84) 0x47bbdc FABS	D1, D1

        (84) 0x47bbe0 FADD	D0, D0, D1

        (84) 0x47bbe4 STR	D0, [X10, X1,LSL #3]

        (84) 0x47bbe8 B	47bba8

      (82) 0x47bbec CBZ	X13, 47bb60

      (82) 0x47bbf0 LDR	X5, [X14, X1,LSL #3]

      (82) 0x47bbf4 LDR	X4, [X14, X0,LSL #3]

      (82) 0x47bbf8 CMP	X4, X5

      (82) 0x47bbfc B.LE	47bb60

      (82) 0x47bc00 LDR	X6, [X26]

      (82) 0x47bc04 SUB	W7, W4, W5

      (82) 0x47bc08 TBNZ	W7, #0, 47bc20

      (82) 0x47bc0c ORR	X7, XZR, X5

      (82) 0x47bc10 ADD	X5, X5, #1

      (82) 0x47bc14 CMP	X4, X5

      (82) 0x47bc18 B.EQ	47bb60

      (82) 0x47bc1c B	47bc50

      (82) 0x47bc20 LDR	X7, [X17, X5,LSL #3]

      (82) 0x47bc24 LDR	X7, [X16, X7,LSL #3]

      (82) 0x47bc28 CMP	X3, X7

      (82) 0x47bc2c B.NE	47bc40

      (82) 0x47bc30 LDR	D1, [X6, X5,LSL #3]

      (82) 0x47bc34 FABS	D1, D1

      (82) 0x47bc38 FADD	D0, D0, D1

      (82) 0x47bc3c STR	D0, [X10, X1,LSL #3]

      (82) 0x47bc40 ADD	X7, X5, #1

      (82) 0x47bc44 ADD	X5, X5, #1

      (82) 0x47bc48 CMP	X4, X5

      (82) 0x47bc4c B.EQ	47bb60

      (82) 0x47bc50 SUB	X4, X4, X7

      (82) 0x47bc54 UBFM	X7, X7, #61, #60

      (82) 0x47bc58 ADD	X6, X6, X7

      (82) 0x47bc5c ADD	X5, X18, X7

      (82) 0x47bc60 ADD	X6, X6, #8

      (82) 0x47bc64 B	47bc78

        (83) 0x47bc68 SUBS	X4, X4, #2

        (83) 0x47bc6c ADD	X5, X5, #16

        (83) 0x47bc70 ADD	X6, X6, #16

        (83) 0x47bc74 B.EQ	47bb60

        (83) 0x47bc78 LDUR	X7, [X5, #504]

        (83) 0x47bc7c LDR	X7, [X16, X7,LSL #3]

        (83) 0x47bc80 CMP	X3, X7

        (83) 0x47bc84 B.NE	47bcac

        (83) 0x47bc88 LDUR	D1, [X6, #504]

        (83) 0x47bc8c FABS	D1, D1

        (83) 0x47bc90 FADD	D0, D0, D1

        (83) 0x47bc94 STR	D0, [X10, X1,LSL #3]

        (83) 0x47bc98 LDR	X7, [X5]

        (83) 0x47bc9c LDR	X7, [X16, X7,LSL #3]

        (83) 0x47bca0 CMP	X3, X7

        (83) 0x47bca4 B.NE	47bc68

        (83) 0x47bca8 B	47bcbc

        (83) 0x47bcac LDR	X7, [X5]

        (83) 0x47bcb0 LDR	X7, [X16, X7,LSL #3]

        (83) 0x47bcb4 CMP	X3, X7

        (83) 0x47bcb8 B.NE	47bc68

        (83) 0x47bcbc LDR	D1, [X6]

        (83) 0x47bcc0 FABS	D1, D1

        (83) 0x47bcc4 FADD	D0, D0, D1

        (83) 0x47bcc8 STR	D0, [X10, X1,LSL #3]

        (83) 0x47bccc B	47bc68

0x47bcd0 HINT	#0

0x47bcd4 HINT	#0

0x47bcd8 HINT	#0

0x47bcdc HINT	#0

    (65) 0x47bce0 CMP	X9, X8

    (65) 0x47bce4 B.LE	47c7a0

    (65) 0x47bce8 LDP	X11, X12, [SP, #48]

    (65) 0x47bcec LDP	X13, X10, [SP, #64]

    (65) 0x47bcf0 LDR	X14, [X11]

    (65) 0x47bcf4 LDR	X11, [SP, #80]

    (65) 0x47bcf8 LDR	X10, [X10]

    (65) 0x47bcfc LDR	X12, [X12]

    (65) 0x47bd00 LDR	X13, [X13]

    (65) 0x47bd04 LDR	X11, [X11]

    (65) 0x47bd08 CBZ	X14, 47c51c

    (65) 0x47bd0c LDP	X17, X15, [SP, #32]

    (65) 0x47bd10 LDR	X16, [SP, #24]

    (65) 0x47bd14 LDR	X1, [X11, X8,LSL #3]

    (65) 0x47bd18 ORR	X2, XZR, X8

    (65) 0x47bd1c LDR	X15, [X15]

    (65) 0x47bd20 LDR	X17, [X17]

    (65) 0x47bd24 LDR	X16, [X16]

    (65) 0x47bd28 ADD	X18, X15, #8

    (65) 0x47bd2c ADD	X0, X17, #8

    (65) 0x47bd30 B	47bd48

0x47bd34 HINT	#0

0x47bd38 HINT	#0

0x47bd3c HINT	#0

      (74) 0x47bd40 CMP	X2, X9

      (74) 0x47bd44 B.EQ	47c7a0

      (74) 0x47bd48 STR	XZR, [X10, X2,LSL #3]

      (74) 0x47bd4c ORR	X3, XZR, X2

      (74) 0x47bd50 ORR	X5, XZR, X1

      (74) 0x47bd54 MOVI	D0, #0

      (74) 0x47bd58 LDR	X4, [X14, X2,LSL #3]

      (74) 0x47bd5c ADD	X2, X2, #1

      (74) 0x47bd60 LDR	X1, [X11, X2,LSL #3]

      (74) 0x47bd64 CMP	X1, X5

      (74) 0x47bd68 B.LE	47bdb0

      (74) 0x47bd6c LDR	X7, [X19]

      (74) 0x47bd70 SUB	W22, W1, W5

      (74) 0x47bd74 MOVI	D0, #0

      (74) 0x47bd78 ORR	X6, XZR, X5

      (74) 0x47bd7c TBZ	W22, #0, 47bda4

      (74) 0x47bd80 LDR	X6, [X15, X5,LSL #3]

      (74) 0x47bd84 MOVI	D0, #0

      (74) 0x47bd88 LDR	X6, [X14, X6,LSL #3]

      (74) 0x47bd8c CMP	X4, X6

      (74) 0x47bd90 B.NE	47bda0

      (74) 0x47bd94 LDR	D0, [X7, X5,LSL #3]

      (74) 0x47bd98 FABS	D0, D0

      (74) 0x47bd9c STR	D0, [X10, X3,LSL #3]

      (74) 0x47bda0 ADD	X6, X5, #1

      (74) 0x47bda4 ADD	X5, X5, #1

      (74) 0x47bda8 CMP	X1, X5

      (74) 0x47bdac B.NE	47bde4

      (74) 0x47bdb0 CBZ	X12, 47bd40

      (74) 0x47bdb4 LDR	X6, [X13, X3,LSL #3]

      (74) 0x47bdb8 LDR	X5, [X13, X2,LSL #3]

      (74) 0x47bdbc CMP	X5, X6

      (74) 0x47bdc0 B.LE	47bd40

      (74) 0x47bdc4 LDR	X7, [X26]

      (74) 0x47bdc8 SUB	W22, W5, W6

      (74) 0x47bdcc TBNZ	W22, #0, 47be68

      (74) 0x47bdd0 ORR	X22, XZR, X6

      (74) 0x47bdd4 ADD	X6, X6, #1

      (74) 0x47bdd8 CMP	X5, X6

      (74) 0x47bddc B.EQ	47bd40

      (74) 0x47bde0 B	47be98

      (74) 0x47bde4 UBFM	X22, X6, #61, #60

      (74) 0x47bde8 SUB	X5, X1, X6

      (74) 0x47bdec ADD	X7, X7, X22

      (74) 0x47bdf0 ADD	X6, X18, X22

      (74) 0x47bdf4 ADD	X7, X7, #8

      (74) 0x47bdf8 B	47be10

0x47bdfc HINT	#0

        (76) 0x47be00 SUBS	X5, X5, #2

        (76) 0x47be04 ADD	X6, X6, #16

        (76) 0x47be08 ADD	X7, X7, #16

        (76) 0x47be0c B.EQ	47bdb0

        (76) 0x47be10 LDUR	X22, [X6, #504]

        (76) 0x47be14 LDR	X22, [X14, X22,LSL #3]

        (76) 0x47be18 CMP	X4, X22

        (76) 0x47be1c B.NE	47be44

        (76) 0x47be20 LDUR	D1, [X7, #504]

        (76) 0x47be24 FABS	D1, D1

        (76) 0x47be28 FADD	D0, D0, D1

        (76) 0x47be2c STR	D0, [X10, X3,LSL #3]

        (76) 0x47be30 LDR	X22, [X6]

        (76) 0x47be34 LDR	X22, [X14, X22,LSL #3]

        (76) 0x47be38 CMP	X4, X22

        (76) 0x47be3c B.NE	47be00

        (76) 0x47be40 B	47be54

        (76) 0x47be44 LDR	X22, [X6]

        (76) 0x47be48 LDR	X22, [X14, X22,LSL #3]

        (76) 0x47be4c CMP	X4, X22

        (76) 0x47be50 B.NE	47be00

        (76) 0x47be54 LDR	D1, [X7]

        (76) 0x47be58 FABS	D1, D1

        (76) 0x47be5c FADD	D0, D0, D1

        (76) 0x47be60 STR	D0, [X10, X3,LSL #3]

        (76) 0x47be64 B	47be00

      (74) 0x47be68 LDR	X22, [X17, X6,LSL #3]

      (74) 0x47be6c LDR	X22, [X16, X22,LSL #3]

      (74) 0x47be70 CMP	X4, X22

      (74) 0x47be74 B.NE	47be88

      (74) 0x47be78 LDR	D1, [X7, X6,LSL #3]

      (74) 0x47be7c FABS	D1, D1

      (74) 0x47be80 FADD	D0, D0, D1

      (74) 0x47be84 STR	D0, [X10, X3,LSL #3]

      (74) 0x47be88 ADD	X22, X6, #1

      (74) 0x47be8c ADD	X6, X6, #1

      (74) 0x47be90 CMP	X5, X6

      (74) 0x47be94 B.EQ	47bd40

      (74) 0x47be98 SUB	X5, X5, X22

      (74) 0x47be9c UBFM	X22, X22, #61, #60

      (74) 0x47bea0 ADD	X7, X7, X22

      (74) 0x47bea4 ADD	X6, X0, X22

      (74) 0x47bea8 ADD	X7, X7, #8

      (74) 0x47beac B	47bed0

0x47beb0 HINT	#0

0x47beb4 HINT	#0

0x47beb8 HINT	#0

0x47bebc HINT	#0

        (75) 0x47bec0 SUBS	X5, X5, #2

        (75) 0x47bec4 ADD	X6, X6, #16

        (75) 0x47bec8 ADD	X7, X7, #16

        (75) 0x47becc B.EQ	47bd40

        (75) 0x47bed0 LDUR	X22, [X6, #504]

        (75) 0x47bed4 LDR	X22, [X16, X22,LSL #3]

        (75) 0x47bed8 CMP	X4, X22

        (75) 0x47bedc B.NE	47bf04

        (75) 0x47bee0 LDUR	D1, [X7, #504]

        (75) 0x47bee4 FABS	D1, D1

        (75) 0x47bee8 FADD	D0, D0, D1

        (75) 0x47beec STR	D0, [X10, X3,LSL #3]

        (75) 0x47bef0 LDR	X22, [X6]

        (75) 0x47bef4 LDR	X22, [X16, X22,LSL #3]

        (75) 0x47bef8 CMP	X4, X22

        (75) 0x47befc B.NE	47bec0

        (75) 0x47bf00 B	47bf14

        (75) 0x47bf04 LDR	X22, [X6]

        (75) 0x47bf08 LDR	X22, [X16, X22,LSL #3]

        (75) 0x47bf0c CMP	X4, X22

        (75) 0x47bf10 B.NE	47bec0

        (75) 0x47bf14 LDR	D1, [X7]

        (75) 0x47bf18 FABS	D1, D1

        (75) 0x47bf1c FADD	D0, D0, D1

        (75) 0x47bf20 STR	D0, [X10, X3,LSL #3]

        (75) 0x47bf24 B	47bec0

    (65) 0x47bf28 CMP	X10, #4

    (65) 0x47bf2c B.NE	47c7a0

    (65) 0x47bf30 CMP	X9, X8

    (65) 0x47bf34 B.LE	47c7a0

    (65) 0x47bf38 LDP	X16, X17, [SP, #24]

    (65) 0x47bf3c LDP	X10, X12, [SP, #72]

    (65) 0x47bf40 LDP	X13, X11, [SP, #40]

    (65) 0x47bf44 ORR	X2, XZR, X8

    (65) 0x47bf48 LDP	X14, X15, [SP, #56]

    (65) 0x47bf4c LDR	X18, [X26]

    (65) 0x47bf50 LDR	X17, [X17]

    (65) 0x47bf54 LDR	X10, [X10]

    (65) 0x47bf58 LDR	X11, [X11]

    (65) 0x47bf5c LDR	X12, [X12]

    (65) 0x47bf60 LDR	X13, [X13]

    (65) 0x47bf64 LDR	X14, [X14]

    (65) 0x47bf68 LDR	X15, [X15]

    (65) 0x47bf6c LDR	X16, [X16]

    (65) 0x47bf70 ADD	X1, X18, #16

    (65) 0x47bf74 ADD	X0, X17, #8

    (65) 0x47bf78 B	47bf8c

0x47bf7c HINT	#0

      (85) 0x47bf80 ADD	X2, X2, #1

      (85) 0x47bf84 CMP	X2, X9

      (85) 0x47bf88 B.EQ	47c7a0

      (85) 0x47bf8c STR	XZR, [X10, X2,LSL #3]

      (85) 0x47bf90 CBZ	X11, 47c060

      (85) 0x47bf94 ADD	X4, X2, #1

      (85) 0x47bf98 LDR	X6, [X12, X2,LSL #3]

      (85) 0x47bf9c LDR	X3, [X11, X2,LSL #3]

      (85) 0x47bfa0 MOVI	D0, #0

      (85) 0x47bfa4 LDR	X7, [X12, X4,LSL #3]

      (85) 0x47bfa8 CMP	X6, X7

      (85) 0x47bfac B.GE	47c020

      (85) 0x47bfb0 LDR	X5, [X19]

      (85) 0x47bfb4 UBFM	X22, X6, #61, #60

      (85) 0x47bfb8 SUB	X6, X7, X6

      (85) 0x47bfbc MOVI	D0, #0

      (85) 0x47bfc0 ADD	X7, X13, X22

      (85) 0x47bfc4 ADD	X5, X5, X22

      (85) 0x47bfc8 B	47bfdc

        (90) 0x47bfcc ADD	X5, X5, #8

        (90) 0x47bfd0 SUBS	X6, X6, #1

        (90) 0x47bfd4 ADD	X7, X7, #8

        (90) 0x47bfd8 B.EQ	47c020

        (90) 0x47bfdc LDR	X22, [X7]

        (90) 0x47bfe0 CMP	X22, X2

        (90) 0x47bfe4 CCMP	X22, X8, #8, #1

        (90) 0x47bfe8 CCMP	X22, X9, #0, #10

        (90) 0x47bfec B.LT	47bfcc

        (90) 0x47bff0 LDR	X23, [X11, X22,LSL #3]

        (90) 0x47bff4 CMP	X3, X23

        (90) 0x47bff8 B.NE	47bfcc

        (90) 0x47bffc LDR	D1, [X5]

        (90) 0x47c000 CMP	X22, X2

        (90) 0x47c004 FABS	D1, D1

        (90) 0x47c008 FMADD	D2, D1, D8, D0

        (90) 0x47c00c FADD	D0, D0, D1

        (90) 0x47c010 FCSEL	D9, D9, D1, #1

        (90) 0x47c014 FCSEL	D0, D2, D0, #1

        (90) 0x47c018 STR	D0, [X10, X2,LSL #3]

        (90) 0x47c01c B	47bfcc

      (85) 0x47c020 CBZ	X14, 47c260

      (85) 0x47c024 LDR	X5, [X15, X2,LSL #3]

      (85) 0x47c028 LDR	X4, [X15, X4,LSL #3]

      (85) 0x47c02c CMP	X4, X5

      (85) 0x47c030 B.LE	47c260

      (85) 0x47c034 LDR	X6, [X26]

      (85) 0x47c038 SUB	W7, W4, W5

      (85) 0x47c03c TBNZ	W7, #0, 47c13c

      (85) 0x47c040 ORR	X7, XZR, X5

      (85) 0x47c044 ADD	X5, X5, #1

      (85) 0x47c048 CMP	X4, X5

      (85) 0x47c04c B.NE	47c16c

      (85) 0x47c050 B	47c260

0x47c054 HINT	#0

0x47c058 HINT	#0

0x47c05c HINT	#0

      (85) 0x47c060 ADD	X3, X2, #1

      (85) 0x47c064 LDR	X5, [X12, X2,LSL #3]

      (85) 0x47c068 MOVI	D0, #0

      (85) 0x47c06c LDR	X4, [X12, X3,LSL #3]

      (85) 0x47c070 CMP	X5, X4

      (85) 0x47c074 B.GE	47c0e8

      (85) 0x47c078 LDR	X6, [X19]

      (85) 0x47c07c UBFM	X7, X5, #61, #60

      (85) 0x47c080 SUB	X4, X4, X5

      (85) 0x47c084 MOVI	D0, #0

      (85) 0x47c088 ADD	X5, X6, X7

      (85) 0x47c08c ADD	X6, X13, X7

      (85) 0x47c090 B	47c0b0

0x47c094 HINT	#0

0x47c098 HINT	#0

0x47c09c HINT	#0

        (88) 0x47c0a0 SUBS	X4, X4, #1

        (88) 0x47c0a4 ADD	X5, X5, #8

        (88) 0x47c0a8 ADD	X6, X6, #8

        (88) 0x47c0ac B.EQ	47c0e8

        (88) 0x47c0b0 LDR	X7, [X6]

        (88) 0x47c0b4 CMP	X7, X2

        (88) 0x47c0b8 CCMP	X7, X8, #8, #1

        (88) 0x47c0bc CCMP	X7, X9, #0, #10

        (88) 0x47c0c0 B.LT	47c0a0

        (88) 0x47c0c4 LDR	D1, [X5]

        (88) 0x47c0c8 CMP	X7, X2

        (88) 0x47c0cc FABS	D1, D1

        (88) 0x47c0d0 FMADD	D2, D1, D8, D0

        (88) 0x47c0d4 FADD	D0, D0, D1

        (88) 0x47c0d8 FCSEL	D9, D9, D1, #1

        (88) 0x47c0dc FCSEL	D0, D2, D0, #1

        (88) 0x47c0e0 STR	D0, [X10, X2,LSL #3]

        (88) 0x47c0e4 B	47c0a0

      (85) 0x47c0e8 CBZ	X14, 47c260

      (85) 0x47c0ec LDR	X4, [X15, X2,LSL #3]

      (85) 0x47c0f0 LDR	X3, [X15, X3,LSL #3]

      (85) 0x47c0f4 CMP	X3, X4

      (85) 0x47c0f8 B.LE	47c260

      (85) 0x47c0fc SUB	W5, W3, W4

      (85) 0x47c100 ANDS	X6, X5, #4160

      (85) 0x47c104 B.EQ	47c1ec

      (85) 0x47c108 ORR	X5, XZR, X4

        (87) 0x47c10c LDR	D1, [X18, X5,LSL #3]

        (87) 0x47c110 ADD	X5, X5, #1

        (87) 0x47c114 SUBS	X6, X6, #1

        (87) 0x47c118 FABS	D1, D1

        (87) 0x47c11c FMADD	D0, D1, D8, D0

        (87) 0x47c120 STR	D0, [X10, X2,LSL #3]

        (87) 0x47c124 B.NE	47c10c

      (85) 0x47c128 ORN	X4, XZR, X4

      (85) 0x47c12c ADD	X4, X3, X4

      (85) 0x47c130 CMP	X4, #3

      (85) 0x47c134 B.CS	47c200

      (85) 0x47c138 B	47c260

      (85) 0x47c13c LDR	X7, [X17, X5,LSL #3]

      (85) 0x47c140 LDR	X7, [X16, X7,LSL #3]

      (85) 0x47c144 CMP	X3, X7

      (85) 0x47c148 B.NE	47c15c

      (85) 0x47c14c LDR	D1, [X6, X5,LSL #3]

      (85) 0x47c150 FABS	D1, D1

      (85) 0x47c154 FMADD	D0, D1, D8, D0

      (85) 0x47c158 STR	D0, [X10, X2,LSL #3]

      (85) 0x47c15c ADD	X7, X5, #1

      (85) 0x47c160 ADD	X5, X5, #1

      (85) 0x47c164 CMP	X4, X5

      (85) 0x47c168 B.EQ	47c260

      (85) 0x47c16c SUB	X4, X4, X7

      (85) 0x47c170 UBFM	X7, X7, #61, #60

      (85) 0x47c174 ADD	X6, X6, X7

      (85) 0x47c178 ADD	X5, X0, X7

      (85) 0x47c17c ADD	X6, X6, #8

      (85) 0x47c180 B	47c194

        (89) 0x47c184 SUBS	X4, X4, #2

        (89) 0x47c188 ADD	X5, X5, #16

        (89) 0x47c18c ADD	X6, X6, #16

        (89) 0x47c190 B.EQ	47c260

        (89) 0x47c194 LDUR	X7, [X5, #504]

        (89) 0x47c198 LDR	X7, [X16, X7,LSL #3]

        (89) 0x47c19c CMP	X3, X7

        (89) 0x47c1a0 B.NE	47c1c8

        (89) 0x47c1a4 LDUR	D1, [X6, #504]

        (89) 0x47c1a8 FABS	D1, D1

        (89) 0x47c1ac FMADD	D0, D1, D8, D0

        (89) 0x47c1b0 STR	D0, [X10, X2,LSL #3]

        (89) 0x47c1b4 LDR	X7, [X5]

        (89) 0x47c1b8 LDR	X7, [X16, X7,LSL #3]

        (89) 0x47c1bc CMP	X3, X7

        (89) 0x47c1c0 B.NE	47c184

        (89) 0x47c1c4 B	47c1d8

        (89) 0x47c1c8 LDR	X7, [X5]

        (89) 0x47c1cc LDR	X7, [X16, X7,LSL #3]

        (89) 0x47c1d0 CMP	X3, X7

        (89) 0x47c1d4 B.NE	47c184

        (89) 0x47c1d8 LDR	D1, [X6]

        (89) 0x47c1dc FABS	D1, D1

        (89) 0x47c1e0 FMADD	D0, D1, D8, D0

        (89) 0x47c1e4 STR	D0, [X10, X2,LSL #3]

        (89) 0x47c1e8 B	47c184

      (85) 0x47c1ec ORR	X5, XZR, X4

      (85) 0x47c1f0 ORN	X4, XZR, X4

      (85) 0x47c1f4 ADD	X4, X3, X4

      (85) 0x47c1f8 CMP	X4, #3

      (85) 0x47c1fc B.CC	47c260

      (85) 0x47c200 SUB	X3, X3, X5

      (85) 0x47c204 ADD	X4, X1, X5,LSL #3

        (86) 0x47c208 LDUR	D1, [X4, #496]

        (86) 0x47c20c SUBS	X3, X3, #4

        (86) 0x47c210 FABS	D1, D1

        (86) 0x47c214 FMADD	D0, D1, D8, D0

        (86) 0x47c218 STR	D0, [X10, X2,LSL #3]

        (86) 0x47c21c LDUR	D1, [X4, #504]

        (86) 0x47c220 FABS	D1, D1

        (86) 0x47c224 FMADD	D0, D1, D8, D0

        (86) 0x47c228 STR	D0, [X10, X2,LSL #3]

        (86) 0x47c22c LDR	D1, [X4]

        (86) 0x47c230 FABS	D1, D1

        (86) 0x47c234 FMADD	D0, D1, D8, D0

        (86) 0x47c238 STR	D0, [X10, X2,LSL #3]

        (86) 0x47c23c LDR	D1, [X4, #8]

        (86) 0x47c240 ADD	X4, X4, #32

        (86) 0x47c244 FABS	D1, D1

        (86) 0x47c248 FMADD	D0, D1, D8, D0

        (86) 0x47c24c STR	D0, [X10, X2,LSL #3]

        (86) 0x47c250 B.NE	47c208

      (85) 0x47c254 HINT	#0

      (85) 0x47c258 HINT	#0

      (85) 0x47c25c HINT	#0

      (85) 0x47c260 FMOV	D1, X20

      (85) 0x47c264 FMUL	D1, D9, D1

      (85) 0x47c268 FCMP	D0, D1

      (85) 0x47c26c B.HI	47bf80

      (85) 0x47c270 STR	D9, [X10, X2,LSL #3]

      (85) 0x47c274 B	47bf80

    (65) 0x47c278 LDR	X16, [X26]

    (65) 0x47c27c UBFM	X17, X8, #61, #60

    (65) 0x47c280 ORR	X3, XZR, X8

    (65) 0x47c284 ADD	X0, X12, #8

    (65) 0x47c288 LDR	X1, [X11, X17]

    (65) 0x47c28c ADD	X17, X10, X17

    (65) 0x47c290 ADD	X18, X17, #8

    (65) 0x47c294 ADD	X2, X16, #16

    (65) 0x47c298 B	47c2ac

0x47c29c HINT	#0

      (77) 0x47c2a0 ADD	X15, X15, #1

      (77) 0x47c2a4 CMP	X3, X9

      (77) 0x47c2a8 B.EQ	47c7a0

      (77) 0x47c2ac ORR	X4, XZR, X3

      (77) 0x47c2b0 STR	XZR, [X10, X3,LSL #3]

      (77) 0x47c2b4 ADD	X3, X3, #1

      (77) 0x47c2b8 ORR	X5, XZR, X1

      (77) 0x47c2bc MOVI	D0, #0

      (77) 0x47c2c0 LDR	X1, [X11, X3,LSL #3]

      (77) 0x47c2c4 CMP	X1, X5

      (77) 0x47c2c8 B.LE	47c314

      (77) 0x47c2cc LDR	X6, [X19]

      (77) 0x47c2d0 SUB	W22, W1, W5

      (77) 0x47c2d4 MOVI	D0, #0

      (77) 0x47c2d8 ORR	X7, XZR, X5

      (77) 0x47c2dc TBZ	W22, #0, 47c308

      (77) 0x47c2e0 LDR	X7, [X12, X5,LSL #3]

      (77) 0x47c2e4 MOVI	D0, #0

      (77) 0x47c2e8 CMP	X7, X4

      (77) 0x47c2ec CCMP	X7, X8, #8, #1

      (77) 0x47c2f0 CCMP	X7, X9, #0, #10

      (77) 0x47c2f4 B.LT	47c304

      (77) 0x47c2f8 LDR	D0, [X6, X5,LSL #3]

      (77) 0x47c2fc FABS	D0, D0

      (77) 0x47c300 STR	D0, [X10, X4,LSL #3]

      (77) 0x47c304 ADD	X7, X5, #1

      (77) 0x47c308 ADD	X5, X5, #1

      (77) 0x47c30c CMP	X1, X5

      (77) 0x47c310 B.NE	47c400

      (77) 0x47c314 CBZ	X13, 47c2a0

      (77) 0x47c318 LDR	X23, [X14, X4,LSL #3]

      (77) 0x47c31c LDR	X5, [X14, X3,LSL #3]

      (77) 0x47c320 SUBS	X6, X5, X23

      (77) 0x47c324 B.LE	47c2a0

      (77) 0x47c328 CMP	X25, #8

      (77) 0x47c32c MOVZ	W7, #8

      (77) 0x47c330 CSEL	X7, X25, X7, #8

      (77) 0x47c334 CMP	X6, X7

      (77) 0x47c338 B.CC	47c4a0

      (77) 0x47c33c UBFM	X7, X15, #61, #60

      (77) 0x47c340 ADD	X30, X16, X5,LSL #3

      (77) 0x47c344 ADD	X24, X16, X23,LSL #3

      (77) 0x47c348 ADD	X22, X17, X7

      (77) 0x47c34c ADD	X7, X18, X7

      (77) 0x47c350 CMP	X22, X30

      (77) 0x47c354 CCMP	X24, X7, #2, #3

      (77) 0x47c358 B.CC	47c4a0

      (77) 0x47c35c UDIV	X7, X6, X25

      (77) 0x47c360 UBFM	X24, X23, #61, #60

      (77) 0x47c364 ORR	X30, XZR, XZR

      (77) 0x47c368 MADD	X22, X7, X25, XZR

      (77) 0x47c36c SUB	X7, X6, X22

      (77) 0x47c370 ADD	X6, X23, X22

      (77) 0x47c374 ADD	X23, X16, X24

      (77) 0x47c378 ADDVL	X24, X24, #1

      (77) 0x47c37c ADD	X24, X16, X24

        (80) 0x47c380 LD1D	{Z1.D}, P0/Z, [X23, X30,LSL #3]

        (80) 0x47c384 LD1D	{Z2.D}, P0/Z, [X24, X30,LSL #3]

        (80) 0x47c388 ADD	X30, X30, X25

        (80) 0x47c38c CMP	X22, X30

        (80) 0x47c390 FABS	Z1.D, P0/M, Z1.D

        (80) 0x47c394 FABS	Z2.D, P0/M, Z2.D

        (80) 0x47c398 FADDA	D0, P0, D0, Z1.D

        (80) 0x47c39c FADDA	D0, P0, D0, Z2.D

        (80) 0x47c3a0 B.NE	47c380

      (77) 0x47c3a4 STR	D0, [X10, X4,LSL #3]

      (77) 0x47c3a8 CBZ	X7, 47c2a0

      (77) 0x47c3ac SUB	W7, W5, W6

      (77) 0x47c3b0 ANDS	X22, X7, #4160

      (77) 0x47c3b4 B.EQ	47c4b0

      (77) 0x47c3b8 ORR	X7, XZR, X6

      (77) 0x47c3bc HINT	#0

        (78) 0x47c3c0 LDR	D1, [X16, X7,LSL #3]

        (78) 0x47c3c4 ADD	X7, X7, #1

        (78) 0x47c3c8 SUBS	X22, X22, #1

        (78) 0x47c3cc FABS	D1, D1

        (78) 0x47c3d0 FADD	D0, D0, D1

        (78) 0x47c3d4 STR	D0, [X10, X4,LSL #3]

        (78) 0x47c3d8 B.NE	47c3c0

      (77) 0x47c3dc ORN	X6, XZR, X6

      (77) 0x47c3e0 ADD	X6, X5, X6

      (77) 0x47c3e4 CMP	X6, #3

      (77) 0x47c3e8 B.CC	47c2a0

      (77) 0x47c3ec B	47c4c4

0x47c3f0 HINT	#0

0x47c3f4 HINT	#0

0x47c3f8 HINT	#0

0x47c3fc HINT	#0

      (77) 0x47c400 SUB	X5, X1, X7

      (77) 0x47c404 UBFM	X7, X7, #61, #60

      (77) 0x47c408 ADD	X6, X6, X7

      (77) 0x47c40c ADD	X7, X0, X7

      (77) 0x47c410 ADD	X6, X6, #8

      (77) 0x47c414 B	47c430

0x47c418 HINT	#0

0x47c41c HINT	#0

        (81) 0x47c420 SUBS	X5, X5, #2

        (81) 0x47c424 ADD	X6, X6, #16

        (81) 0x47c428 ADD	X7, X7, #16

        (81) 0x47c42c B.EQ	47c314

        (81) 0x47c430 LDUR	X22, [X7, #504]

        (81) 0x47c434 CMP	X22, X4

        (81) 0x47c438 CCMP	X22, X8, #8, #1

        (81) 0x47c43c CCMP	X22, X9, #0, #10

        (81) 0x47c440 B.LT	47c46c

        (81) 0x47c444 LDUR	D1, [X6, #504]

        (81) 0x47c448 FABS	D1, D1

        (81) 0x47c44c FADD	D0, D0, D1

        (81) 0x47c450 STR	D0, [X10, X4,LSL #3]

        (81) 0x47c454 LDR	X22, [X7]

        (81) 0x47c458 CMP	X22, X4

        (81) 0x47c45c CCMP	X22, X8, #8, #1

        (81) 0x47c460 CCMP	X22, X9, #0, #10

        (81) 0x47c464 B.LT	47c420

        (81) 0x47c468 B	47c480

        (81) 0x47c46c LDR	X22, [X7]

        (81) 0x47c470 CMP	X22, X4

        (81) 0x47c474 CCMP	X22, X8, #8, #1

        (81) 0x47c478 CCMP	X22, X9, #0, #10

        (81) 0x47c47c B.LT	47c420

        (81) 0x47c480 LDR	D1, [X6]

        (81) 0x47c484 FABS	D1, D1

        (81) 0x47c488 FADD	D0, D0, D1

        (81) 0x47c48c STR	D0, [X10, X4,LSL #3]

        (81) 0x47c490 B	47c420

0x47c494 HINT	#0

0x47c498 HINT	#0

0x47c49c HINT	#0

      (77) 0x47c4a0 ORR	X6, XZR, X23

      (77) 0x47c4a4 SUB	W7, W5, W6

      (77) 0x47c4a8 ANDS	X22, X7, #4160

      (77) 0x47c4ac B.NE	47c3b8

      (77) 0x47c4b0 ORR	X7, XZR, X6

      (77) 0x47c4b4 ORN	X6, XZR, X6

      (77) 0x47c4b8 ADD	X6, X5, X6

      (77) 0x47c4bc CMP	X6, #3

      (77) 0x47c4c0 B.CC	47c2a0

      (77) 0x47c4c4 SUB	X5, X5, X7

      (77) 0x47c4c8 ADD	X6, X2, X7,LSL #3

        (79) 0x47c4cc LDUR	D1, [X6, #496]

        (79) 0x47c4d0 SUBS	X5, X5, #4

        (79) 0x47c4d4 FABS	D1, D1

        (79) 0x47c4d8 FADD	D0, D0, D1

        (79) 0x47c4dc STR	D0, [X10, X4,LSL #3]

        (79) 0x47c4e0 LDUR	D1, [X6, #504]

        (79) 0x47c4e4 FABS	D1, D1

        (79) 0x47c4e8 FADD	D0, D0, D1

        (79) 0x47c4ec STR	D0, [X10, X4,LSL #3]

        (79) 0x47c4f0 LDR	D1, [X6]

        (79) 0x47c4f4 FABS	D1, D1

        (79) 0x47c4f8 FADD	D0, D0, D1

        (79) 0x47c4fc STR	D0, [X10, X4,LSL #3]

        (79) 0x47c500 LDR	D1, [X6, #8]

        (79) 0x47c504 ADD	X6, X6, #32

        (79) 0x47c508 FABS	D1, D1

        (79) 0x47c50c FADD	D0, D0, D1

        (79) 0x47c510 STR	D0, [X10, X4,LSL #3]

        (79) 0x47c514 B.NE	47c4cc

      (77) 0x47c518 B	47c2a0

    (65) 0x47c51c LDR	X15, [X19]

    (65) 0x47c520 LDR	X16, [X26]

    (65) 0x47c524 UBFM	X17, X8, #61, #60

    (65) 0x47c528 ORR	X3, XZR, X8

    (65) 0x47c52c LDR	X1, [X11, X17]

    (65) 0x47c530 ADD	X17, X10, X17

    (65) 0x47c534 ADD	X18, X17, #8

    (65) 0x47c538 ADD	X0, X15, #16

    (65) 0x47c53c ADD	X2, X16, #16

    (65) 0x47c540 B	47c550

      (68) 0x47c544 ADD	X14, X14, #1

      (68) 0x47c548 CMP	X3, X9

      (68) 0x47c54c B.EQ	47c7a0

      (68) 0x47c550 ORR	X4, XZR, X3

      (68) 0x47c554 STR	XZR, [X10, X3,LSL #3]

      (68) 0x47c558 ADD	X3, X3, #1

      (68) 0x47c55c ORR	X5, XZR, X1

      (68) 0x47c560 MOVI	D0, #0

      (68) 0x47c564 LDR	X1, [X11, X3,LSL #3]

      (68) 0x47c568 CMP	X1, X5

      (68) 0x47c56c B.LE	47c62c

      (68) 0x47c570 SUB	W6, W1, W5

      (68) 0x47c574 MOVI	D0, #0

      (68) 0x47c578 ANDS	X7, X6, #4160

      (68) 0x47c57c B.EQ	47c5b4

      (68) 0x47c580 ORR	X6, XZR, X5

        (73) 0x47c584 LDR	D1, [X15, X6,LSL #3]

        (73) 0x47c588 ADD	X6, X6, #1

        (73) 0x47c58c SUBS	X7, X7, #1

        (73) 0x47c590 FABS	D1, D1

        (73) 0x47c594 FADD	D0, D0, D1

        (73) 0x47c598 STR	D0, [X10, X4,LSL #3]

        (73) 0x47c59c B.NE	47c584

      (68) 0x47c5a0 ORN	X5, XZR, X5

      (68) 0x47c5a4 ADD	X5, X1, X5

      (68) 0x47c5a8 CMP	X5, #3

      (68) 0x47c5ac B.CS	47c5c8

      (68) 0x47c5b0 B	47c62c

      (68) 0x47c5b4 ORR	X6, XZR, X5

      (68) 0x47c5b8 ORN	X5, XZR, X5

      (68) 0x47c5bc ADD	X5, X1, X5

      (68) 0x47c5c0 CMP	X5, #3

      (68) 0x47c5c4 B.CC	47c62c

      (68) 0x47c5c8 SUB	X5, X1, X6

      (68) 0x47c5cc ADD	X6, X0, X6,LSL #3

      (68) 0x47c5d0 HINT	#0

      (68) 0x47c5d4 HINT	#0

      (68) 0x47c5d8 HINT	#0

      (68) 0x47c5dc HINT	#0

        (72) 0x47c5e0 LDUR	D1, [X6, #496]

        (72) 0x47c5e4 SUBS	X5, X5, #4

        (72) 0x47c5e8 FABS	D1, D1

        (72) 0x47c5ec FADD	D0, D0, D1

        (72) 0x47c5f0 STR	D0, [X10, X4,LSL #3]

        (72) 0x47c5f4 LDUR	D1, [X6, #504]

        (72) 0x47c5f8 FABS	D1, D1

        (72) 0x47c5fc FADD	D0, D0, D1

        (72) 0x47c600 STR	D0, [X10, X4,LSL #3]

        (72) 0x47c604 LDR	D1, [X6]

        (72) 0x47c608 FABS	D1, D1

        (72) 0x47c60c FADD	D0, D0, D1

        (72) 0x47c610 STR	D0, [X10, X4,LSL #3]

        (72) 0x47c614 LDR	D1, [X6, #8]

        (72) 0x47c618 ADD	X6, X6, #32

        (72) 0x47c61c FABS	D1, D1

        (72) 0x47c620 FADD	D0, D0, D1

        (72) 0x47c624 STR	D0, [X10, X4,LSL #3]

        (72) 0x47c628 B.NE	47c5e0

      (68) 0x47c62c CBZ	X12, 47c544

      (68) 0x47c630 LDR	X23, [X13, X4,LSL #3]

      (68) 0x47c634 LDR	X5, [X13, X3,LSL #3]

      (68) 0x47c638 SUBS	X6, X5, X23

      (68) 0x47c63c B.LE	47c544

      (68) 0x47c640 CMP	X25, #8

      (68) 0x47c644 MOVZ	W7, #8

      (68) 0x47c648 CSEL	X7, X25, X7, #8

      (68) 0x47c64c CMP	X6, X7

      (68) 0x47c650 B.CC	47c720

      (68) 0x47c654 UBFM	X7, X14, #61, #60

      (68) 0x47c658 ADD	X30, X16, X5,LSL #3

      (68) 0x47c65c ADD	X24, X16, X23,LSL #3

      (68) 0x47c660 ADD	X22, X17, X7

      (68) 0x47c664 ADD	X7, X18, X7

      (68) 0x47c668 CMP	X22, X30

      (68) 0x47c66c CCMP	X24, X7, #2, #3

      (68) 0x47c670 B.CC	47c720

      (68) 0x47c674 UDIV	X7, X6, X25

      (68) 0x47c678 UBFM	X24, X23, #61, #60

      (68) 0x47c67c ORR	X30, XZR, XZR

      (68) 0x47c680 MADD	X22, X7, X25, XZR

      (68) 0x47c684 SUB	X7, X6, X22

      (68) 0x47c688 ADD	X6, X23, X22

      (68) 0x47c68c ADD	X23, X16, X24

      (68) 0x47c690 ADDVL	X24, X24, #1

      (68) 0x47c694 ADD	X24, X16, X24

      (68) 0x47c698 HINT	#0

      (68) 0x47c69c HINT	#0

        (71) 0x47c6a0 LD1D	{Z1.D}, P0/Z, [X23, X30,LSL #3]

        (71) 0x47c6a4 LD1D	{Z2.D}, P0/Z, [X24, X30,LSL #3]

        (71) 0x47c6a8 ADD	X30, X30, X25

        (71) 0x47c6ac CMP	X22, X30

        (71) 0x47c6b0 FABS	Z1.D, P0/M, Z1.D

        (71) 0x47c6b4 FABS	Z2.D, P0/M, Z2.D

        (71) 0x47c6b8 FADDA	D0, P0, D0, Z1.D

        (71) 0x47c6bc FADDA	D0, P0, D0, Z2.D

        (71) 0x47c6c0 B.NE	47c6a0

      (68) 0x47c6c4 STR	D0, [X10, X4,LSL #3]

      (68) 0x47c6c8 CBZ	X7, 47c544

      (68) 0x47c6cc SUB	W7, W5, W6

      (68) 0x47c6d0 ANDS	X22, X7, #4160

      (68) 0x47c6d4 B.EQ	47c730

      (68) 0x47c6d8 ORR	X7, XZR, X6

      (68) 0x47c6dc HINT	#0

        (69) 0x47c6e0 LDR	D1, [X16, X7,LSL #3]

        (69) 0x47c6e4 ADD	X7, X7, #1

        (69) 0x47c6e8 SUBS	X22, X22, #1

        (69) 0x47c6ec FABS	D1, D1

        (69) 0x47c6f0 FADD	D0, D0, D1

        (69) 0x47c6f4 STR	D0, [X10, X4,LSL #3]

        (69) 0x47c6f8 B.NE	47c6e0

      (68) 0x47c6fc ORN	X6, XZR, X6

      (68) 0x47c700 ADD	X6, X5, X6

      (68) 0x47c704 CMP	X6, #3

      (68) 0x47c708 B.CC	47c544

      (68) 0x47c70c B	47c744

0x47c710 HINT	#0

0x47c714 HINT	#0

0x47c718 HINT	#0

0x47c71c HINT	#0

      (68) 0x47c720 ORR	X6, XZR, X23

      (68) 0x47c724 SUB	W7, W5, W6

      (68) 0x47c728 ANDS	X22, X7, #4160

      (68) 0x47c72c B.NE	47c6d8

      (68) 0x47c730 ORR	X7, XZR, X6

      (68) 0x47c734 ORN	X6, XZR, X6

      (68) 0x47c738 ADD	X6, X5, X6

      (68) 0x47c73c CMP	X6, #3

      (68) 0x47c740 B.CC	47c544

      (68) 0x47c744 SUB	X5, X5, X7

      (68) 0x47c748 ADD	X6, X2, X7,LSL #3

        (70) 0x47c74c LDUR	D1, [X6, #496]

        (70) 0x47c750 SUBS	X5, X5, #4

        (70) 0x47c754 FABS	D1, D1

        (70) 0x47c758 FADD	D0, D0, D1

        (70) 0x47c75c STR	D0, [X10, X4,LSL #3]

        (70) 0x47c760 LDUR	D1, [X6, #504]

        (70) 0x47c764 FABS	D1, D1

        (70) 0x47c768 FADD	D0, D0, D1

        (70) 0x47c76c STR	D0, [X10, X4,LSL #3]

        (70) 0x47c770 LDR	D1, [X6]

        (70) 0x47c774 FABS	D1, D1

        (70) 0x47c778 FADD	D0, D0, D1

        (70) 0x47c77c STR	D0, [X10, X4,LSL #3]

        (70) 0x47c780 LDR	D1, [X6, #8]

        (70) 0x47c784 ADD	X6, X6, #32

        (70) 0x47c788 FABS	D1, D1

        (70) 0x47c78c FADD	D0, D0, D1

        (70) 0x47c790 STR	D0, [X10, X4,LSL #3]

        (70) 0x47c794 B.NE	47c74c

      (68) 0x47c798 B	47c544

0x47c79c HINT	#0

    (65) 0x47c7a0 SUBS	X10, X9, X8

    (65) 0x47c7a4 B.LE	47b81c

  (67) 0x47c7a8 LDR	X11, [SP, #80]

  (67) 0x47c7ac LDR	X12, [X19]

  (67) 0x47c7b0 ORR	X14, XZR, X8

  (67) 0x47c7b4 LDR	X13, [X11]

  (67) 0x47c7b8 LDR	X11, [SP, #72]

  (67) 0x47c7bc LDR	X11, [X11]

  (67) 0x47c7c0 TBZ	W10, #0, 47c7e4

  (67) 0x47c7c4 LDR	X14, [X13, X8,LSL #3]

  (67) 0x47c7c8 LDR	D0, [X12, X14,LSL #3]

  (67) 0x47c7cc FCMP	D0, #0

  (67) 0x47c7d0 B.PL	47c7e0

  (67) 0x47c7d4 LDR	D0, [X11, X8,LSL #3]

  (67) 0x47c7d8 FNEG	D0, D0

  (67) 0x47c7dc STR	D0, [X11, X8,LSL #3]

  (67) 0x47c7e0 ADD	X14, X8, #1

  (67) 0x47c7e4 ADD	X15, X8, #1

  (67) 0x47c7e8 CMP	X9, X15

  (67) 0x47c7ec B.NE	47c820

  (67) 0x47c7f0 ADD	X8, X11, X8,LSL #3

  (67) 0x47c7f4 HINT	#0

  (67) 0x47c7f8 HINT	#0

  (67) 0x47c7fc HINT	#0

    (97) 0x47c800 LDR	D0, [X8]

    (97) 0x47c804 FCMP	D0, #0

    (97) 0x47c808 B.EQ	47b800

    (97) 0x47c80c SUBS	X10, X10, #1

    (97) 0x47c810 ADD	X8, X8, #8

    (97) 0x47c814 B.NE	47c800

  (67) 0x47c818 B	47b81c

0x47c81c HINT	#0

(66) 0x47c820 SUB	X9, X9, X14

(66) 0x47c824 UBFM	X14, X14, #61, #60

(66) 0x47c828 ADD	X13, X13, X14

(66) 0x47c82c ADD	X14, X11, X14

(66) 0x47c830 ADD	X13, X13, #8

(66) 0x47c834 ADD	X14, X14, #8

(66) 0x47c838 B	47c850

0x47c83c HINT	#0

(66) 0x47c840 SUBS	X9, X9, #2

(66) 0x47c844 ADD	X13, X13, #16

(66) 0x47c848 ADD	X14, X14, #16

(66) 0x47c84c B.EQ	47c7f0

(66) 0x47c850 LDUR	X15, [X13, #504]

(66) 0x47c854 LDR	D0, [X12, X15,LSL #3]

(66) 0x47c858 FCMP	D0, #0

(66) 0x47c85c B.PL	47c880

(66) 0x47c860 LDUR	D0, [X14, #504]

(66) 0x47c864 FNEG	D0, D0

(66) 0x47c868 STUR	D0, [X14, #504]

(66) 0x47c86c LDR	X15, [X13]

(66) 0x47c870 LDR	D0, [X12, X15,LSL #3]

(66) 0x47c874 FCMP	D0, #0

(66) 0x47c878 B.PL	47c840

(66) 0x47c87c B	47c890

(66) 0x47c880 LDR	X15, [X13]

(66) 0x47c884 LDR	D0, [X12, X15,LSL #3]

(66) 0x47c888 FCMP	D0, #0

(66) 0x47c88c B.PL	47c840

(66) 0x47c890 LDR	D0, [X14]

(66) 0x47c894 FNEG	D0, D0

(66) 0x47c898 STR	D0, [X14]

(66) 0x47c89c B	47c840

0x47c8a0 LDR	W20, [SP, #20]

0x47c8a4 ORR	W1, WZR, W20

0x47c8a8 ADRP	X0,

0x47c8ac ADD	X0, X0, #808

0x47c8b0 BL	40f410

0x47c8b4 LDP	D9, D8, [SP, #144]

0x47c8b8 LDP	X20, X19, [SP, #240]

0x47c8bc LDP	X22, X21, [SP, #224]

0x47c8c0 LDP	X24, X23, [SP, #208]

0x47c8c4 LDP	X26, X25, [SP, #192]

0x47c8c8 LDP	X28, X27, [SP, #176]

0x47c8cc LDP	X29, X30, [SP, #160]

0x47c8d0 ADD	SP, SP, #256

0x47c8d4 RET

0x47c8d8 HINT	#0

0x47c8dc HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	ams.c:3363-3540
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3363-3409,3416-3451,3458-3481,3493-3507,3517-3540.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.00 to 1.00 cycles (13.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 29% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 13.00 to 12.75 cycles (1.02x speedup).

Details

11% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 13.00 to 1.00 cycles (13.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 200 bytes. The binary function is storing 248 bytes.

General properties

nb instructions	114
loop length	456
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	6.50	6.50	6.50	6.50	0.50	0.50	0.50	0.50	13.00	13.00	13.00	10.50	10.50
cycles	3.00	3.00	6.50	6.50	6.50	6.50	0.50	0.50	0.50	0.50	13.00	13.00	13.00	10.50	10.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.75
Overall L1	13.00

Vectorization ratios

all	11%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.00 cycles. At this rate:

16% of peak load performance is reached (15.38 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
39% of peak store performance is reached (19.08 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 47b720

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP D9, D8, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP X29, X30, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X5, X7, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X6, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUBS X19, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STP X3, X4, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X2, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.LT 47c8b4 <.omp_outlined.+0x1194>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W20, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4ee768>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #784	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #44	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, XZR, [X29, #992]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR WZR, [X29, #468]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X4, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X5, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f550 <@plt_start@+0x160>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X28, [X29, #992]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X8, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X27, X8, X19, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X28, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STUR X27, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.GT 47c8a4 <.omp_outlined.+0x1184>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X19, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W20, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CNTW X25, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
FMOV D8, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ORR X20, XZR, #3840	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVK X20, #16373	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X26, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 47b828 <.omp_outlined.+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDR W20, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4ee8a8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #808	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f410 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP D9, D8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X20, X19, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Source file and lines	ams.c:3363-3540
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3363-3409,3416-3451,3458-3481,3493-3507,3517-3540.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

11% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 13.00 to 1.00 cycles (13.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 200 bytes. The binary function is storing 248 bytes.

General properties

nb instructions	114
loop length	456
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	6.50	6.50	6.50	6.50	0.50	0.50	0.50	0.50	13.00	13.00	13.00	10.50	10.50
cycles	3.00	3.00	6.50	6.50	6.50	6.50	0.50	0.50	0.50	0.50	13.00	13.00	13.00	10.50	10.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.75
Overall L1	13.00

Vectorization ratios

all	11%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.00 cycles. At this rate:

16% of peak load performance is reached (15.38 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
39% of peak store performance is reached (19.08 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 47b720

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP D9, D8, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP X29, X30, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X5, X7, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X6, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUBS X19, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STP X3, X4, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X2, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.LT 47c8b4 <.omp_outlined.+0x1194>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W20, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4ee768>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #784	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #44	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, XZR, [X29, #992]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR WZR, [X29, #468]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X4, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X5, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f550 <@plt_start@+0x160>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X28, [X29, #992]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X8, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X27, X8, X19, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X28, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STUR X27, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.GT 47c8a4 <.omp_outlined.+0x1184>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X19, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W20, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CNTW X25, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
FMOV D8, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ORR X20, XZR, #3840	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVK X20, #16373	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X26, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 47b828 <.omp_outlined.+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDR W20, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4ee8a8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #808	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f410 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP D9, D8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X20, X19, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined.#0x47b720–	0.23	0.09
▼Loop 66 - ams.c:3365-3540 - exec–	0.04	0.01
▼Loop 67 - ams.c:3365-3540 - exec–	0	0
▼Loop 65 - ams.c:3365-3532 - exec–	0	0
▼Loop 68 - ams.c:3382-3394 - exec–	0.04	0.01
○Loop 72 - ams.c:3388-3389 - exec	0.12	0.04
○Loop 73 - ams.c:3388-3389 - exec	0.02	0.01
○Loop 69 - ams.c:3393-3394 - exec	0	0
○Loop 71 - ams.c:3394-3394 - exec	0	0
○Loop 70 - ams.c:3393-3394 - exec	0	0
▼Loop 85 - ams.c:3470-3527 - exec–	0	0
○Loop 90 - ams.c:3501-3507 - exec	0	0
○Loop 86 - ams.c:3493-3494 - exec	0	0
○Loop 88 - ams.c:3476-3481 - exec	0	0
○Loop 89 - ams.c:3519-3521 - exec	0	0
○Loop 87 - ams.c:3493-3494 - exec	0	0
▼Loop 82 - ams.c:3416-3451 - exec–	0	0
○Loop 84 - ams.c:3439-3444 - exec	0	0
○Loop 83 - ams.c:3449-3451 - exec	0	0
▼Loop 91 - ams.c:3458-3465 - exec–	0	0
○Loop 94 - ams.c:3465-3465 - exec	0	0
○Loop 96 - ams.c:3461-3462 - exec	0	0
○Loop 93 - ams.c:3464-3465 - exec	0	0
○Loop 95 - ams.c:3461-3462 - exec	0	0
○Loop 92 - ams.c:3464-3465 - exec	0	0
▼Loop 74 - ams.c:3382-3409 - exec–	0	0
○Loop 76 - ams.c:3401-3403 - exec	0	0
○Loop 75 - ams.c:3407-3409 - exec	0	0
▼Loop 77 - ams.c:3416-3432 - exec–	0	0
○Loop 78 - ams.c:3431-3432 - exec	0	0
○Loop 79 - ams.c:3431-3432 - exec	0	0
○Loop 81 - ams.c:3422-3426 - exec	0	0
○Loop 80 - ams.c:3432-3432 - exec	0	0
○Loop 97 - ams.c:3536-3538 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code