OV - exec - Function .omp_outlined.#0x43b900

	Function: .omp_outlined.#0x43b900	Module: exec	Source: par_lr_interp.c:1196-1757 [...]	Coverage: 0.22%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c: 1196 - 1757

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1196: #pragma omp parallel private(i,my_thread_num,num_threads,start,stop,coarse_counter,jj_counter,jj_counter_offd, P_marker, P_marker_offd,jj,kk,i1,k1,loc_col,jj_begin_row,jj_begin_row_offd,jj_end_row,jj_end_row_offd,diagonal,sum,sgn,jj1,i2,distribute,strong_f_marker)

[...]

1221:        if (n_fine)

1222:        {

1223:            P_marker = hypre_CTAlloc(HYPRE_Int, n_fine);

1224:            for (i = 0; i < n_fine; i++)

1225:            {  P_marker[i] = -1; }

1226:        }

1227:        if (full_off_procNodes)

1228:        {

1229:          P_marker_offd = hypre_CTAlloc(HYPRE_Int, full_off_procNodes);

1230:          for (i = 0; i < full_off_procNodes; i++)

1231:          {  P_marker_offd[i] = -1;}

1232:        }

1233:

1234:        /* this thread's row range */

1235:        my_thread_num = hypre_GetThreadNum();

1236:        num_threads = hypre_NumActiveThreads();

1237:        start = (n_fine/num_threads)*my_thread_num;

1238:        if (my_thread_num == num_threads-1)

[...]

1244:        for (i = start; i < stop; i++)

1245:        {

1246:          P_diag_i[i] = jj_counter;

1247:          if (num_procs > 1)

1248:            P_offd_i[i] = jj_counter_offd;

1249:

1250:          if (CF_marker[i] >= 0)

1251:          {

1252:            jj_counter++;

1253:            fine_to_coarse[i] = coarse_counter;

1254:            coarse_counter++;

[...]

1262:          else if (CF_marker[i] != -3)

1263:          {

1264:            for (jj = S_diag_i[i]; jj < S_diag_i[i+1]; jj++)

1265:            {

1266:              i1 = S_diag_j[jj];

1267:              if (CF_marker[i1] >= 0)

1268:              { /* i1 is a C point */

1269:                if (P_marker[i1] < P_diag_i[i])

1270:                {

1271:                  P_marker[i1] = jj_counter;

1272:                  jj_counter++;

1273:                }

1274:              }

1275:              else if (CF_marker[i1] != -3)

1276:              { /* i1 is a F point, loop through it's strong neighbors */

1277:                for (kk = S_diag_i[i1]; kk < S_diag_i[i1+1]; kk++)

1278:                {

1279:                  k1 = S_diag_j[kk];

1280:                  if (CF_marker[k1] >= 0)

1281:                  {

1282:                    if(P_marker[k1] < P_diag_i[i])

1283:                    {

1284:                      P_marker[k1] = jj_counter;

1285:                      jj_counter++;

1286:                    }

1287:                  }

1288:                }

1289:                if(num_procs > 1)

1290:                {

1291:                  for (kk = S_offd_i[i1]; kk < S_offd_i[i1+1]; kk++)

1292:                  {

1293:                    if(col_offd_S_to_A)

1294:                      k1 = col_offd_S_to_A[S_offd_j[kk]];

1295:                    else

1296:                      k1 = S_offd_j[kk];

1297:                    if (CF_marker_offd[k1] >= 0)

1298:                    {

1299:                      if(P_marker_offd[k1] < P_offd_i[i])

1300:                      {

1301:                        tmp_CF_marker_offd[k1] = 1;

1302:                        P_marker_offd[k1] = jj_counter_offd;

1303:                        jj_counter_offd++;

[...]

1311:            if (num_procs > 1)

1312:            {

1313:              for (jj = S_offd_i[i]; jj < S_offd_i[i+1]; jj++)

1314:              {

1315:                i1 = S_offd_j[jj];

1316:                if(col_offd_S_to_A)

1317:                  i1 = col_offd_S_to_A[i1];

1318:                if (CF_marker_offd[i1] >= 0)

1319:                {

1320:                  if(P_marker_offd[i1] < P_offd_i[i])

1321:                  {

1322:                    tmp_CF_marker_offd[i1] = 1;

1323:                    P_marker_offd[i1] = jj_counter_offd;

1324:                    jj_counter_offd++;

1325:                  }

1326:                }

1327:                else if (CF_marker_offd[i1] != -3)

1328:                { /* F point; look at neighbors of i1. Sop contains global col

1329:                   * numbers and entries that could be in S_diag or S_offd or

1330:                   * neither. */

1331:                  for(kk = Sop_i[i1]; kk < Sop_i[i1+1]; kk++)

1332:                  {

1333:                    k1 = Sop_j[kk];

1334:                    if(k1 >= col_1 && k1 < col_n)

1335:                    { /* In S_diag */

1336:                      loc_col = k1-col_1;

1337:                      if(P_marker[loc_col] < P_diag_i[i])

1338:                      {

1339:                        P_marker[loc_col] = jj_counter;

1340:                        jj_counter++;

1341:                      }

1342:                    }

1343:                    else

1344:                    {

1345:                      loc_col = -k1 - 1;

1346:                      if(P_marker_offd[loc_col] < P_offd_i[i])

1347:                      {

1348:                        P_marker_offd[loc_col] = jj_counter_offd;

1349:                        tmp_CF_marker_offd[loc_col] = 1;

1350:                        jj_counter_offd++;

[...]

1363: #pragma omp barrier

1364: #endif

1365:        P_diag_i[stop] = jj_counter;

1366:        P_offd_i[stop] = jj_counter_offd;

1367:        fine_to_coarse_offset[my_thread_num] = coarse_counter;

1368:        diag_offset[my_thread_num] = jj_counter;

1369:        offd_offset[my_thread_num] = jj_counter_offd;

1370:

1371:        /* Stitch P_diag_i, P_offd_i and fine_to_coarse together */

1372: #ifdef HYPRE_USING_OPENMP

1373: #pragma omp barrier

1374: #endif

1375:        if(my_thread_num == 0)

1376:        {

1377:          /* Calculate the offset for P_diag_i and P_offd_i for each thread */

1378:          for (i = 1; i < num_threads; i++)

1379:          {

1380:            diag_offset[i] = diag_offset[i-1] + diag_offset[i];

1381:            fine_to_coarse_offset[i] = fine_to_coarse_offset[i-1] + fine_to_coarse_offset[i];

1382:            offd_offset[i] = offd_offset[i-1] + offd_offset[i];

1383:          }

1384:        }

1385: #ifdef HYPRE_USING_OPENMP

1386: #pragma omp barrier

1387: #endif

1388:

1389:        if(my_thread_num > 0)

1390:        {

1391:          /* update row pointer array with offset,

1392:           * making sure to update the row stop index */

1393:          for (i = start+1; i <= stop; i++)

1394:          {

1395:             P_diag_i[i] += diag_offset[my_thread_num-1];

1396:             P_offd_i[i] += offd_offset[my_thread_num-1];

1397:          }

1398:          /* update fine_to_coarse by offsetting with the offset

1399:           * from the preceding thread */

1400:          for (i = start; i < stop; i++)

1401:          {

1402:            if(fine_to_coarse[i] >= 0)

1403:            { fine_to_coarse[i] += fine_to_coarse_offset[my_thread_num-1]; }

1404:          }

1405:        }

1406: #ifdef HYPRE_USING_OPENMP

1407: #pragma omp barrier

1408: #endif

1409:

1410:        if(my_thread_num == 0)

1411:        {

1412:          if (debug_flag==4)

1413:          {

1414:             wall_time = time_getWallclockSeconds() - wall_time;

1415:             hypre_printf("Proc = %d     determine structure    %f\n",

1416:                           my_id, wall_time);

1417:             fflush(NULL);

[...]

1423:          if (debug_flag== 4) wall_time = time_getWallclockSeconds();

1424:

1425:          P_diag_size =  P_diag_i[n_fine];

1426:          P_offd_size = P_offd_i[n_fine];

1427:

1428:          if (P_diag_size)

1429:          {

1430:             P_diag_j    = hypre_CTAlloc(HYPRE_Int, P_diag_size);

1431:             P_diag_data = hypre_CTAlloc(HYPRE_Real, P_diag_size);

1432:          }

1433:

1434:          if (P_offd_size)

1435:          {

1436:             P_offd_j    = hypre_CTAlloc(HYPRE_Int, P_offd_size);

1437:             P_offd_data = hypre_CTAlloc(HYPRE_Real, P_offd_size);

1438:          }

1439:        }

1440:

1441:        /* Fine to coarse mapping */

1442:        if(num_procs > 1   &&   my_thread_num == 0)

1443:        {

1444:          for (i = 0; i < n_fine; i++)

1445:            fine_to_coarse[i] += my_first_cpt;

1446:

1447:          hypre_alt_insert_new_nodes(comm_pkg, extend_comm_pkg, fine_to_coarse,

1448:                   full_off_procNodes,

1449:                   fine_to_coarse_offd);

1450:

1451:          for (i = 0; i < n_fine; i++)

1452:            fine_to_coarse[i] -= my_first_cpt;

1453:        }

1454:

1455:        for (i = 0; i < n_fine; i++)

1456:          P_marker[i] = -1;

1457:

1458:        for (i = 0; i < full_off_procNodes; i++)

1459:          P_marker_offd[i] = -1;

[...]

1467: #pragma omp barrier

1468: #endif

1469:        for (i = start; i < stop; i++)

1470:        {

1471:          jj_begin_row = P_diag_i[i];

[...]

1480:          if (CF_marker[i] >= 0)

1481:          {

1482:            P_diag_j[jj_counter]    = fine_to_coarse[i];

1483:            P_diag_data[jj_counter] = one;

[...]

1491:          else if (CF_marker[i] != -3)

1492:          {

1493:            strong_f_marker--;

1494:            for (jj = S_diag_i[i]; jj < S_diag_i[i+1]; jj++)

1495:            {

1496:              i1 = S_diag_j[jj];

[...]

1503:              if (CF_marker[i1] >= 0)

1504:              {

1505:                if (P_marker[i1] < jj_begin_row)

1506:                {

1507:                  P_marker[i1] = jj_counter;

1508:                  P_diag_j[jj_counter]    = fine_to_coarse[i1];

1509:                  P_diag_data[jj_counter] = zero;

1510:                  jj_counter++;

1511:                }

1512:              }

1513:              else  if (CF_marker[i1] != -3)

1514:              {

1515:                P_marker[i1] = strong_f_marker;

1516:                for (kk = S_diag_i[i1]; kk < S_diag_i[i1+1]; kk++)

1517:                {

1518:                  k1 = S_diag_j[kk];

1519:                  if (CF_marker[k1] >= 0)

1520:                  {

1521:                    if(P_marker[k1] < jj_begin_row)

1522:                    {

1523:                      P_marker[k1] = jj_counter;

1524:                      P_diag_j[jj_counter] = fine_to_coarse[k1];

1525:                      P_diag_data[jj_counter] = zero;

1526:                      jj_counter++;

1527:                    }

1528:                  }

1529:                }

1530:                if(num_procs > 1)

1531:                {

1532:                  for (kk = S_offd_i[i1]; kk < S_offd_i[i1+1]; kk++)

1533:                  {

1534:                    if(col_offd_S_to_A)

1535:                     k1 = col_offd_S_to_A[S_offd_j[kk]];

1536:                    else

1537:                     k1 = S_offd_j[kk];

1538:                    if(CF_marker_offd[k1] >= 0)

1539:                    {

1540:                      if(P_marker_offd[k1] < jj_begin_row_offd)

1541:                      {

1542:                        P_marker_offd[k1] = jj_counter_offd;

1543:                        P_offd_j[jj_counter_offd] = k1;

1544:                        P_offd_data[jj_counter_offd] = zero;

1545:                        jj_counter_offd++;

[...]

1553:            if ( num_procs > 1)

1554:            {

1555:              for (jj=S_offd_i[i]; jj < S_offd_i[i+1]; jj++)

1556:              {

1557:                i1 = S_offd_j[jj];

1558:                if(col_offd_S_to_A)

1559:                  i1 = col_offd_S_to_A[i1];

1560:                if ( CF_marker_offd[i1] >= 0)

1561:                {

1562:                  if(P_marker_offd[i1] < jj_begin_row_offd)

1563:                  {

1564:                    P_marker_offd[i1] = jj_counter_offd;

1565:                    P_offd_j[jj_counter_offd] = i1;

1566:                    P_offd_data[jj_counter_offd] = zero;

1567:                    jj_counter_offd++;

1568:                  }

1569:                }

1570:                else if (CF_marker_offd[i1] != -3)

1571:                {

1572:                  P_marker_offd[i1] = strong_f_marker;

1573:                  for(kk = Sop_i[i1]; kk < Sop_i[i1+1]; kk++)

1574:                  {

1575:                    k1 = Sop_j[kk];

1576:                    /* Find local col number */

1577:                    if(k1 >= col_1 && k1 < col_n)

1578:                    {

1579:                      loc_col = k1-col_1;

1580:                      if(P_marker[loc_col] < jj_begin_row)

1581:                      {

1582:                        P_marker[loc_col] = jj_counter;

1583:                        P_diag_j[jj_counter] = fine_to_coarse[loc_col];

1584:                        P_diag_data[jj_counter] = zero;

1585:                        jj_counter++;

1586:                      }

1587:                    }

1588:                    else

1589:                    {

1590:                      loc_col = -k1 - 1;

1591:                      if(P_marker_offd[loc_col] < jj_begin_row_offd)

1592:                      {

1593:                        P_marker_offd[loc_col] = jj_counter_offd;

1594:                        P_offd_j[jj_counter_offd]=loc_col;

1595:                        P_offd_data[jj_counter_offd] = zero;

1596:                        jj_counter_offd++;

[...]

1607:            diagonal = A_diag_data[A_diag_i[i]];

1608:

1609:            for (jj = A_diag_i[i]+1; jj < A_diag_i[i+1]; jj++)

1610:            { /* i1 is a c-point and strongly influences i, accumulate

1611:               * a_(i,i1) into interpolation weight */

1612:              i1 = A_diag_j[jj];

1613:              if (P_marker[i1] >= jj_begin_row)

1614:              {

1615:                P_diag_data[P_marker[i1]] += A_diag_data[jj];

1616:              }

1617:              else if(P_marker[i1] == strong_f_marker)

1618:              {

1619:                sum = zero;

1620:                sgn = 1;

1621:                if(A_diag_data[A_diag_i[i1]] < 0) sgn = -1;

1622:                /* Loop over row of A for point i1 and calculate the sum

1623:                 * of the connections to c-points that strongly influence i. */

1624:                for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++)

1625:                {

1626:                  i2 = A_diag_j[jj1];

1627:                  if((P_marker[i2] >= jj_begin_row || i2 == i) && (sgn*A_diag_data[jj1]) < 0)

1628:                    sum += A_diag_data[jj1];

1629:                }

1630:                if(num_procs > 1)

1631:                {

1632:                  for(jj1 = A_offd_i[i1]; jj1< A_offd_i[i1+1]; jj1++)

1633:                  {

1634:                    i2 = A_offd_j[jj1];

1635:                    if(P_marker_offd[i2] >= jj_begin_row_offd &&

1636:                       (sgn*A_offd_data[jj1]) < 0)

1637:                       sum += A_offd_data[jj1];

1638:                  }

1639:                }

1640:                if(sum != 0)

1641:                {

1642:                  distribute = A_diag_data[jj]/sum;

1643:                  /* Loop over row of A for point i1 and do the distribution */

1644:                  for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++)

1645:                  {

1646:                    i2 = A_diag_j[jj1];

1647:                    if(P_marker[i2] >= jj_begin_row && (sgn*A_diag_data[jj1]) < 0)

1648:                       P_diag_data[P_marker[i2]] +=

1649:                       distribute*A_diag_data[jj1];

1650:                        if(i2 == i && (sgn*A_diag_data[jj1]) < 0)

1651:                          diagonal += distribute*A_diag_data[jj1];

1652:                  }

1653:                  if(num_procs > 1)

1654:                  {

1655:                    for(jj1 = A_offd_i[i1]; jj1 < A_offd_i[i1+1]; jj1++)

1656:                    {

1657:                      i2 = A_offd_j[jj1];

1658:                      if(P_marker_offd[i2] >= jj_begin_row_offd &&

1659:                                 (sgn*A_offd_data[jj1]) < 0)

1660:                        P_offd_data[P_marker_offd[i2]] +=

[...]

1667:                  diagonal += A_diag_data[jj];

1668:                }

1669:              }

1670:              /* neighbor i1 weakly influences i, accumulate a_(i,i1) into

1671:               * diagonal */

1672:              else if (CF_marker[i1] != -3)

1673:              {

1674:                if(num_functions == 1 || dof_func[i] == dof_func[i1])

1675:                  diagonal += A_diag_data[jj];

1676:              }

1677:            }

1678:            if(num_procs > 1)

1679:            {

1680:              for(jj = A_offd_i[i]; jj < A_offd_i[i+1]; jj++)

1681:              {

1682:                i1 = A_offd_j[jj];

1683:                if(P_marker_offd[i1] >= jj_begin_row_offd)

1684:                  P_offd_data[P_marker_offd[i1]] += A_offd_data[jj];

1685:                else if(P_marker_offd[i1] == strong_f_marker)

1686:                {

1687:                  sum = zero;

1688:                  for(jj1 = A_ext_i[i1]; jj1 < A_ext_i[i1+1]; jj1++)

1689:                  {

1690:                    k1 = A_ext_j[jj1];

1691:                    if(k1 >= col_1 && k1 < col_n)

1692:                    { /* diag */

1693:                      loc_col = k1 - col_1;

1694:                      if(P_marker[loc_col] >= jj_begin_row || loc_col == i)

1695:                        sum += A_ext_data[jj1];

1696:                    }

1697:                    else

1698:                    {

1699:                      loc_col = -k1 - 1;

1700:                      if(P_marker_offd[loc_col] >= jj_begin_row_offd)

1701:                        sum += A_ext_data[jj1];

1702:                    }

1703:                  }

1704:                  if(sum != 0)

1705:                  {

1706:                    distribute = A_offd_data[jj] / sum;

1707:                    for(jj1 = A_ext_i[i1]; jj1 < A_ext_i[i1+1]; jj1++)

1708:                    {

1709:                      k1 = A_ext_j[jj1];

1710:                      if(k1 >= col_1 && k1 < col_n)

1711:                      { /* diag */

1712:                        loc_col = k1 - col_1;

1713:                        if(P_marker[loc_col] >= jj_begin_row)

1714:                          P_diag_data[P_marker[loc_col]] += distribute*

1715:                           A_ext_data[jj1];

1716:                                if(loc_col == i)

1717:                                  diagonal += distribute*A_ext_data[jj1];

1718:                      }

1719:                      else

1720:                      {

1721:                        loc_col = -k1 - 1;

1722:                        if(P_marker_offd[loc_col] >= jj_begin_row_offd)

1723:                          P_offd_data[P_marker_offd[loc_col]] += distribute*

1724:                            A_ext_data[jj1];

[...]

1730:                    diagonal += A_offd_data[jj];

1731:                  }

1732:                }

1733:                else if (CF_marker_offd[i1] != -3)

1734:                {

1735:                  if(num_functions == 1 || dof_func[i] == dof_func_offd[i1])

1736:                    diagonal += A_offd_data[jj];

1737:                }

1738:              }

1739:            }

1740:            if (diagonal)

1741:            {

1742:              for(jj = jj_begin_row; jj < jj_end_row; jj++)

1743:                 P_diag_data[jj] /= -diagonal;

1744:              for(jj = jj_begin_row_offd; jj < jj_end_row_offd; jj++)

1745:                 P_offd_data[jj] /= -diagonal;

1746:            }

1747:          }

1748:          strong_f_marker--;

[...]

1754:        if (n_fine)

1755:        {  hypre_TFree(P_marker); }

1756:        if (full_off_procNodes)

1757:        {  hypre_TFree(P_marker_offd); }

0x43b900 STP	X29, X30, [SP, #928]!

0x43b904 STP	X28, X27, [SP, #16]

0x43b908 STP	X26, X25, [SP, #32]

0x43b90c STP	X24, X23, [SP, #48]

0x43b910 STP	X22, X21, [SP, #64]

0x43b914 STP	X20, X19, [SP, #80]

0x43b918 ADD	X29, SP, #0

0x43b91c SUB	SP, SP, #464

0x43b920 STUR	X7, [X29, #464]

0x43b924 STUR	X6, [X29, #488]

0x43b928 LDR	X21, [X2]

0x43b92c STUR	X5, [X29, #448]

0x43b930 STR	X4, [SP, #232]

0x43b934 STR	X0, [SP, #200]

0x43b938 LDR	X8, [X29, #432]

0x43b93c LDR	X0, [X3]

0x43b940 STR	X8, [SP, #104]

0x43b944 LDR	X8, [X29, #424]

0x43b948 STR	X8, [SP, #224]

0x43b94c LDR	X8, [X29, #416]

0x43b950 STR	X8, [SP, #96]

0x43b954 LDR	X8, [X29, #408]

0x43b958 STR	X8, [SP, #88]

0x43b95c LDR	X8, [X29, #400]

0x43b960 STR	X8, [SP, #168]

0x43b964 LDR	X8, [X29, #392]

0x43b968 STR	X8, [SP, #160]

0x43b96c LDR	X8, [X29, #384]

0x43b970 STUR	X8, [X29, #352]

0x43b974 LDR	X8, [X29, #376]

0x43b978 STR	X8, [SP, #152]

0x43b97c LDR	X8, [X29, #368]

0x43b980 STR	X8, [SP, #144]

0x43b984 LDR	X8, [X29, #360]

0x43b988 STR	X8, [SP, #72]

0x43b98c LDR	X8, [X29, #352]

0x43b990 STR	X8, [SP, #112]

0x43b994 LDR	X8, [X29, #344]

0x43b998 STR	X8, [SP, #80]

0x43b99c LDR	X8, [X29, #336]

0x43b9a0 STUR	X8, [X29, #496]

0x43b9a4 LDR	X8, [X29, #328]

0x43b9a8 STUR	X8, [X29, #288]

0x43b9ac LDR	X8, [X29, #320]

0x43b9b0 STR	X8, [SP, #32]

0x43b9b4 LDR	X8, [X29, #312]

0x43b9b8 STR	X8, [SP, #24]

0x43b9bc LDR	X8, [X29, #304]

0x43b9c0 STR	X8, [SP, #16]

0x43b9c4 LDR	X8, [X29, #296]

0x43b9c8 STR	X8, [SP, #40]

0x43b9cc LDR	X8, [X29, #288]

0x43b9d0 STUR	X8, [X29, #416]

0x43b9d4 LDR	X8, [X29, #280]

0x43b9d8 STUR	X8, [X29, #336]

0x43b9dc LDR	X8, [X29, #272]

0x43b9e0 STUR	X8, [X29, #440]

0x43b9e4 LDP	X25, X8, [X29, #256]

0x43b9e8 STUR	X8, [X29, #400]

0x43b9ec LDR	X8, [X29, #248]

0x43b9f0 STR	X8, [SP, #64]

0x43b9f4 LDR	X8, [X29, #240]

0x43b9f8 STR	X8, [SP, #8]

0x43b9fc LDR	X8, [X29, #232]

0x43ba00 STR	X8, [SP, #48]

0x43ba04 LDR	X8, [X29, #224]

0x43ba08 STR	X8, [SP, #56]

0x43ba0c LDP	X9, X26, [X29, #208]

0x43ba10 LDP	X24, X8, [X29, #192]

0x43ba14 STP	X9, X8, [X29, #936]

0x43ba18 LDP	X8, X28, [X29, #176]

0x43ba1c STR	X8, [SP, #136]

0x43ba20 LDR	X8, [X29, #168]

0x43ba24 STR	X8, [SP, #128]

0x43ba28 LDP	X9, X8, [X29, #152]

0x43ba2c STUR	X8, [X29, #456]

0x43ba30 LDR	X8, [X29, #144]

0x43ba34 STUR	X8, [X29, #344]

0x43ba38 LDR	X8, [X29, #136]

0x43ba3c STP	X8, X9, [X29, #832]

0x43ba40 LDR	X8, [X29, #128]

0x43ba44 STUR	X8, [X29, #312]

0x43ba48 LDR	X8, [X29, #120]

0x43ba4c STR	X8, [SP, #208]

0x43ba50 LDR	X8, [X29, #112]

0x43ba54 STR	X8, [SP, #184]

0x43ba58 LDR	X8, [X29, #104]

0x43ba5c STUR	X8, [X29, #408]

0x43ba60 LDR	X8, [X29, #96]

0x43ba64 STR	X8, [SP, #176]

0x43ba68 STUR	X3, [X29, #360]

0x43ba6c CBZ	X0, 43bab8

0x43ba70 MOVZ	W1, #8

0x43ba74 ORR	X19, XZR, X3

0x43ba78 BL	4ae430

0x43ba7c LDR	X8, [X19]

0x43ba80 ORR	X22, XZR, X0

0x43ba84 CMP	X8, #1

0x43ba88 B.LT	43bb18

0x43ba8c LDR	X11, [SP, #232]

0x43ba90 ORR	X8, XZR, XZR

0x43ba94 MOVN	X9, #0

0x43ba98 HINT	#0

0x43ba9c HINT	#0

(206) 0x43baa0 STR	X9, [X22, X8,LSL #3]

(206) 0x43baa4 ADD	X8, X8, #1

(206) 0x43baa8 LDR	X10, [X19]

(206) 0x43baac CMP	X8, X10

(206) 0x43bab0 B.LT	43baa0

0x43bab4 B	43babc

0x43bab8 LDR	X11, [SP, #232]

0x43babc LDR	X0, [X11]

0x43bac0 CBZ	X0, 43bb24

0x43bac4 MOVZ	W1, #8

0x43bac8 ORR	X19, XZR, X11

0x43bacc BL	4ae430

0x43bad0 LDR	X8, [X19]

0x43bad4 ORR	X23, XZR, X0

0x43bad8 CMP	X8, #1

0x43badc B.LT	43bb2c

0x43bae0 ORR	X11, XZR, X19

0x43bae4 LDUR	X19, [X29, #360]

0x43bae8 ORR	X8, XZR, XZR

0x43baec MOVN	X9, #0

0x43baf0 HINT	#0

0x43baf4 HINT	#0

0x43baf8 HINT	#0

0x43bafc HINT	#0

(205) 0x43bb00 STR	X9, [X23, X8,LSL #3]

(205) 0x43bb04 ADD	X8, X8, #1

(205) 0x43bb08 LDR	X10, [X11]

(205) 0x43bb0c CMP	X8, X10

(205) 0x43bb10 B.LT	43bb00

0x43bb14 B	43bb30

0x43bb18 LDR	X11, [SP, #232]

0x43bb1c LDR	X0, [X11]

0x43bb20 CBNZ	X0, 43bac4

0x43bb24 LDUR	X19, [X29, #360]

0x43bb28 B	43bb30

0x43bb2c LDUR	X19, [X29, #360]

0x43bb30 BL	4b05e0

0x43bb34 ORR	X20, XZR, X0

0x43bb38 BL	4b05c0

0x43bb3c LDR	X8, [X19]

0x43bb40 SUB	X9, X0, #1

0x43bb44 CMP	X20, X9

0x43bb48 SDIV	X10, X8, X0

0x43bb4c MADD	X27, X10, X20, XZR

0x43bb50 STR	X10, [SP, #192]

0x43bb54 STUR	X26, [X29, #304]

0x43bb58 ORR	X26, XZR, XZR

0x43bb5c STUR	X20, [X29, #368]

0x43bb60 ADD	X10, X10, X27

0x43bb64 CSEL	X14, X8, X10, #0

0x43bb68 CMP	X14, X27

0x43bb6c STUR	X14, [X29, #384]

0x43bb70 STR	X28, [SP, #120]

0x43bb74 STUR	X0, [X29, #296]

0x43bb78 STR	X25, [SP, #216]

0x43bb7c B.GT	43bc98

0x43bb80 ORR	X19, XZR, X21

0x43bb84 LDR	X8, [SP, #200]

0x43bb88 ADRP	X0,

0x43bb8c ADD	X0, X0, #1224

0x43bb90 LDR	W28, [X8]

0x43bb94 ORR	W1, WZR, W28

0x43bb98 BL	40f900

0x43bb9c LDUR	X8, [X29, #448]

0x43bba0 LDUR	X9, [X29, #464]

0x43bba4 LDUR	X10, [X29, #432]

0x43bba8 ORR	W1, WZR, W28

0x43bbac ADRP	X0,

0x43bbb0 ADD	X0, X0, #1248

0x43bbb4 LDUR	X11, [X29, #384]

0x43bbb8 LDUR	X20, [X29, #368]

0x43bbbc LDR	X8, [X8]

0x43bbc0 LDR	X9, [X9]

0x43bbc4 LDR	X10, [X10]

0x43bbc8 STR	X19, [X8, X11,LSL #3]

0x43bbcc LDUR	X8, [X29, #424]

0x43bbd0 STR	X21, [X9, X11,LSL #3]

0x43bbd4 LDR	X8, [X8]

0x43bbd8 STR	X26, [X10, X20,LSL #3]

0x43bbdc LDUR	X26, [X29, #304]

0x43bbe0 STR	X19, [X8, X20,LSL #3]

0x43bbe4 LDR	X8, [X26]

0x43bbe8 STR	X21, [X8, X20,LSL #3]

0x43bbec ORR	W21, WZR, W28

0x43bbf0 BL	40f900

0x43bbf4 LDUR	X19, [X29, #360]

0x43bbf8 LDR	X25, [SP, #216]

0x43bbfc LDUR	X12, [X29, #296]

0x43bc00 CBNZ	X20, 43c08c

0x43bc04 SUBS	X8, X12, #1

0x43bc08 B.LE	43c08c

0x43bc0c LDUR	X9, [X29, #424]

0x43bc10 LDR	X11, [X26]

0x43bc14 UBFM	X12, X12, #61, #60

0x43bc18 LDR	X10, [X9]

0x43bc1c LDUR	X9, [X29, #432]

0x43bc20 ADD	X13, X11, X12

0x43bc24 LDR	X9, [X9]

0x43bc28 ADD	X14, X10, X12

0x43bc2c CMP	X10, X13

0x43bc30 CCMP	X11, X14, #2, #3

0x43bc34 ADD	X15, X9, X12

0x43bc38 CSINC	W12, WZR, WZR, #2

0x43bc3c CMP	X9, X13

0x43bc40 CCMP	X11, X15, #2, #3

0x43bc44 CSINC	W13, WZR, WZR, #2

0x43bc48 CMP	X9, X14

0x43bc4c CCMP	X10, X15, #2, #3

0x43bc50 B.CC	43c048

0x43bc54 TBNZ	W12, #0, 43c048

0x43bc58 CBNZ	W13, 43c048

0x43bc5c LDR	X12, [X10], #8

0x43bc60 LDR	X13, [X11], #8

0x43bc64 LDR	X14, [X9], #8

(196) 0x43bc68 LDR	X15, [X10]

(196) 0x43bc6c SUBS	X8, X8, #1

(196) 0x43bc70 ADD	X12, X15, X12

(196) 0x43bc74 STR	X12, [X10], #8

(196) 0x43bc78 LDR	X15, [X9]

(196) 0x43bc7c ADD	X14, X15, X14

(196) 0x43bc80 STR	X14, [X9], #8

(196) 0x43bc84 LDR	X15, [X11]

(196) 0x43bc88 ADD	X13, X15, X13

(196) 0x43bc8c STR	X13, [X11], #8

(196) 0x43bc90 B.NE	43bc68

0x43bc94 B	43c08c

0x43bc98 LDUR	X9, [X29, #464]

0x43bc9c LDUR	X8, [X29, #448]

0x43bca0 ORR	X18, XZR, X27

0x43bca4 ORR	X19, XZR, X21

0x43bca8 LDR	X16, [X9]

0x43bcac LDR	X9, [SP, #176]

0x43bcb0 LDR	X8, [X8]

0x43bcb4 LDR	X10, [X9]

0x43bcb8 LDR	X9, [SP, #184]

0x43bcbc LDR	X11, [X9]

0x43bcc0 LDR	X9, [SP, #208]

0x43bcc4 STUR	X16, [X29, #392]

0x43bcc8 LDR	X12, [X9]

0x43bccc LDUR	X9, [X29, #312]

0x43bcd0 LDR	X13, [X9]

0x43bcd4 LDUR	X9, [X29, #344]

0x43bcd8 LDR	X9, [X9]

0x43bcdc STUR	X9, [X29, #480]

0x43bce0 LDUR	X9, [X29, #320]

0x43bce4 LDR	X15, [X9]

0x43bce8 LDUR	X9, [X29, #328]

0x43bcec LDR	X9, [X9]

0x43bcf0 STUR	X9, [X29, #472]

0x43bcf4 LDUR	X9, [X29, #408]

0x43bcf8 LDR	X17, [X9]

0x43bcfc STUR	X17, [X29, #376]

0x43bd00 B	43bd24

      (197) 0x43bd04 LDR	X9, [X10, X18,LSL #3]

      (197) 0x43bd08 TBNZ	X9, #63, 43bd40

      (197) 0x43bd0c ADD	X19, X19, #1

      (197) 0x43bd10 STR	X26, [X17, X18,LSL #3]

      (197) 0x43bd14 ADD	X26, X26, #1

      (197) 0x43bd18 ADD	X18, X18, #1

      (197) 0x43bd1c CMP	X18, X14

      (197) 0x43bd20 B.EQ	43bb84

      (197) 0x43bd24 LDUR	X9, [X29, #488]

      (197) 0x43bd28 STR	X19, [X8, X18,LSL #3]

      (197) 0x43bd2c LDR	X9, [X9]

      (197) 0x43bd30 CMP	X9, #2

      (197) 0x43bd34 B.LT	43bd04

      (197) 0x43bd38 STR	X21, [X16, X18,LSL #3]

      (197) 0x43bd3c B	43bd04

      (197) 0x43bd40 CMN	X9, #3

      (197) 0x43bd44 B.EQ	43bd18

      (197) 0x43bd48 ADD	X1, X18, #1

      (197) 0x43bd4c LDR	X2, [X11, X18,LSL #3]

      (197) 0x43bd50 LDR	X9, [X11, X1,LSL #3]

      (197) 0x43bd54 CMP	X2, X9

      (197) 0x43bd58 B.GE	43beec

      (197) 0x43bd5c LDUR	X9, [X29, #312]

      (197) 0x43bd60 LDR	X3, [X9]

      (197) 0x43bd64 LDUR	X9, [X29, #320]

      (197) 0x43bd68 LDR	X4, [X9]

      (197) 0x43bd6c LDUR	X9, [X29, #328]

      (197) 0x43bd70 LDR	X5, [X9]

      (197) 0x43bd74 B	43bd90

0x43bd78 HINT	#0

0x43bd7c HINT	#0

        (201) 0x43bd80 LDR	X9, [X11, X1,LSL #3]

        (201) 0x43bd84 ADD	X2, X2, #1

        (201) 0x43bd88 CMP	X2, X9

        (201) 0x43bd8c B.GE	43bee4

        (201) 0x43bd90 LDR	X9, [X12, X2,LSL #3]

        (201) 0x43bd94 LDR	X14, [X10, X9,LSL #3]

        (201) 0x43bd98 TBNZ	X14, #63, 43bdc0

        (201) 0x43bd9c LDR	X14, [X22, X9,LSL #3]

        (201) 0x43bda0 LDR	X0, [X8, X18,LSL #3]

        (201) 0x43bda4 CMP	X14, X0

        (201) 0x43bda8 B.GE	43bd80

        (201) 0x43bdac STR	X19, [X22, X9,LSL #3]

        (201) 0x43bdb0 ADD	X19, X19, #1

        (201) 0x43bdb4 B	43bd80

0x43bdb8 HINT	#0

0x43bdbc HINT	#0

        (201) 0x43bdc0 CMN	X14, #3

        (201) 0x43bdc4 B.EQ	43bd80

        (201) 0x43bdc8 ADD	X6, X9, #1

        (201) 0x43bdcc LDR	X0, [X11, X9,LSL #3]

        (201) 0x43bdd0 LDR	X7, [X11, X6,LSL #3]

        (201) 0x43bdd4 B	43bde4

0x43bdd8 HINT	#0

0x43bddc HINT	#0

          (204) 0x43bde0 ADD	X0, X0, #1

          (204) 0x43bde4 CMP	X0, X7

          (204) 0x43bde8 B.GE	43be18

          (204) 0x43bdec LDR	X14, [X12, X0,LSL #3]

          (204) 0x43bdf0 LDR	X20, [X10, X14,LSL #3]

          (204) 0x43bdf4 TBNZ	X20, #63, 43bde0

          (204) 0x43bdf8 LDR	X20, [X22, X14,LSL #3]

          (204) 0x43bdfc LDR	X30, [X8, X18,LSL #3]

          (204) 0x43be00 CMP	X20, X30

          (204) 0x43be04 B.GE	43bde0

          (204) 0x43be08 STR	X19, [X22, X14,LSL #3]

          (204) 0x43be0c ADD	X19, X19, #1

          (204) 0x43be10 LDR	X7, [X11, X6,LSL #3]

          (204) 0x43be14 B	43bde0

        (201) 0x43be18 LDUR	X14, [X29, #488]

        (201) 0x43be1c LDR	X14, [X14]

        (201) 0x43be20 CMP	X14, #2

        (201) 0x43be24 B.LT	43bd80

        (201) 0x43be28 LDR	X7, [X3, X9,LSL #3]

        (201) 0x43be2c LDR	X0, [X3, X6,LSL #3]

        (201) 0x43be30 CMP	X7, X0

        (201) 0x43be34 B.GE	43bd80

        (201) 0x43be38 LDUR	X9, [X29, #344]

        (201) 0x43be3c LDR	X20, [X9]

        (201) 0x43be40 LDUR	X9, [X29, #464]

        (201) 0x43be44 LDR	X30, [X9]

        (201) 0x43be48 LDUR	X9, [X29, #456]

        (201) 0x43be4c LDR	X9, [X9]

        (201) 0x43be50 CBNZ	X4, 43be6c

        (201) 0x43be54 B	43beb0

0x43be58 HINT	#0

0x43be5c HINT	#0

          (202) 0x43be60 ADD	X7, X7, #1

          (202) 0x43be64 CMP	X7, X0

          (202) 0x43be68 B.GE	43bd80

          (202) 0x43be6c LDR	X14, [X20, X7,LSL #3]

          (202) 0x43be70 LDR	X14, [X4, X14,LSL #3]

          (202) 0x43be74 LDR	X16, [X5, X14,LSL #3]

          (202) 0x43be78 TBNZ	X16, #63, 43be60

          (202) 0x43be7c LDR	X16, [X23, X14,LSL #3]

          (202) 0x43be80 LDR	X17, [X30, X18,LSL #3]

          (202) 0x43be84 CMP	X16, X17

          (202) 0x43be88 B.GE	43be60

          (202) 0x43be8c MOVZ	W16, #1

          (202) 0x43be90 STR	X16, [X9, X14,LSL #3]

          (202) 0x43be94 STR	X21, [X23, X14,LSL #3]

          (202) 0x43be98 ADD	X21, X21, #1

          (202) 0x43be9c LDR	X0, [X3, X6,LSL #3]

          (202) 0x43bea0 B	43be60

          (203) 0x43bea4 ADD	X7, X7, #1

          (203) 0x43bea8 CMP	X7, X0

          (203) 0x43beac B.GE	43bd80

          (203) 0x43beb0 LDR	X14, [X20, X7,LSL #3]

          (203) 0x43beb4 LDR	X16, [X5, X14,LSL #3]

          (203) 0x43beb8 TBNZ	X16, #63, 43bea4

          (203) 0x43bebc LDR	X16, [X23, X14,LSL #3]

          (203) 0x43bec0 LDR	X17, [X30, X18,LSL #3]

          (203) 0x43bec4 CMP	X16, X17

          (203) 0x43bec8 B.GE	43bea4

          (203) 0x43becc MOVZ	W16, #1

          (203) 0x43bed0 STR	X16, [X9, X14,LSL #3]

          (203) 0x43bed4 STR	X21, [X23, X14,LSL #3]

          (203) 0x43bed8 ADD	X21, X21, #1

          (203) 0x43bedc LDR	X0, [X3, X6,LSL #3]

          (203) 0x43bee0 B	43bea4

      (197) 0x43bee4 LDP	X14, X16, [X29, #896]

      (197) 0x43bee8 LDUR	X17, [X29, #376]

      (197) 0x43beec LDUR	X9, [X29, #488]

      (197) 0x43bef0 LDR	X9, [X9]

      (197) 0x43bef4 CMP	X9, #2

      (197) 0x43bef8 B.LT	43bd18

      (197) 0x43befc LDR	X2, [X13, X18,LSL #3]

      (197) 0x43bf00 LDR	X9, [X13, X1,LSL #3]

      (197) 0x43bf04 CMP	X2, X9

      (197) 0x43bf08 B.GE	43bd18

    (198) 0x43bf0c LDR	X9, [SP, #128]

    (198) 0x43bf10 LDR	X25, [X9]

    (198) 0x43bf14 LDR	X9, [SP, #136]

    (198) 0x43bf18 LDR	X4, [X9]

    (198) 0x43bf1c LDUR	X9, [X29, #464]

    (198) 0x43bf20 ADD	X7, X25, #8

    (198) 0x43bf24 LDR	X5, [X9]

    (198) 0x43bf28 LDUR	X9, [X29, #456]

    (198) 0x43bf2c LDR	X6, [X9]

    (198) 0x43bf30 B	43bf50

0x43bf34 HINT	#0

0x43bf38 HINT	#0

0x43bf3c HINT	#0

    (198) 0x43bf40 LDR	X9, [X13, X1,LSL #3]

    (198) 0x43bf44 ADD	X2, X2, #1

    (198) 0x43bf48 CMP	X2, X9

    (198) 0x43bf4c B.GE	43c03c

    (198) 0x43bf50 LDUR	X9, [X29, #480]

    (198) 0x43bf54 LDR	X20, [X9, X2,LSL #3]

    (198) 0x43bf58 CBZ	X15, 43bf60

    (198) 0x43bf5c LDR	X20, [X15, X20,LSL #3]

    (198) 0x43bf60 LDUR	X9, [X29, #472]

    (198) 0x43bf64 LDR	X9, [X9, X20,LSL #3]

    (198) 0x43bf68 TBNZ	X9, #63, 43bfa0

    (198) 0x43bf6c LDR	X9, [X23, X20,LSL #3]

    (198) 0x43bf70 LDR	X14, [X5, X18,LSL #3]

    (198) 0x43bf74 CMP	X9, X14

    (198) 0x43bf78 B.GE	43bf40

    (198) 0x43bf7c MOVZ	W9, #1

    (198) 0x43bf80 STR	X9, [X6, X20,LSL #3]

    (198) 0x43bf84 STR	X21, [X23, X20,LSL #3]

    (198) 0x43bf88 ADD	X21, X21, #1

    (198) 0x43bf8c B	43bf40

0x43bf90 HINT	#0

0x43bf94 HINT	#0

0x43bf98 HINT	#0

0x43bf9c HINT	#0

    (198) 0x43bfa0 CMN	X9, #3

    (198) 0x43bfa4 B.EQ	43bf40

    (198) 0x43bfa8 LDR	X9, [X25, X20,LSL #3]

    (198) 0x43bfac LDR	X14, [X7, X20,LSL #3]

    (198) 0x43bfb0 CMP	X9, X14

    (198) 0x43bfb4 B.GE	43bf40

  (200) 0x43bfb8 LDUR	X14, [X29, #464]

  (200) 0x43bfbc LDR	X0, [X14]

  (200) 0x43bfc0 LDUR	X14, [X29, #456]

  (200) 0x43bfc4 LDR	X30, [X14]

  (200) 0x43bfc8 B	43bfdc

  (200) 0x43bfcc LDR	X14, [X7, X20,LSL #3]

  (200) 0x43bfd0 ADD	X9, X9, #1

  (200) 0x43bfd4 CMP	X9, X14

  (200) 0x43bfd8 B.GE	43bf40

  (200) 0x43bfdc LDR	X3, [X4, X9,LSL #3]

  (200) 0x43bfe0 LDR	X14, [X28]

  (200) 0x43bfe4 LDR	X16, [X24]

  (200) 0x43bfe8 SUBS	X14, X3, X14

  (200) 0x43bfec CCMP	X3, X16, #0, #10

  (200) 0x43bff0 B.LT	43c020

  (200) 0x43bff4 ORN	X14, XZR, X3

  (200) 0x43bff8 LDR	X17, [X0, X18,LSL #3]

  (200) 0x43bffc LDR	X16, [X23, X14,LSL #3]

  (200) 0x43c000 CMP	X16, X17

  (200) 0x43c004 B.GE	43bfcc

  (200) 0x43c008 STR	X21, [X23, X14,LSL #3]

  (200) 0x43c00c MOVZ	W16, #1

  (200) 0x43c010 ADD	X21, X21, #1

  (200) 0x43c014 STR	X16, [X30, X14,LSL #3]

  (200) 0x43c018 B	43bfcc

0x43c01c HINT	#0

(199) 0x43c020 LDR	X16, [X22, X14,LSL #3]

(199) 0x43c024 LDR	X17, [X8, X18,LSL #3]

(199) 0x43c028 CMP	X16, X17

(199) 0x43c02c B.GE	43bfcc

(199) 0x43c030 STR	X19, [X22, X14,LSL #3]

(199) 0x43c034 ADD	X19, X19, #1

(199) 0x43c038 B	43bfcc

    (198) 0x43c03c LDP	X14, X16, [X29, #896]

    (198) 0x43c040 LDUR	X17, [X29, #376]

    (198) 0x43c044 B	43bd18

0x43c048 ADD	X11, X11, #8

0x43c04c ADD	X10, X10, #8

0x43c050 ADD	X9, X9, #8

0x43c054 HINT	#0

0x43c058 HINT	#0

0x43c05c HINT	#0

(195) 0x43c060 LDP	X12, X13, [X10, #1016]

(195) 0x43c064 SUBS	X8, X8, #1

(195) 0x43c068 ADD	X12, X13, X12

(195) 0x43c06c STR	X12, [X10], #8

(195) 0x43c070 LDP	X12, X13, [X9, #1016]

(195) 0x43c074 ADD	X12, X13, X12

(195) 0x43c078 STR	X12, [X9], #8

(195) 0x43c07c LDP	X12, X13, [X11, #1016]

(195) 0x43c080 ADD	X12, X13, X12

(195) 0x43c084 STR	X12, [X11], #8

(195) 0x43c088 B.NE	43c060

0x43c08c ORR	W1, WZR, W21

0x43c090 ADRP	X0,

0x43c094 ADD	X0, X0, #1272

0x43c098 BL	40f900

0x43c09c LDUR	X4, [X29, #384]

0x43c0a0 LDR	X28, [SP, #120]

0x43c0a4 SUBS	X8, X20, #1

0x43c0a8 B.LT	43c28c

0x43c0ac SUBS	X9, X4, X27

0x43c0b0 B.LE	43c28c

0x43c0b4 LDUR	X10, [X29, #424]

0x43c0b8 LDUR	X12, [X29, #448]

0x43c0bc LDUR	X13, [X29, #464]

0x43c0c0 CNTW	X14, ALL

0x43c0c4 MOVZ	W15, #16

0x43c0c8 UBFM	X11, X8, #61, #60

0x43c0cc CMP	X14, #16

0x43c0d0 LDR	X17, [X26]

0x43c0d4 CSEL	X15, X14, X15, #8

0x43c0d8 LDR	X16, [X10]

0x43c0dc LDR	X12, [X12]

0x43c0e0 LDR	X13, [X13]

0x43c0e4 CMP	X9, X15

0x43c0e8 ORR	X15, XZR, X27

0x43c0ec ADD	X10, X16, X11

0x43c0f0 ADD	X11, X17, X11

0x43c0f4 B.CC	43c20c

0x43c0f8 UBFM	X18, X4, #61, #60

0x43c0fc UBFM	X15, X27, #61, #60

0x43c100 ADD	X18, X18, #8

0x43c104 ADD	X15, X15, #8

0x43c108 ADD	X2, X12, X18

0x43c10c ADD	X3, X13, X18

0x43c110 UBFM	X18, X20, #61, #60

0x43c114 ADD	X1, X12, X15

0x43c118 ADD	X15, X13, X15

0x43c11c ADD	X16, X16, X18

0x43c120 ADD	X4, X17, X18

0x43c124 CMP	X1, X16

0x43c128 CCMP	X10, X2, #2, #3

0x43c12c CSINC	W0, WZR, WZR, #2

0x43c130 CMP	X1, X4

0x43c134 CCMP	X11, X2, #2, #3

0x43c138 CSINC	W18, WZR, WZR, #2

0x43c13c CMP	X15, X16

0x43c140 CCMP	X10, X3, #2, #3

0x43c144 CSINC	W17, WZR, WZR, #2

0x43c148 CMP	X15, X4

0x43c14c LDUR	X4, [X29, #384]

0x43c150 CCMP	X11, X3, #2, #3

0x43c154 CSINC	W16, WZR, WZR, #2

0x43c158 CMP	X15, X2

0x43c15c ORR	X15, XZR, X27

0x43c160 CCMP	X1, X3, #2, #3

0x43c164 B.CC	43c20c

0x43c168 ORR	X15, XZR, X27

0x43c16c TBNZ	W0, #0, 43c20c

0x43c170 ORR	X15, XZR, X27

0x43c174 TBNZ	W18, #0, 43c20c

0x43c178 ORR	X15, XZR, X27

0x43c17c TBNZ	W17, #0, 43c20c

0x43c180 ORR	X15, XZR, X27

0x43c184 TBNZ	W16, #0, 43c20c

0x43c188 UDIV	X15, X9, X14

0x43c18c LDR	X0, [SP, #192]

0x43c190 PTRUE	P0.D, ALL

0x43c194 ORR	X16, XZR, XZR

0x43c198 LD1RD	{Z0.D}, P0/Z, [X10]

0x43c19c LD1RD	{Z1.D}, P0/Z, [X11]

0x43c1a0 MADD	X0, X20, X0, XZR

0x43c1a4 UBFM	X0, X0, #61, #60

0x43c1a8 ADD	X3, X0, #8

0x43c1ac ADDVL	X2, X3, #1

0x43c1b0 ADD	X1, X13, X3

0x43c1b4 ADD	X3, X12, X3

0x43c1b8 ADD	X0, X13, X2

0x43c1bc ADD	X2, X12, X2

0x43c1c0 MADD	X18, X15, X14, XZR

0x43c1c4 SUB	X17, X9, X18

0x43c1c8 ADD	X15, X27, X18

(194) 0x43c1cc LD1D	{Z2.D}, P0/Z, [X3, X16,LSL #3]

(194) 0x43c1d0 LD1D	{Z3.D}, P0/Z, [X2, X16,LSL #3]

(194) 0x43c1d4 ADD	Z2.D, Z2.D, Z0.D

(194) 0x43c1d8 ADD	Z3.D, Z3.D, Z0.D

(194) 0x43c1dc ST1D	{Z2.D}, P0, [X3, X16,LSL #3]

(194) 0x43c1e0 ST1D	{Z3.D}, P0, [X2, X16,LSL #3]

(194) 0x43c1e4 LD1D	{Z2.D}, P0/Z, [X1, X16,LSL #3]

(194) 0x43c1e8 LD1D	{Z3.D}, P0/Z, [X0, X16,LSL #3]

(194) 0x43c1ec ADD	Z2.D, Z2.D, Z1.D

(194) 0x43c1f0 ADD	Z3.D, Z3.D, Z1.D

(194) 0x43c1f4 ST1D	{Z2.D}, P0, [X1, X16,LSL #3]

(194) 0x43c1f8 ST1D	{Z3.D}, P0, [X0, X16,LSL #3]

(194) 0x43c1fc ADD	X16, X16, X14

(194) 0x43c200 CMP	X18, X16

(194) 0x43c204 B.NE	43c1cc

0x43c208 CBZ	X17, 43c248

0x43c20c SUB	X14, X4, X15

0x43c210 UBFM	X15, X15, #61, #60

0x43c214 ADD	X15, X15, #8

0x43c218 ADD	X13, X13, X15

0x43c21c ADD	X12, X12, X15

(192) 0x43c220 LDR	X15, [X10]

(192) 0x43c224 LDR	X16, [X12]

(192) 0x43c228 SUBS	X14, X14, #1

(192) 0x43c22c ADD	X15, X16, X15

(192) 0x43c230 STR	X15, [X12], #8

(192) 0x43c234 LDR	X15, [X11]

(192) 0x43c238 LDR	X16, [X13]

(192) 0x43c23c ADD	X15, X16, X15

(192) 0x43c240 STR	X15, [X13], #8

(192) 0x43c244 B.NE	43c220

0x43c248 LDUR	X10, [X29, #408]

0x43c24c LDR	X12, [SP, #192]

0x43c250 LDR	X11, [X10]

0x43c254 LDUR	X10, [X29, #432]

0x43c258 MADD	X12, X20, X12, XZR

0x43c25c LDR	X10, [X10]

0x43c260 ADD	X11, X11, X12,LSL #3

0x43c264 B	43c274

(193) 0x43c268 SUBS	X9, X9, #1

(193) 0x43c26c ADD	X11, X11, #8

(193) 0x43c270 B.EQ	43c28c

(193) 0x43c274 LDR	X12, [X11]

(193) 0x43c278 TBNZ	X12, #63, 43c268

(193) 0x43c27c LDR	X13, [X10, X8,LSL #3]

(193) 0x43c280 ADD	X12, X13, X12

(193) 0x43c284 STR	X12, [X11]

(193) 0x43c288 B	43c268

0x43c28c ORR	W1, WZR, W21

0x43c290 ADRP	X0,

0x43c294 ADD	X0, X0, #1296

0x43c298 BL	40f900

0x43c29c CBNZ	X20, 43c46c

0x43c2a0 LDR	X9, [SP, #56]

0x43c2a4 LDR	X8, [X9]

0x43c2a8 CMP	X8, #4

0x43c2ac B.NE	43c2fc

0x43c2b0 ORR	X20, XZR, X9

0x43c2b4 BL	4b0670

0x43c2b8 LDR	X8, [SP, #48]

0x43c2bc ADRP	X0,

0x43c2c0 ADD	X0, X0, #1777

0x43c2c4 LDR	D1, [X8]

0x43c2c8 FSUB	D0, D0, S1

0x43c2cc STR	D0, [X8]

0x43c2d0 LDR	X8, [SP, #8]

0x43c2d4 LDR	X1, [X8]

0x43c2d8 BL	4ae640

0x43c2dc ORR	X0, XZR, XZR

0x43c2e0 BL	40f7d0

0x43c2e4 LDR	X8, [X20]

0x43c2e8 CMP	X8, #4

0x43c2ec B.NE	43c2fc

0x43c2f0 BL	4b0670

0x43c2f4 LDR	X8, [SP, #48]

0x43c2f8 STR	D0, [X8]

0x43c2fc LDUR	X8, [X29, #448]

0x43c300 LDR	X9, [X19]

0x43c304 LDR	X10, [SP, #64]

0x43c308 LDR	X8, [X8]

0x43c30c LDR	X8, [X8, X9,LSL #3]

0x43c310 STR	X8, [X10]

0x43c314 LDUR	X8, [X29, #464]

0x43c318 LDR	X9, [X19]

0x43c31c LDR	X8, [X8]

0x43c320 LDR	X0, [X8, X9,LSL #3]

0x43c324 STR	X0, [X25]

0x43c328 LDR	X8, [X10]

0x43c32c CBZ	X8, 43c360

0x43c330 ORR	X0, XZR, X8

0x43c334 MOVZ	W1, #8

0x43c338 ORR	X20, XZR, X10

0x43c33c BL	4ae430

0x43c340 LDUR	X8, [X29, #400]

0x43c344 MOVZ	W1, #8

0x43c348 STR	X0, [X8]

0x43c34c LDR	X0, [X20]

0x43c350 BL	4ae430

0x43c354 LDUR	X8, [X29, #440]

0x43c358 STR	X0, [X8]

0x43c35c LDR	X0, [X25]

0x43c360 CBZ	X0, 43c388

0x43c364 MOVZ	W1, #8

0x43c368 BL	4ae430

0x43c36c LDUR	X8, [X29, #336]

0x43c370 MOVZ	W1, #8

0x43c374 STR	X0, [X8]

0x43c378 LDR	X0, [X25]

0x43c37c BL	4ae430

0x43c380 LDUR	X8, [X29, #416]

0x43c384 STR	X0, [X8]

0x43c388 LDUR	X8, [X29, #488]

0x43c38c LDR	X8, [X8]

0x43c390 CMP	X8, #2

0x43c394 B.LT	43c46c

0x43c398 LDR	X8, [X19]

0x43c39c CMP	X8, #1

0x43c3a0 B.LT	43c3e0

0x43c3a4 LDUR	X9, [X29, #408]

0x43c3a8 LDR	X12, [SP, #40]

0x43c3ac ORR	X8, XZR, XZR

0x43c3b0 LDR	X9, [X9]

0x43c3b4 HINT	#0

0x43c3b8 HINT	#0

0x43c3bc HINT	#0

(191) 0x43c3c0 LDR	X10, [X12]

(191) 0x43c3c4 LDR	X11, [X9, X8,LSL #3]

(191) 0x43c3c8 ADD	X10, X11, X10

(191) 0x43c3cc STR	X10, [X9, X8,LSL #3]

(191) 0x43c3d0 ADD	X8, X8, #1

(191) 0x43c3d4 LDR	X10, [X19]

(191) 0x43c3d8 CMP	X8, X10

(191) 0x43c3dc B.LT	43c3c0

0x43c3e0 LDR	X8, [SP, #16]

0x43c3e4 LDR	X19, [SP, #232]

0x43c3e8 LDR	X0, [X8]

0x43c3ec LDR	X8, [SP, #24]

0x43c3f0 LDR	X3, [X19]

0x43c3f4 LDR	X1, [X8]

0x43c3f8 LDUR	X8, [X29, #408]

0x43c3fc LDR	X2, [X8]

0x43c400 LDR	X8, [SP, #32]

0x43c404 LDR	X4, [X8]

0x43c408 BL	47df40

0x43c40c ORR	X12, XZR, X19

0x43c410 LDUR	X19, [X29, #360]

0x43c414 LDR	X8, [X19]

0x43c418 CMP	X8, #1

0x43c41c B.LT	43c498

0x43c420 LDUR	X9, [X29, #408]

0x43c424 LDR	X13, [SP, #40]

0x43c428 ORR	X8, XZR, XZR

0x43c42c LDR	X9, [X9]

0x43c430 HINT	#0

0x43c434 HINT	#0

0x43c438 HINT	#0

0x43c43c HINT	#0

(190) 0x43c440 LDR	X10, [X13]

(190) 0x43c444 LDR	X11, [X9, X8,LSL #3]

(190) 0x43c448 SUB	X10, X11, X10

(190) 0x43c44c STR	X10, [X9, X8,LSL #3]

(190) 0x43c450 ADD	X8, X8, #1

(190) 0x43c454 LDR	X10, [X19]

(190) 0x43c458 CMP	X8, X10

(190) 0x43c45c B.LT	43c440

0x43c460 CMP	X10, #1

0x43c464 B.GE	43c47c

0x43c468 B	43c498

0x43c46c LDR	X10, [X19]

0x43c470 LDR	X12, [SP, #232]

0x43c474 CMP	X10, #1

0x43c478 B.LT	43c498

0x43c47c ORR	X8, XZR, XZR

0x43c480 MOVN	X9, #0

(189) 0x43c484 STR	X9, [X22, X8,LSL #3]

(189) 0x43c488 ADD	X8, X8, #1

(189) 0x43c48c LDR	X10, [X19]

(189) 0x43c490 CMP	X8, X10

(189) 0x43c494 B.LT	43c484

0x43c498 LDR	X8, [X12]

0x43c49c CMP	X8, #1

0x43c4a0 B.LT	43c4c0

0x43c4a4 ORR	X8, XZR, XZR

0x43c4a8 MOVN	X9, #0

(188) 0x43c4ac STR	X9, [X23, X8,LSL #3]

(188) 0x43c4b0 ADD	X8, X8, #1

(188) 0x43c4b4 LDR	X10, [X12]

(188) 0x43c4b8 CMP	X8, X10

(188) 0x43c4bc B.LT	43c4ac

0x43c4c0 ORR	W1, WZR, W21

0x43c4c4 ADRP	X0,

0x43c4c8 ADD	X0, X0, #1320

0x43c4cc BL	40f900

0x43c4d0 LDUR	X13, [X29, #384]

0x43c4d4 CMP	X13, X27

0x43c4d8 B.GT	43c51c

0x43c4dc LDR	X8, [X19]

0x43c4e0 CBZ	X8, 43c4ec

0x43c4e4 ORR	X0, XZR, X22

0x43c4e8 BL	4ae530

0x43c4ec LDR	X8, [SP, #232]

0x43c4f0 LDR	X8, [X8]

0x43c4f4 CBZ	X8, 43d26c

0x43c4f8 ORR	X0, XZR, X23

0x43c4fc ADD	SP, SP, #464

0x43c500 LDP	X20, X19, [SP, #80]

0x43c504 LDP	X22, X21, [SP, #64]

0x43c508 LDP	X24, X23, [SP, #48]

0x43c50c LDP	X26, X25, [SP, #32]

0x43c510 LDP	X28, X27, [SP, #16]

0x43c514 LDP	X29, X30, [SP], #96

0x43c518 B	4ae530

0x43c51c LDUR	X8, [X29, #448]

0x43c520 FMOV	D0, #1.0000000

0x43c524 FMOV	D1, #-1.0000000

0x43c528 PTRUE	P0.D, ALL

0x43c52c MOVN	X6, #1

0x43c530 LDR	X14, [X8]

0x43c534 LDUR	X8, [X29, #464]

0x43c538 LDR	X8, [X8]

0x43c53c STR	X8, [SP, #200]

0x43c540 LDR	X8, [SP, #176]

0x43c544 LDR	X10, [X8]

0x43c548 LDR	X8, [SP, #184]

0x43c54c LDR	X11, [X8]

0x43c550 LDR	X8, [SP, #208]

0x43c554 LDR	X12, [X8]

0x43c558 LDUR	X8, [X29, #312]

0x43c55c LDR	X9, [X8]

0x43c560 LDUR	X8, [X29, #344]

0x43c564 LDR	X8, [X8]

0x43c568 STP	X8, X9, [X29, #984]

0x43c56c LDUR	X8, [X29, #320]

0x43c570 LDR	X17, [X8]

0x43c574 LDUR	X8, [X29, #328]

0x43c578 LDR	X8, [X8]

0x43c57c STUR	X8, [X29, #464]

0x43c580 LDR	X8, [SP, #80]

0x43c584 LDR	X9, [X8]

0x43c588 LDR	X8, [SP, #112]

0x43c58c LDR	X8, [X8]

0x43c590 STUR	X8, [X29, #432]

0x43c594 LDR	X8, [SP, #72]

0x43c598 LDR	X0, [X8]

0x43c59c LDR	X8, [SP, #144]

0x43c5a0 LDR	X8, [X8]

0x43c5a4 STR	X8, [SP, #112]

0x43c5a8 LDR	X8, [SP, #152]

0x43c5ac STUR	X9, [X29, #456]

0x43c5b0 LDR	X8, [X8]

0x43c5b4 STUR	X8, [X29, #392]

0x43c5b8 LDUR	X8, [X29, #440]

0x43c5bc LDR	X15, [X8]

0x43c5c0 ADD	X8, X0, #8

0x43c5c4 STUR	X8, [X29, #376]

0x43c5c8 ADD	X8, X9, #8

0x43c5cc STUR	X8, [X29, #368]

0x43c5d0 LDUR	X8, [X29, #416]

0x43c5d4 LDR	X8, [X8]

0x43c5d8 STR	X8, [SP, #80]

0x43c5dc LDUR	X8, [X29, #408]

0x43c5e0 LDUR	X9, [X29, #288]

0x43c5e4 STUR	X17, [X29, #424]

0x43c5e8 STUR	X0, [X29, #448]

0x43c5ec LDR	X16, [X8]

0x43c5f0 LDUR	X8, [X29, #400]

0x43c5f4 STR	X14, [SP, #192]

0x43c5f8 LDR	X18, [X8]

0x43c5fc STUR	X15, [X29, #304]

0x43c600 STP	X18, X16, [SP, #176]

0x43c604 B	43c628

        (167) 0x43c608 LDR	D2, [X9]

        (167) 0x43c60c LDR	X8, [X16, X27,LSL #3]

        (167) 0x43c610 STR	X8, [X18, X5,LSL #3]

        (167) 0x43c614 STR	D2, [X15, X5,LSL #3]

        (167) 0x43c618 ADD	X27, X27, #1

        (167) 0x43c61c SUB	X6, X6, #1

        (167) 0x43c620 CMP	X27, X13

        (167) 0x43c624 B.EQ	43c4dc

        (167) 0x43c628 LDR	X5, [X14, X27,LSL #3]

        (167) 0x43c62c LDR	X8, [X10, X27,LSL #3]

        (167) 0x43c630 TBZ	X8, #63, 43c608

        (167) 0x43c634 CMN	X8, #3

        (167) 0x43c638 B.EQ	43c618

      (168) 0x43c63c LDR	X8, [SP, #200]

      (168) 0x43c640 ADD	X9, X27, #1

      (168) 0x43c644 ORR	X7, XZR, X5

      (168) 0x43c648 SUB	X6, X6, #1

      (168) 0x43c64c LDR	X13, [X11, X9,LSL #3]

      (168) 0x43c650 LDR	X1, [X8, X27,LSL #3]

      (168) 0x43c654 LDR	X8, [X11, X27,LSL #3]

      (168) 0x43c658 ORR	X4, XZR, X1

      (168) 0x43c65c CMP	X8, X13

      (168) 0x43c660 B.GE	43c850

      (168) 0x43c664 LDUR	X13, [X29, #312]

      (168) 0x43c668 ORR	X7, XZR, X5

      (168) 0x43c66c ORR	X4, XZR, X1

      (168) 0x43c670 LDR	X14, [X13]

      (168) 0x43c674 LDUR	X13, [X29, #320]

      (168) 0x43c678 LDR	X16, [X13]

      (168) 0x43c67c LDUR	X13, [X29, #328]

      (168) 0x43c680 LDR	X2, [X13]

      (168) 0x43c684 LDUR	X13, [X29, #408]

      (168) 0x43c688 LDR	X3, [X13]

      (168) 0x43c68c LDUR	X13, [X29, #400]

      (168) 0x43c690 LDR	X19, [X13]

      (168) 0x43c694 LDUR	X13, [X29, #440]

      (168) 0x43c698 LDR	X20, [X13]

      (168) 0x43c69c B	43c6b4

        (180) 0x43c6a0 LDUR	X17, [X29, #424]

        (180) 0x43c6a4 LDR	X13, [X11, X9,LSL #3]

        (180) 0x43c6a8 ADD	X8, X8, #1

        (180) 0x43c6ac CMP	X8, X13

        (180) 0x43c6b0 B.GE	43c84c

        (180) 0x43c6b4 LDR	X13, [X12, X8,LSL #3]

        (180) 0x43c6b8 LDR	X15, [X10, X13,LSL #3]

        (180) 0x43c6bc TBNZ	X15, #63, 43c6ec

        (180) 0x43c6c0 LDR	X15, [X22, X13,LSL #3]

        (180) 0x43c6c4 CMP	X15, X5

        (180) 0x43c6c8 B.GE	43c6a4

        (180) 0x43c6cc STR	X7, [X22, X13,LSL #3]

        (180) 0x43c6d0 LDR	X13, [X3, X13,LSL #3]

        (180) 0x43c6d4 STR	X13, [X19, X7,LSL #3]

        (180) 0x43c6d8 LDUR	X13, [X29, #496]

        (180) 0x43c6dc LDR	D2, [X13]

        (180) 0x43c6e0 STR	D2, [X20, X7,LSL #3]

        (180) 0x43c6e4 ADD	X7, X7, #1

        (180) 0x43c6e8 B	43c6a4

        (180) 0x43c6ec CMN	X15, #3

        (180) 0x43c6f0 B.EQ	43c6a4

        (180) 0x43c6f4 STR	X6, [X22, X13,LSL #3]

        (180) 0x43c6f8 ADD	X21, X13, #1

        (180) 0x43c6fc LDR	X15, [X11, X13,LSL #3]

        (180) 0x43c700 LDR	X30, [X11, X21,LSL #3]

        (180) 0x43c704 CMP	X15, X30

        (180) 0x43c708 B.GE	43c774

        (180) 0x43c70c LDUR	X17, [X29, #408]

        (180) 0x43c710 LDR	X18, [X17]

        (180) 0x43c714 LDUR	X17, [X29, #400]

        (180) 0x43c718 LDR	X26, [X17]

        (180) 0x43c71c LDUR	X17, [X29, #440]

        (180) 0x43c720 LDR	X0, [X17]

        (180) 0x43c724 B	43c734

          (183) 0x43c728 ADD	X15, X15, #1

          (183) 0x43c72c CMP	X15, X30

          (183) 0x43c730 B.GE	43c770

          (183) 0x43c734 LDR	X17, [X12, X15,LSL #3]

          (183) 0x43c738 LDR	X25, [X10, X17,LSL #3]

          (183) 0x43c73c TBNZ	X25, #63, 43c728

          (183) 0x43c740 LDR	X25, [X22, X17,LSL #3]

          (183) 0x43c744 CMP	X25, X5

          (183) 0x43c748 B.GE	43c728

          (183) 0x43c74c STR	X7, [X22, X17,LSL #3]

          (183) 0x43c750 LDR	X17, [X18, X17,LSL #3]

          (183) 0x43c754 STR	X17, [X26, X7,LSL #3]

          (183) 0x43c758 LDUR	X17, [X29, #496]

          (183) 0x43c75c LDR	D2, [X17]

          (183) 0x43c760 LDR	X30, [X11, X21,LSL #3]

          (183) 0x43c764 STR	D2, [X0, X7,LSL #3]

          (183) 0x43c768 ADD	X7, X7, #1

          (183) 0x43c76c B	43c728

        (180) 0x43c770 LDUR	X17, [X29, #424]

        (180) 0x43c774 LDUR	X15, [X29, #488]

        (180) 0x43c778 LDR	X15, [X15]

        (180) 0x43c77c CMP	X15, #2

        (180) 0x43c780 B.LT	43c6a4

        (180) 0x43c784 LDR	X26, [X14, X13,LSL #3]

        (180) 0x43c788 LDR	X15, [X14, X21,LSL #3]

        (180) 0x43c78c CMP	X26, X15

        (180) 0x43c790 B.GE	43c6a0

        (180) 0x43c794 LDUR	X13, [X29, #344]

        (180) 0x43c798 LDUR	X17, [X29, #416]

        (180) 0x43c79c LDR	X30, [X13]

        (180) 0x43c7a0 LDUR	X13, [X29, #336]

        (180) 0x43c7a4 LDR	X18, [X17]

        (180) 0x43c7a8 LDR	X13, [X13]

        (180) 0x43c7ac CBNZ	X16, 43c7cc

        (180) 0x43c7b0 B	43c814

0x43c7b4 HINT	#0

0x43c7b8 HINT	#0

0x43c7bc HINT	#0

          (181) 0x43c7c0 ADD	X26, X26, #1

          (181) 0x43c7c4 CMP	X26, X15

          (181) 0x43c7c8 B.GE	43c6a0

          (181) 0x43c7cc LDR	X17, [X30, X26,LSL #3]

          (181) 0x43c7d0 LDR	X17, [X16, X17,LSL #3]

          (181) 0x43c7d4 LDR	X0, [X2, X17,LSL #3]

          (181) 0x43c7d8 TBNZ	X0, #63, 43c7c0

          (181) 0x43c7dc LDR	X0, [X23, X17,LSL #3]

          (181) 0x43c7e0 CMP	X0, X1

          (181) 0x43c7e4 B.GE	43c7c0

          (181) 0x43c7e8 LDUR	X15, [X29, #496]

          (181) 0x43c7ec STR	X4, [X23, X17,LSL #3]

          (181) 0x43c7f0 STR	X17, [X13, X4,LSL #3]

          (181) 0x43c7f4 LDR	D2, [X15]

          (181) 0x43c7f8 LDR	X15, [X14, X21,LSL #3]

          (181) 0x43c7fc STR	D2, [X18, X4,LSL #3]

          (181) 0x43c800 ADD	X4, X4, #1

          (181) 0x43c804 B	43c7c0

          (182) 0x43c808 ADD	X26, X26, #1

          (182) 0x43c80c CMP	X26, X15

          (182) 0x43c810 B.GE	43c6a0

          (182) 0x43c814 LDR	X17, [X30, X26,LSL #3]

          (182) 0x43c818 LDR	X0, [X2, X17,LSL #3]

          (182) 0x43c81c TBNZ	X0, #63, 43c808

          (182) 0x43c820 LDR	X0, [X23, X17,LSL #3]

          (182) 0x43c824 CMP	X0, X1

          (182) 0x43c828 B.GE	43c808

          (182) 0x43c82c LDUR	X15, [X29, #496]

          (182) 0x43c830 STR	X4, [X23, X17,LSL #3]

          (182) 0x43c834 STR	X17, [X13, X4,LSL #3]

          (182) 0x43c838 LDR	D2, [X15]

          (182) 0x43c83c LDR	X15, [X14, X21,LSL #3]

          (182) 0x43c840 STR	D2, [X18, X4,LSL #3]

          (182) 0x43c844 ADD	X4, X4, #1

          (182) 0x43c848 B	43c808

      (168) 0x43c84c LDUR	X0, [X29, #448]

      (168) 0x43c850 LDUR	X8, [X29, #488]

      (168) 0x43c854 LDR	X8, [X8]

      (168) 0x43c858 CMP	X8, #2

      (168) 0x43c85c B.LT	43c9d0

      (168) 0x43c860 LDUR	X13, [X29, #480]

      (168) 0x43c864 LDR	X8, [X13, X27,LSL #3]

      (168) 0x43c868 LDR	X13, [X13, X9,LSL #3]

      (168) 0x43c86c CMP	X8, X13

      (168) 0x43c870 B.GE	43c9d0

      (168) 0x43c874 LDR	X13, [SP, #128]

      (168) 0x43c878 LDR	X14, [X13]

      (168) 0x43c87c LDR	X13, [SP, #136]

      (168) 0x43c880 LDR	X16, [X13]

      (168) 0x43c884 LDUR	X13, [X29, #336]

      (168) 0x43c888 ADD	X19, X14, #8

      (168) 0x43c88c LDR	X2, [X13]

      (168) 0x43c890 LDUR	X13, [X29, #416]

      (168) 0x43c894 LDR	X3, [X13]

      (168) 0x43c898 B	43c8b4

        (178) 0x43c89c LDUR	X17, [X29, #424]

        (178) 0x43c8a0 LDUR	X13, [X29, #480]

        (178) 0x43c8a4 ADD	X8, X8, #1

        (178) 0x43c8a8 LDR	X13, [X13, X9,LSL #3]

        (178) 0x43c8ac CMP	X8, X13

        (178) 0x43c8b0 B.GE	43c9cc

        (178) 0x43c8b4 LDUR	X13, [X29, #472]

        (178) 0x43c8b8 LDR	X20, [X13, X8,LSL #3]

        (178) 0x43c8bc CBZ	X17, 43c8c4

        (178) 0x43c8c0 LDR	X20, [X17, X20,LSL #3]

        (178) 0x43c8c4 LDUR	X13, [X29, #464]

        (178) 0x43c8c8 LDR	X13, [X13, X20,LSL #3]

        (178) 0x43c8cc TBNZ	X13, #63, 43c900

        (178) 0x43c8d0 LDR	X13, [X23, X20,LSL #3]

        (178) 0x43c8d4 CMP	X13, X1

        (178) 0x43c8d8 B.GE	43c8a0

        (178) 0x43c8dc LDUR	X13, [X29, #496]

        (178) 0x43c8e0 STR	X4, [X23, X20,LSL #3]

        (178) 0x43c8e4 STR	X20, [X2, X4,LSL #3]

        (178) 0x43c8e8 LDR	D2, [X13]

        (178) 0x43c8ec STR	D2, [X3, X4,LSL #3]

        (178) 0x43c8f0 ADD	X4, X4, #1

        (178) 0x43c8f4 B	43c8a0

0x43c8f8 HINT	#0

0x43c8fc HINT	#0

        (178) 0x43c900 CMN	X13, #3

        (178) 0x43c904 B.EQ	43c8a0

        (178) 0x43c908 STR	X6, [X23, X20,LSL #3]

        (178) 0x43c90c LDR	X13, [X14, X20,LSL #3]

        (178) 0x43c910 LDR	X15, [X19, X20,LSL #3]

        (178) 0x43c914 CMP	X13, X15

        (178) 0x43c918 B.GE	43c8a0

        (178) 0x43c91c LDUR	X17, [X29, #416]

        (178) 0x43c920 LDUR	X15, [X29, #336]

        (178) 0x43c924 LDR	X18, [X17]

        (178) 0x43c928 LDUR	X17, [X29, #408]

        (178) 0x43c92c LDR	X15, [X15]

        (178) 0x43c930 LDR	X21, [X17]

        (178) 0x43c934 LDUR	X17, [X29, #400]

        (178) 0x43c938 LDR	X26, [X17]

        (178) 0x43c93c LDUR	X17, [X29, #440]

        (178) 0x43c940 LDR	X30, [X17]

        (178) 0x43c944 B	43c958

          (179) 0x43c948 LDR	X17, [X19, X20,LSL #3]

          (179) 0x43c94c ADD	X13, X13, #1

          (179) 0x43c950 CMP	X13, X17

          (179) 0x43c954 B.GE	43c89c

          (179) 0x43c958 LDR	X17, [X16, X13,LSL #3]

          (179) 0x43c95c LDR	X0, [X28]

          (179) 0x43c960 LDR	X25, [X24]

          (179) 0x43c964 SUBS	X0, X17, X0

          (179) 0x43c968 CCMP	X17, X25, #0, #10

          (179) 0x43c96c B.LT	43c9a0

          (179) 0x43c970 ORN	X17, XZR, X17

          (179) 0x43c974 LDR	X0, [X23, X17,LSL #3]

          (179) 0x43c978 CMP	X0, X1

          (179) 0x43c97c B.GE	43c948

          (179) 0x43c980 STR	X4, [X23, X17,LSL #3]

          (179) 0x43c984 STR	X17, [X15, X4,LSL #3]

          (179) 0x43c988 LDUR	X17, [X29, #496]

          (179) 0x43c98c LDR	D2, [X17]

          (179) 0x43c990 STR	D2, [X18, X4,LSL #3]

          (179) 0x43c994 ADD	X4, X4, #1

          (179) 0x43c998 B	43c948

0x43c99c HINT	#0

          (179) 0x43c9a0 LDR	X17, [X22, X0,LSL #3]

          (179) 0x43c9a4 CMP	X17, X5

          (179) 0x43c9a8 B.GE	43c948

          (179) 0x43c9ac STR	X7, [X22, X0,LSL #3]

          (179) 0x43c9b0 LDR	X17, [X21, X0,LSL #3]

          (179) 0x43c9b4 STR	X17, [X26, X7,LSL #3]

          (179) 0x43c9b8 LDUR	X17, [X29, #496]

          (179) 0x43c9bc LDR	D2, [X17]

          (179) 0x43c9c0 STR	D2, [X30, X7,LSL #3]

          (179) 0x43c9c4 ADD	X7, X7, #1

          (179) 0x43c9c8 B	43c948

      (168) 0x43c9cc LDUR	X0, [X29, #448]

      (168) 0x43c9d0 LDUR	X14, [X29, #432]

      (168) 0x43c9d4 LDUR	X13, [X29, #456]

      (168) 0x43c9d8 LDR	X8, [X14, X27,LSL #3]

      (168) 0x43c9dc LDR	X19, [X14, X9,LSL #3]

      (168) 0x43c9e0 LDR	D2, [X13, X8,LSL #3]

      (168) 0x43c9e4 ADD	X3, X8, #1

      (168) 0x43c9e8 CMP	X3, X19

      (168) 0x43c9ec B.GE	43ce8c

      (168) 0x43c9f0 LDR	X13, [SP, #160]

      (168) 0x43c9f4 LDUR	X8, [X29, #440]

      (168) 0x43c9f8 LDR	X25, [X13]

      (168) 0x43c9fc LDR	X13, [SP, #168]

      (168) 0x43ca00 LDR	X8, [X8]

      (168) 0x43ca04 LDR	X13, [X13]

      (168) 0x43ca08 STUR	X13, [X29, #296]

      (168) 0x43ca0c LDUR	X13, [X29, #488]

      (168) 0x43ca10 LDR	X30, [X13]

      (168) 0x43ca14 LDR	X13, [SP, #144]

      (168) 0x43ca18 LDR	X26, [X13]

      (168) 0x43ca1c LDR	X13, [SP, #152]

      (168) 0x43ca20 LDR	X13, [X13]

      (168) 0x43ca24 STR	X13, [SP, #216]

      (168) 0x43ca28 ADD	X13, X13, #8

      (168) 0x43ca2c STR	X13, [SP, #208]

      (168) 0x43ca30 LDUR	X17, [X29, #456]

      (168) 0x43ca34 B	43ca5c

0x43ca38 HINT	#0

0x43ca3c HINT	#0

        (173) 0x43ca40 LDR	D3, [X17, X3,LSL #3]

        (173) 0x43ca44 LDR	D4, [X8, X13,LSL #3]

        (173) 0x43ca48 FADD	D3, D3, D4

        (173) 0x43ca4c STR	D3, [X8, X13,LSL #3]

        (173) 0x43ca50 ADD	X3, X3, #1

        (173) 0x43ca54 CMP	X3, X19

        (173) 0x43ca58 B.EQ	43ceac

        (173) 0x43ca5c LDR	X21, [X0, X3,LSL #3]

        (173) 0x43ca60 LDR	X13, [X22, X21,LSL #3]

        (173) 0x43ca64 CMP	X13, X5

        (173) 0x43ca68 B.GE	43ca40

        (173) 0x43ca6c CMP	X13, X6

        (173) 0x43ca70 B.NE	43cac4

        (173) 0x43ca74 LDUR	X13, [X29, #496]

        (173) 0x43ca78 ADD	X14, X21, #1

        (173) 0x43ca7c LDR	D4, [X13]

        (173) 0x43ca80 LDUR	X13, [X29, #432]

        (173) 0x43ca84 LDR	X16, [X13, X21,LSL #3]

        (173) 0x43ca88 LDR	X20, [X13, X14,LSL #3]

        (173) 0x43ca8c LDR	D3, [X17, X16,LSL #3]

        (173) 0x43ca90 ADD	X2, X16, #1

        (173) 0x43ca94 FCMP	D3, #0

        (173) 0x43ca98 FCSEL	D3, D1, D0, #4

        (173) 0x43ca9c CMP	X2, X20

        (173) 0x43caa0 B.GE	43cbc8

        (173) 0x43caa4 ORN	W13, WZR, W16

        (173) 0x43caa8 ADD	W15, W20, W13

        (173) 0x43caac SUB	X13, X20, #2

        (173) 0x43cab0 TBNZ	W15, #0, 43caf8

        (173) 0x43cab4 ORR	X15, XZR, X2

        (173) 0x43cab8 CMP	X13, X16

        (173) 0x43cabc B.NE	43cb3c

        (173) 0x43cac0 B	43cbc8

        (173) 0x43cac4 LDR	X13, [X10, X21,LSL #3]

        (173) 0x43cac8 CMN	X13, #3

        (173) 0x43cacc B.EQ	43ca50

        (173) 0x43cad0 CMP	X25, #1

        (173) 0x43cad4 B.EQ	43caec

        (173) 0x43cad8 LDUR	X14, [X29, #296]

        (173) 0x43cadc LDR	X13, [X14, X27,LSL #3]

        (173) 0x43cae0 LDR	X14, [X14, X21,LSL #3]

        (173) 0x43cae4 CMP	X13, X14

        (173) 0x43cae8 B.NE	43ca50

        (173) 0x43caec LDR	D3, [X17, X3,LSL #3]

        (173) 0x43caf0 FADD	D2, D2, D3

        (173) 0x43caf4 B	43ca50

        (173) 0x43caf8 LDUR	X15, [X29, #448]

        (173) 0x43cafc LDR	X15, [X15, X2,LSL #3]

        (173) 0x43cb00 LDR	X17, [X22, X15,LSL #3]

        (173) 0x43cb04 CMP	X17, X5

        (173) 0x43cb08 CCMP	X15, X27, #4, #11

        (173) 0x43cb0c B.NE	43cb2c

        (173) 0x43cb10 LDUR	X17, [X29, #456]

        (173) 0x43cb14 LDR	D5, [X17, X2,LSL #3]

        (173) 0x43cb18 FMUL	D6, D3, D5

        (173) 0x43cb1c FCMP	D6, #0

        (173) 0x43cb20 B.PL	43cb30

        (173) 0x43cb24 FADD	D4, D4, D5

        (173) 0x43cb28 B	43cb30

        (173) 0x43cb2c LDUR	X17, [X29, #456]

        (173) 0x43cb30 ADD	X15, X16, #2

        (173) 0x43cb34 CMP	X13, X16

        (173) 0x43cb38 B.EQ	43cbc8

        (173) 0x43cb3c SUB	X13, X20, X15

        (173) 0x43cb40 UBFM	X17, X15, #61, #60

        (173) 0x43cb44 LDP	X18, X15, [X29, #880]

        (173) 0x43cb48 ADD	X15, X15, X17

        (173) 0x43cb4c ADD	X18, X18, X17

        (173) 0x43cb50 B	43cb70

0x43cb54 HINT	#0

0x43cb58 HINT	#0

0x43cb5c HINT	#0

          (177) 0x43cb60 SUBS	X13, X13, #2

          (177) 0x43cb64 ADD	X15, X15, #16

          (177) 0x43cb68 ADD	X18, X18, #16

          (177) 0x43cb6c B.EQ	43cbc4

          (177) 0x43cb70 LDUR	X17, [X15, #504]

          (177) 0x43cb74 LDR	X0, [X22, X17,LSL #3]

          (177) 0x43cb78 CMP	X0, X5

          (177) 0x43cb7c CCMP	X17, X27, #4, #11

          (177) 0x43cb80 B.NE	43cb98

          (177) 0x43cb84 LDUR	D5, [X18, #504]

          (177) 0x43cb88 FMUL	D6, D3, D5

          (177) 0x43cb8c FCMP	D6, #0

          (177) 0x43cb90 B.PL	43cb98

          (177) 0x43cb94 FADD	D4, D4, D5

          (177) 0x43cb98 LDR	X17, [X15]

          (177) 0x43cb9c LDR	X0, [X22, X17,LSL #3]

          (177) 0x43cba0 CMP	X0, X5

          (177) 0x43cba4 CCMP	X17, X27, #4, #11

          (177) 0x43cba8 B.NE	43cb60

          (177) 0x43cbac LDR	D5, [X18]

          (177) 0x43cbb0 FMUL	D6, D3, D5

          (177) 0x43cbb4 FCMP	D6, #0

          (177) 0x43cbb8 B.PL	43cb60

          (177) 0x43cbbc FADD	D4, D4, D5

          (177) 0x43cbc0 B	43cb60

        (173) 0x43cbc4 LDUR	X17, [X29, #456]

        (173) 0x43cbc8 CMP	X30, #2

        (173) 0x43cbcc B.LT	43cc04

        (173) 0x43cbd0 LDR	X18, [X26, X21,LSL #3]

        (173) 0x43cbd4 LDR	X13, [X26, X14,LSL #3]

        (173) 0x43cbd8 CMP	X13, X18

        (173) 0x43cbdc B.LE	43cc04

        (173) 0x43cbe0 LDUR	X15, [X29, #352]

        (173) 0x43cbe4 SUB	W17, W13, W18

        (173) 0x43cbe8 LDR	X15, [X15]

        (173) 0x43cbec TBNZ	W17, #0, 43cce8

        (173) 0x43cbf0 ORR	X0, XZR, X18

        (173) 0x43cbf4 ADD	X17, X18, #1

        (173) 0x43cbf8 CMP	X13, X17

        (173) 0x43cbfc LDUR	X17, [X29, #456]

        (173) 0x43cc00 B.NE	43cd24

        (173) 0x43cc04 LDR	D5, [X17, X3,LSL #3]

        (173) 0x43cc08 FCMP	D4, #0

        (173) 0x43cc0c B.EQ	43cdac

        (173) 0x43cc10 FDIV	D4, D5, D4

        (173) 0x43cc14 CMP	X2, X20

        (173) 0x43cc18 B.GE	43cca0

        (173) 0x43cc1c LDUR	X13, [X29, #440]

        (173) 0x43cc20 LDP	X15, X18, [X29, #880]

        (173) 0x43cc24 UBFM	X17, X16, #61, #60

        (173) 0x43cc28 ORN	X16, XZR, X16

        (173) 0x43cc2c ADD	X16, X16, X20

        (173) 0x43cc30 LDR	X13, [X13]

        (173) 0x43cc34 ADD	X15, X15, X17

        (173) 0x43cc38 ADD	X18, X18, X17

        (173) 0x43cc3c B	43cc50

          (175) 0x43cc40 ADD	X15, X15, #8

          (175) 0x43cc44 SUBS	X16, X16, #1

          (175) 0x43cc48 ADD	X18, X18, #8

          (175) 0x43cc4c B.EQ	43cc9c

          (175) 0x43cc50 LDR	X0, [X18]

          (175) 0x43cc54 LDR	X2, [X22, X0,LSL #3]

          (175) 0x43cc58 CMP	X2, X5

          (175) 0x43cc5c B.LT	43cc7c

          (175) 0x43cc60 LDR	D5, [X15]

          (175) 0x43cc64 FMUL	D6, D3, D5

          (175) 0x43cc68 FCMP	D6, #0

          (175) 0x43cc6c B.PL	43cc7c

          (175) 0x43cc70 LDR	D6, [X13, X2,LSL #3]

          (175) 0x43cc74 FMADD	D5, D4, D5, D6

          (175) 0x43cc78 STR	D5, [X13, X2,LSL #3]

          (175) 0x43cc7c CMP	X0, X27

          (175) 0x43cc80 B.NE	43cc40

          (175) 0x43cc84 LDR	D5, [X15]

          (175) 0x43cc88 FMUL	D6, D3, D5

          (175) 0x43cc8c FCMP	D6, #0

          (175) 0x43cc90 B.PL	43cc40

          (175) 0x43cc94 FMADD	D2, D4, D5, D2

          (175) 0x43cc98 B	43cc40

        (173) 0x43cc9c LDUR	X17, [X29, #456]

        (173) 0x43cca0 LDUR	X0, [X29, #448]

        (173) 0x43cca4 CMP	X30, #2

        (173) 0x43cca8 B.LT	43ca50

        (173) 0x43ccac LDR	X15, [X26, X21,LSL #3]

        (173) 0x43ccb0 LDR	X14, [X26, X14,LSL #3]

        (173) 0x43ccb4 CMP	X14, X15

        (173) 0x43ccb8 B.LE	43ca50

        (173) 0x43ccbc LDUR	X13, [X29, #352]

        (173) 0x43ccc0 SUB	W17, W14, W15

        (173) 0x43ccc4 LDR	X16, [X13]

        (173) 0x43ccc8 LDUR	X13, [X29, #416]

        (173) 0x43cccc LDR	X13, [X13]

        (173) 0x43ccd0 TBNZ	W17, #0, 43cdb8

        (173) 0x43ccd4 ORR	X18, XZR, X15

        (173) 0x43ccd8 ADD	X15, X15, #1

        (173) 0x43ccdc CMP	X14, X15

        (173) 0x43cce0 B.EQ	43cdf8

        (173) 0x43cce4 B	43ce00

        (173) 0x43cce8 LDR	X17, [SP, #216]

        (173) 0x43ccec LDR	X17, [X17, X18,LSL #3]

        (173) 0x43ccf0 LDR	X17, [X23, X17,LSL #3]

        (173) 0x43ccf4 CMP	X17, X1

        (173) 0x43ccf8 B.LT	43cd10

        (173) 0x43ccfc LDR	D5, [X15, X18,LSL #3]

        (173) 0x43cd00 FMUL	D6, D3, D5

        (173) 0x43cd04 FCMP	D6, #0

        (173) 0x43cd08 B.PL	43cd10

        (173) 0x43cd0c FADD	D4, D4, D5

        (173) 0x43cd10 ADD	X0, X18, #1

        (173) 0x43cd14 ADD	X17, X18, #1

        (173) 0x43cd18 CMP	X13, X17

        (173) 0x43cd1c LDUR	X17, [X29, #456]

        (173) 0x43cd20 B.EQ	43cc04

        (173) 0x43cd24 LDR	X18, [SP, #208]

        (173) 0x43cd28 UBFM	X17, X0, #61, #60

        (173) 0x43cd2c SUB	X13, X13, X0

        (173) 0x43cd30 ADD	X15, X15, X17

        (173) 0x43cd34 ADD	X15, X15, #8

        (173) 0x43cd38 ADD	X18, X18, X17

        (173) 0x43cd3c B	43cd50

          (176) 0x43cd40 SUBS	X13, X13, #2

          (176) 0x43cd44 ADD	X15, X15, #16

          (176) 0x43cd48 ADD	X18, X18, #16

          (176) 0x43cd4c B.EQ	43cd9c

          (176) 0x43cd50 LDUR	X17, [X18, #504]

          (176) 0x43cd54 LDR	X17, [X23, X17,LSL #3]

          (176) 0x43cd58 CMP	X17, X1

          (176) 0x43cd5c B.LT	43cd74

          (176) 0x43cd60 LDUR	D5, [X15, #504]

          (176) 0x43cd64 FMUL	D6, D3, D5

          (176) 0x43cd68 FCMP	D6, #0

          (176) 0x43cd6c B.PL	43cd74

          (176) 0x43cd70 FADD	D4, D4, D5

          (176) 0x43cd74 LDR	X17, [X18]

          (176) 0x43cd78 LDR	X17, [X23, X17,LSL #3]

          (176) 0x43cd7c CMP	X17, X1

          (176) 0x43cd80 B.LT	43cd40

          (176) 0x43cd84 LDR	D5, [X15]

          (176) 0x43cd88 FMUL	D6, D3, D5

          (176) 0x43cd8c FCMP	D6, #0

          (176) 0x43cd90 B.PL	43cd40

          (176) 0x43cd94 FADD	D4, D4, D5

          (176) 0x43cd98 B	43cd40

        (173) 0x43cd9c LDUR	X17, [X29, #456]

        (173) 0x43cda0 LDR	D5, [X17, X3,LSL #3]

        (173) 0x43cda4 FCMP	D4, #0

        (173) 0x43cda8 B.NE	43cc10

        (173) 0x43cdac LDUR	X0, [X29, #448]

        (173) 0x43cdb0 FADD	D2, D2, D5

        (173) 0x43cdb4 B	43ca50

        (173) 0x43cdb8 LDR	X17, [SP, #216]

        (173) 0x43cdbc LDR	X17, [X17, X15,LSL #3]

        (173) 0x43cdc0 LDR	X18, [X23, X17,LSL #3]

        (173) 0x43cdc4 CMP	X18, X1

        (173) 0x43cdc8 B.LT	43cde8

        (173) 0x43cdcc LDR	D5, [X16, X15,LSL #3]

        (173) 0x43cdd0 FMUL	D6, D3, D5

        (173) 0x43cdd4 FCMP	D6, #0

        (173) 0x43cdd8 B.PL	43cde8

        (173) 0x43cddc LDR	D6, [X13, X18,LSL #3]

        (173) 0x43cde0 FMADD	D5, D4, D5, D6

        (173) 0x43cde4 STR	D5, [X13, X18,LSL #3]

        (173) 0x43cde8 ADD	X18, X15, #1

        (173) 0x43cdec ADD	X15, X15, #1

        (173) 0x43cdf0 CMP	X14, X15

        (173) 0x43cdf4 B.NE	43ce00

        (173) 0x43cdf8 LDUR	X17, [X29, #456]

        (173) 0x43cdfc B	43ca50

        (173) 0x43ce00 UBFM	X17, X18, #61, #60

        (173) 0x43ce04 SUB	X14, X14, X18

        (173) 0x43ce08 ADD	X15, X16, X17

        (173) 0x43ce0c LDR	X16, [SP, #208]

        (173) 0x43ce10 ADD	X15, X15, #8

        (173) 0x43ce14 ADD	X16, X16, X17

        (173) 0x43ce18 B	43ce30

0x43ce1c HINT	#0

          (174) 0x43ce20 SUBS	X14, X14, #2

          (174) 0x43ce24 ADD	X15, X15, #16

          (174) 0x43ce28 ADD	X16, X16, #16

          (174) 0x43ce2c B.EQ	43cdf8

          (174) 0x43ce30 LDUR	X17, [X16, #504]

          (174) 0x43ce34 LDR	X18, [X23, X17,LSL #3]

          (174) 0x43ce38 CMP	X18, X1

          (174) 0x43ce3c B.LT	43ce5c

          (174) 0x43ce40 LDUR	D5, [X15, #504]

          (174) 0x43ce44 FMUL	D6, D3, D5

          (174) 0x43ce48 FCMP	D6, #0

          (174) 0x43ce4c B.PL	43ce5c

          (174) 0x43ce50 LDR	D6, [X13, X18,LSL #3]

          (174) 0x43ce54 FMADD	D5, D4, D5, D6

          (174) 0x43ce58 STR	D5, [X13, X18,LSL #3]

          (174) 0x43ce5c LDR	X17, [X16]

          (174) 0x43ce60 LDR	X18, [X23, X17,LSL #3]

          (174) 0x43ce64 CMP	X18, X1

          (174) 0x43ce68 B.LT	43ce20

          (174) 0x43ce6c LDR	D5, [X15]

          (174) 0x43ce70 FMUL	D6, D3, D5

          (174) 0x43ce74 FCMP	D6, #0

          (174) 0x43ce78 B.PL	43ce20

          (174) 0x43ce7c LDR	D6, [X13, X18,LSL #3]

          (174) 0x43ce80 FMADD	D5, D4, D5, D6

          (174) 0x43ce84 STR	D5, [X13, X18,LSL #3]

          (174) 0x43ce88 B	43ce20

      (168) 0x43ce8c LDUR	X19, [X29, #360]

      (168) 0x43ce90 LDUR	X8, [X29, #488]

      (168) 0x43ce94 LDUR	X18, [X29, #392]

      (168) 0x43ce98 CNTW	X3, ALL

      (168) 0x43ce9c LDR	X8, [X8]

      (168) 0x43cea0 CMP	X8, #2

      (168) 0x43cea4 B.GE	43cecc

      (168) 0x43cea8 B	43d118

      (168) 0x43ceac LDUR	X19, [X29, #360]

      (168) 0x43ceb0 LDUR	X17, [X29, #424]

      (168) 0x43ceb4 LDUR	X8, [X29, #488]

      (168) 0x43ceb8 LDUR	X18, [X29, #392]

      (168) 0x43cebc CNTW	X3, ALL

      (168) 0x43cec0 LDR	X8, [X8]

      (168) 0x43cec4 CMP	X8, #2

      (168) 0x43cec8 B.LT	43d118

      (168) 0x43cecc LDR	X13, [SP, #112]

      (168) 0x43ced0 LDR	X8, [X13, X27,LSL #3]

      (168) 0x43ced4 LDR	X9, [X13, X9,LSL #3]

      (168) 0x43ced8 CMP	X8, X9

      (168) 0x43cedc B.GE	43d118

    (169) 0x43cee0 LDUR	X13, [X29, #352]

    (169) 0x43cee4 LDR	X30, [X28]

    (169) 0x43cee8 LDR	X14, [X13]

    (169) 0x43ceec LDUR	X13, [X29, #416]

    (169) 0x43cef0 LDR	X16, [X13]

    (169) 0x43cef4 LDUR	X13, [X29, #328]

    (169) 0x43cef8 LDR	X2, [X13]

    (169) 0x43cefc LDR	X13, [SP, #160]

    (169) 0x43cf00 LDR	X13, [X13]

    (169) 0x43cf04 STUR	X13, [X29, #296]

    (169) 0x43cf08 LDR	X13, [SP, #168]

    (169) 0x43cf0c LDR	X15, [X13]

    (169) 0x43cf10 LDR	X13, [SP, #104]

    (169) 0x43cf14 LDR	X13, [X13]

    (169) 0x43cf18 STP	X13, X15, [SP, #208]

    (169) 0x43cf1c LDR	X13, [SP, #88]

    (169) 0x43cf20 LDR	X21, [X13]

    (169) 0x43cf24 LDR	X13, [SP, #96]

    (169) 0x43cf28 LDR	X26, [X13]

    (169) 0x43cf2c ADD	X19, X21, #8

    (169) 0x43cf30 B	43cf5c

0x43cf34 HINT	#0

0x43cf38 HINT	#0

0x43cf3c HINT	#0

    (169) 0x43cf40 LDR	D3, [X14, X8,LSL #3]

    (169) 0x43cf44 LDR	D4, [X16, X15,LSL #3]

    (169) 0x43cf48 FADD	D3, D3, D4

    (169) 0x43cf4c STR	D3, [X16, X15,LSL #3]

    (169) 0x43cf50 ADD	X8, X8, #1

    (169) 0x43cf54 CMP	X8, X9

    (169) 0x43cf58 B.EQ	43d10c

    (169) 0x43cf5c LDR	X13, [X18, X8,LSL #3]

    (169) 0x43cf60 LDR	X15, [X23, X13,LSL #3]

    (169) 0x43cf64 CMP	X15, X1

    (169) 0x43cf68 B.GE	43cf40

    (169) 0x43cf6c CMP	X15, X6

    (169) 0x43cf70 B.NE	43d000

  (170) 0x43cf74 LDUR	X15, [X29, #496]

  (170) 0x43cf78 LDR	X3, [X21, X13,LSL #3]

  (170) 0x43cf7c LDR	X20, [X19, X13,LSL #3]

  (170) 0x43cf80 CMP	X3, X20

  (170) 0x43cf84 LDR	D3, [X15]

  (170) 0x43cf88 B.GE	43d038

  (170) 0x43cf8c LDR	X15, [SP, #224]

  (170) 0x43cf90 LDR	X13, [X24]

  (170) 0x43cf94 LDR	X18, [X15]

  (170) 0x43cf98 ORR	X15, XZR, X3

  (170) 0x43cf9c B	43cfb4

    (172) 0x43cfa0 LDR	D4, [X18, X15,LSL #3]

    (172) 0x43cfa4 FADD	D3, D3, D4

    (172) 0x43cfa8 ADD	X15, X15, #1

    (172) 0x43cfac CMP	X20, X15

    (172) 0x43cfb0 B.EQ	43d044

    (172) 0x43cfb4 LDR	X0, [X26, X15,LSL #3]

    (172) 0x43cfb8 SUBS	X17, X0, X30

    (172) 0x43cfbc CCMP	X0, X13, #0, #10

    (172) 0x43cfc0 B.LT	43cfe0

    (172) 0x43cfc4 ORN	X17, XZR, X0

    (172) 0x43cfc8 LDR	X17, [X23, X17,LSL #3]

    (172) 0x43cfcc CMP	X17, X1

    (172) 0x43cfd0 B.GE	43cfa0

    (172) 0x43cfd4 B	43cfa8

0x43cfd8 HINT	#0

0x43cfdc HINT	#0

    (172) 0x43cfe0 LDR	X0, [X22, X17,LSL #3]

    (172) 0x43cfe4 CMP	X0, X5

    (172) 0x43cfe8 CCMP	X17, X27, #4, #11

    (172) 0x43cfec B.EQ	43cfa0

    (172) 0x43cff0 B	43cfa8

0x43cff4 HINT	#0

0x43cff8 HINT	#0

0x43cffc HINT	#0

    (169) 0x43d000 LDR	X15, [X2, X13,LSL #3]

    (169) 0x43d004 CMN	X15, #3

    (169) 0x43d008 B.EQ	43cf50

    (169) 0x43d00c LDUR	X15, [X29, #296]

    (169) 0x43d010 CMP	X15, #1

    (169) 0x43d014 B.EQ	43d02c

    (169) 0x43d018 LDP	X17, X15, [SP, #208]

    (169) 0x43d01c LDR	X15, [X15, X27,LSL #3]

    (169) 0x43d020 LDR	X13, [X17, X13,LSL #3]

    (169) 0x43d024 CMP	X15, X13

    (169) 0x43d028 B.NE	43cf50

    (169) 0x43d02c LDR	D3, [X14, X8,LSL #3]

    (169) 0x43d030 FADD	D2, D2, D3

    (169) 0x43d034 B	43cf50

  (170) 0x43d038 FCMP	D3, #0

  (170) 0x43d03c B.NE	43d100

  (170) 0x43d040 B	43d0f8

  (170) 0x43d044 FCMP	D3, #0

  (170) 0x43d048 B.EQ	43d0f8

(171) 0x43d04c LDR	D4, [X14, X8,LSL #3]

(171) 0x43d050 LDUR	X13, [X29, #416]

(171) 0x43d054 LDUR	X15, [X29, #440]

(171) 0x43d058 UBFM	X17, X3, #61, #60

(171) 0x43d05c SUB	X20, X20, X3

(171) 0x43d060 ADD	X18, X18, X17

(171) 0x43d064 ADD	X3, X26, X17

(171) 0x43d068 LDR	X13, [X13]

(171) 0x43d06c LDR	X15, [X15]

(171) 0x43d070 FDIV	D3, D4, D3

(171) 0x43d074 B	43d090

0x43d078 HINT	#0

0x43d07c HINT	#0

(171) 0x43d080 ADD	X18, X18, #8

(171) 0x43d084 SUBS	X20, X20, #1

(171) 0x43d088 ADD	X3, X3, #8

(171) 0x43d08c B.EQ	43d100

(171) 0x43d090 LDR	X17, [X3]

(171) 0x43d094 LDR	X25, [X24]

(171) 0x43d098 SUBS	X0, X17, X30

(171) 0x43d09c CCMP	X17, X25, #0, #10

(171) 0x43d0a0 B.LT	43d0c8

(171) 0x43d0a4 ORN	X17, XZR, X17

(171) 0x43d0a8 LDR	X17, [X23, X17,LSL #3]

(171) 0x43d0ac CMP	X17, X1

(171) 0x43d0b0 B.LT	43d080

(171) 0x43d0b4 LDR	D4, [X18]

(171) 0x43d0b8 LDR	D5, [X13, X17,LSL #3]

(171) 0x43d0bc FMADD	D4, D3, D4, D5

(171) 0x43d0c0 STR	D4, [X13, X17,LSL #3]

(171) 0x43d0c4 B	43d080

(171) 0x43d0c8 LDR	X17, [X22, X0,LSL #3]

(171) 0x43d0cc CMP	X17, X5

(171) 0x43d0d0 B.LT	43d0e4

(171) 0x43d0d4 LDR	D4, [X18]

(171) 0x43d0d8 LDR	D5, [X15, X17,LSL #3]

(171) 0x43d0dc FMADD	D4, D3, D4, D5

(171) 0x43d0e0 STR	D4, [X15, X17,LSL #3]

(171) 0x43d0e4 CMP	X0, X27

(171) 0x43d0e8 B.NE	43d080

(171) 0x43d0ec LDR	D4, [X18]

(171) 0x43d0f0 FMADD	D2, D3, D4, D2

(171) 0x43d0f4 B	43d080

  (170) 0x43d0f8 LDR	D3, [X14, X8,LSL #3]

  (170) 0x43d0fc FADD	D2, D2, D3

  (170) 0x43d100 LDUR	X18, [X29, #392]

  (170) 0x43d104 CNTW	X3, ALL

  (170) 0x43d108 B	43cf50

    (169) 0x43d10c LDUR	X19, [X29, #360]

    (169) 0x43d110 LDUR	X17, [X29, #424]

    (169) 0x43d114 LDUR	X0, [X29, #448]

      (168) 0x43d118 FCMP	D2, #0

      (168) 0x43d11c B.EQ	43d254

      (168) 0x43d120 SUBS	X9, X7, X5

      (168) 0x43d124 B.LE	43d1b4

      (168) 0x43d128 FNEG	D3, D2

      (168) 0x43d12c CMP	X9, X3

      (168) 0x43d130 B.CC	43d18c

      (168) 0x43d134 UDIV	X13, X9, X3

      (168) 0x43d138 LDUR	X18, [X29, #304]

      (168) 0x43d13c UBFM	X16, X5, #61, #60

      (168) 0x43d140 ORR	X8, XZR, XZR

      (168) 0x43d144 DUP	Z4.D, Z3.D[0]

      (168) 0x43d148 ADD	X15, X18, X16

      (168) 0x43d14c ADDVL	X16, X16, #1

      (168) 0x43d150 ADD	X16, X18, X16

      (168) 0x43d154 MADD	X13, X13, X3, XZR

      (168) 0x43d158 SUB	X9, X9, X13

      (168) 0x43d15c ADD	X14, X5, X13

        (187) 0x43d160 LD1D	{Z5.D}, P0/Z, [X15, X8,LSL #3]

        (187) 0x43d164 LD1D	{Z6.D}, P0/Z, [X16, X8,LSL #3]

        (187) 0x43d168 FDIV	Z5.D, P0/M, Z5.D, Z4.D

        (187) 0x43d16c FDIV	Z6.D, P0/M, Z6.D, Z4.D

        (187) 0x43d170 ST1D	{Z5.D}, P0, [X15, X8,LSL #3]

        (187) 0x43d174 ST1D	{Z6.D}, P0, [X16, X8,LSL #3]

        (187) 0x43d178 ADD	X8, X8, X3

        (187) 0x43d17c CMP	X13, X8

        (187) 0x43d180 B.NE	43d160

      (168) 0x43d184 ORR	X5, XZR, X14

      (168) 0x43d188 CBZ	X9, 43d1b4

      (168) 0x43d18c LDUR	X9, [X29, #304]

      (168) 0x43d190 SUB	X8, X7, X5

      (168) 0x43d194 ADD	X9, X9, X5,LSL #3

      (168) 0x43d198 HINT	#0

      (168) 0x43d19c HINT	#0

        (186) 0x43d1a0 LDR	D4, [X9]

        (186) 0x43d1a4 SUBS	X8, X8, #1

        (186) 0x43d1a8 FDIV	D4, D4, D3

        (186) 0x43d1ac STR	D4, [X9], #8

        (186) 0x43d1b0 B.NE	43d1a0

      (168) 0x43d1b4 SUBS	X9, X4, X1

      (168) 0x43d1b8 B.LE	43d254

      (168) 0x43d1bc FNEG	D2, D2

      (168) 0x43d1c0 CMP	X9, X3

      (168) 0x43d1c4 B.CC	43d22c

      (168) 0x43d1c8 UDIV	X13, X9, X3

      (168) 0x43d1cc LDR	X18, [SP, #80]

      (168) 0x43d1d0 UBFM	X16, X1, #61, #60

      (168) 0x43d1d4 ORR	X8, XZR, XZR

      (168) 0x43d1d8 DUP	Z3.D, Z2.D[0]

      (168) 0x43d1dc ADD	X15, X18, X16

      (168) 0x43d1e0 ADDVL	X16, X16, #1

      (168) 0x43d1e4 ADD	X16, X18, X16

      (168) 0x43d1e8 MADD	X13, X13, X3, XZR

      (168) 0x43d1ec SUB	X9, X9, X13

      (168) 0x43d1f0 ADD	X14, X1, X13

      (168) 0x43d1f4 HINT	#0

      (168) 0x43d1f8 HINT	#0

      (168) 0x43d1fc HINT	#0

        (185) 0x43d200 LD1D	{Z4.D}, P0/Z, [X15, X8,LSL #3]

        (185) 0x43d204 LD1D	{Z5.D}, P0/Z, [X16, X8,LSL #3]

        (185) 0x43d208 FDIV	Z4.D, P0/M, Z4.D, Z3.D

        (185) 0x43d20c FDIV	Z5.D, P0/M, Z5.D, Z3.D

        (185) 0x43d210 ST1D	{Z4.D}, P0, [X15, X8,LSL #3]

        (185) 0x43d214 ST1D	{Z5.D}, P0, [X16, X8,LSL #3]

        (185) 0x43d218 ADD	X8, X8, X3

        (185) 0x43d21c CMP	X13, X8

        (185) 0x43d220 B.NE	43d200

      (168) 0x43d224 ORR	X1, XZR, X14

      (168) 0x43d228 CBZ	X9, 43d254

      (168) 0x43d22c LDR	X9, [SP, #80]

      (168) 0x43d230 SUB	X8, X4, X1

      (168) 0x43d234 ADD	X9, X9, X1,LSL #3

      (168) 0x43d238 HINT	#0

      (168) 0x43d23c HINT	#0

        (184) 0x43d240 LDR	D3, [X9]

        (184) 0x43d244 SUBS	X8, X8, #1

        (184) 0x43d248 FDIV	D3, D3, D2

        (184) 0x43d24c STR	D3, [X9], #8

        (184) 0x43d250 B.NE	43d240

      (168) 0x43d254 LDUR	X9, [X29, #288]

      (168) 0x43d258 LDUR	X13, [X29, #384]

      (168) 0x43d25c LDP	X16, X14, [SP, #184]

      (168) 0x43d260 LDUR	X15, [X29, #304]

      (168) 0x43d264 LDR	X18, [SP, #176]

      (168) 0x43d268 B	43c618

0x43d26c ADD	SP, SP, #464

0x43d270 LDP	X20, X19, [SP, #80]

0x43d274 LDP	X22, X21, [SP, #64]

0x43d278 LDP	X24, X23, [SP, #48]

0x43d27c LDP	X26, X25, [SP, #32]

0x43d280 LDP	X28, X27, [SP, #16]

0x43d284 LDP	X29, X30, [SP], #96

0x43d288 RET

0x43d28c HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	par_lr_interp.c:1196-1757
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1196,1221-1238,1244-1254,1262-1303,1311-1350,1363-1417,1423-1459,1467-1471,1480-1483,1491-1496,1503-1545,1553-1596,1607-1660,1667-1724,1730-1748,1754-1757.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 101.33 to 8.00 cycles (12.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 101.33 to 100.17 cycles (1.01x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 101.33 to 9.50 cycles (10.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary function is loading 1860 bytes. The binary function is storing 784 bytes.

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	580
loop length	2320
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

65.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	31.50	31.50	44.50	44.50	44.50	44.50	1.25	1.25	1.25	1.25	101.33	101.33	101.33	43.00	43.00
cycles	31.50	31.50	44.50	44.50	44.50	44.50	1.25	1.25	1.25	1.25	101.33	101.33	101.33	43.00	43.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-40.00

Cycles summary

Front-end	65.63
Overall L1	101.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 101.33 cycles. At this rate:

19% of peak load performance is reached (18.36 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (7.74 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 43b900

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB SP, SP, #464	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X7, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X6, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X5, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X0, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X25, X8, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X9, X26, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X9, X8, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X28, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X9, X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X8, X9, [X29, #832]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X3, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ X0, 43bab8 <.omp_outlined.+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 43bb18 <.omp_outlined.+0x218>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
B 43babc <.omp_outlined.+0x1bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X0, 43bb24 <.omp_outlined.+0x224>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 43bb2c <.omp_outlined.+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X11, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X19, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
B 43bb30 <.omp_outlined.+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X0, 43bac4 <.omp_outlined.+0x1c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X19, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 43bb30 <.omp_outlined.+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X19, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4b05e0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b05c0 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X9, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X20, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SDIV X10, X8, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MADD X27, X10, X20, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X10, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X26, [X29, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X26, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X20, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X10, X10, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X14, X8, X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X14, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STUR X14, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X28, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X0, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X25, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.GT 43bc98 <.omp_outlined.+0x398>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <4ecb88>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W28, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f900 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4ecbac>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1248	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X11, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X20, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X19, [X8, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X21, [X9, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X26, [X10, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X26, [X29, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X19, [X8, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X21, [X8, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR W21, WZR, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f900 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X19, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X12, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X20, 43c08c <.omp_outlined.+0x78c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUBS X8, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 43c08c <.omp_outlined.+0x78c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X12, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X10, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X11, X14, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X9, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W12, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X11, X15, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W13, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X10, X15, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.CC 43c048 <.omp_outlined.+0x748>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
TBNZ W12, #0, 43c048 <.omp_outlined.+0x748>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBNZ W13, 43c048 <.omp_outlined.+0x748>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X12, [X10], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X11], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X9], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 43c08c <.omp_outlined.+0x78c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X18, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X16, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X16, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X9, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X9, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X9, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X17, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 43bd24 <.omp_outlined.+0x424>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
ADD X11, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
ORR W1, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4ec090>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f900 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X4, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS X8, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 43c28c <.omp_outlined.+0x98c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUBS X9, X4, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 43c28c <.omp_outlined.+0x98c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X12, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CNTW X14, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ W15, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X11, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X14, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X17, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CSEL X15, X14, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X16, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ORR X15, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X16, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X17, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.CC 43c20c <.omp_outlined.+0x90c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X18, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X15, X27, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X12, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X13, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X18, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X12, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X13, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X16, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X17, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X1, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X10, X2, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W0, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X1, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X11, X2, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W18, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X15, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X10, X3, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W17, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X15, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDUR X4, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CCMP X11, X3, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W16, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X15, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ORR X15, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CCMP X1, X3, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.CC 43c20c <.omp_outlined.+0x90c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X15, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
TBNZ W0, #0, 43c20c <.omp_outlined.+0x90c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X15, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
TBNZ W18, #0, 43c20c <.omp_outlined.+0x90c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X15, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
TBNZ W17, #0, 43c20c <.omp_outlined.+0x90c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X15, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
TBNZ W16, #0, 43c20c <.omp_outlined.+0x90c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X15, X9, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
LDR X0, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X16, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LD1RD {Z0.D}, P0/Z, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z1.D}, P0/Z, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
MADD X0, X20, X0, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X0, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X2, X3, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X1, X13, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X12, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X13, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X12, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X18, X15, X14, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X17, X9, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X27, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X17, 43c248 <.omp_outlined.+0x948>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X14, X4, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X15, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X13, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X10, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X12, X20, X12, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X11, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 43c274 <.omp_outlined.+0x974>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4ec290>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1296	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f900 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBNZ X20, 43c46c <.omp_outlined.+0xb6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 43c2fc <.omp_outlined.+0x9fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b0670 <time_getWallclockSeconds>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <4b82bc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1777	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FSUB D0, D0, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D0, [X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4ae640 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f7d0 <@plt_start@+0x3e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 43c2fc <.omp_outlined.+0x9fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 4b0670 <time_getWallclockSeconds>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR D0, [X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X8, 43c360 <.omp_outlined.+0xa60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X0, 43c388 <.omp_outlined.+0xa88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 43c46c <.omp_outlined.+0xb6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 43c3e0 <.omp_outlined.+0xae0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
HINT #0
HINT #0
LDR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X19, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 47df40 <hypre_alt_insert_new_nodes>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X12, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X19, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 43c498 <.omp_outlined.+0xb98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
HINT #0
HINT #0
HINT #0
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 43c47c <.omp_outlined.+0xb7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 43c498 <.omp_outlined.+0xb98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 43c498 <.omp_outlined.+0xb98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 43c4c0 <.omp_outlined.+0xbc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4ec4c4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1320	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f900 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X13, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X13, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 43c51c <.omp_outlined.+0xc1c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X8, 43c4ec <.omp_outlined.+0xbec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae530 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X8, 43d26c <.omp_outlined.+0x196c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD SP, SP, #464	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 4ae530 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FMOV D0, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D1, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVN X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X8, X9, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X8, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X17, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X0, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X14, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X15, [X29, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X18, X16, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 43c628 <.omp_outlined.+0xd28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
ADD SP, SP, #464	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Source file and lines	par_lr_interp.c:1196-1757
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 101.33 to 9.50 cycles (10.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary function is loading 1860 bytes. The binary function is storing 784 bytes.

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	580
loop length	2320
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

65.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	31.50	31.50	44.50	44.50	44.50	44.50	1.25	1.25	1.25	1.25	101.33	101.33	101.33	43.00	43.00
cycles	31.50	31.50	44.50	44.50	44.50	44.50	1.25	1.25	1.25	1.25	101.33	101.33	101.33	43.00	43.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-40.00

Cycles summary

Front-end	65.63
Overall L1	101.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 101.33 cycles. At this rate:

19% of peak load performance is reached (18.36 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (7.74 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 43b900

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB SP, SP, #464	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X7, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X6, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X5, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X0, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X25, X8, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X9, X26, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X9, X8, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X28, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X9, X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X8, X9, [X29, #832]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X3, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ X0, 43bab8 <.omp_outlined.+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 43bb18 <.omp_outlined.+0x218>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
B 43babc <.omp_outlined.+0x1bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X0, 43bb24 <.omp_outlined.+0x224>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 43bb2c <.omp_outlined.+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X11, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X19, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
B 43bb30 <.omp_outlined.+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X0, 43bac4 <.omp_outlined.+0x1c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X19, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 43bb30 <.omp_outlined.+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X19, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4b05e0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b05c0 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X9, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X20, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SDIV X10, X8, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MADD X27, X10, X20, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X10, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X26, [X29, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X26, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X20, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X10, X10, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X14, X8, X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X14, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STUR X14, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X28, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X0, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X25, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.GT 43bc98 <.omp_outlined.+0x398>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <4ecb88>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W28, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f900 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4ecbac>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1248	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X11, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X20, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X19, [X8, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X21, [X9, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X26, [X10, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X26, [X29, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X19, [X8, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X21, [X8, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR W21, WZR, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f900 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X19, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X12, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X20, 43c08c <.omp_outlined.+0x78c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUBS X8, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 43c08c <.omp_outlined.+0x78c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X12, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X10, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X11, X14, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X9, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W12, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X11, X15, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W13, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X10, X15, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.CC 43c048 <.omp_outlined.+0x748>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
TBNZ W12, #0, 43c048 <.omp_outlined.+0x748>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBNZ W13, 43c048 <.omp_outlined.+0x748>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X12, [X10], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X11], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X9], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 43c08c <.omp_outlined.+0x78c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X18, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X16, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X16, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X9, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X9, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X9, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X17, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 43bd24 <.omp_outlined.+0x424>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
ADD X11, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
ORR W1, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4ec090>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f900 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X4, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS X8, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 43c28c <.omp_outlined.+0x98c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUBS X9, X4, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 43c28c <.omp_outlined.+0x98c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X12, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CNTW X14, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ W15, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X11, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X14, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X17, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CSEL X15, X14, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X16, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ORR X15, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X16, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X17, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.CC 43c20c <.omp_outlined.+0x90c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X18, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X15, X27, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X12, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X13, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X18, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X12, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X13, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X16, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X17, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X1, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X10, X2, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W0, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X1, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X11, X2, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W18, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X15, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X10, X3, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W17, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X15, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDUR X4, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CCMP X11, X3, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W16, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X15, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ORR X15, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CCMP X1, X3, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.CC 43c20c <.omp_outlined.+0x90c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X15, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
TBNZ W0, #0, 43c20c <.omp_outlined.+0x90c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X15, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
TBNZ W18, #0, 43c20c <.omp_outlined.+0x90c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X15, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
TBNZ W17, #0, 43c20c <.omp_outlined.+0x90c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X15, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
TBNZ W16, #0, 43c20c <.omp_outlined.+0x90c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X15, X9, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
LDR X0, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X16, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LD1RD {Z0.D}, P0/Z, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
LD1RD {Z1.D}, P0/Z, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
MADD X0, X20, X0, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X0, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X2, X3, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X1, X13, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X12, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X13, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X12, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X18, X15, X14, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X17, X9, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X27, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X17, 43c248 <.omp_outlined.+0x948>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X14, X4, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X15, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X13, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X10, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X12, X20, X12, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X11, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 43c274 <.omp_outlined.+0x974>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4ec290>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1296	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f900 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBNZ X20, 43c46c <.omp_outlined.+0xb6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 43c2fc <.omp_outlined.+0x9fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4b0670 <time_getWallclockSeconds>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <4b82bc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1777	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FSUB D0, D0, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D0, [X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4ae640 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f7d0 <@plt_start@+0x3e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 43c2fc <.omp_outlined.+0x9fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 4b0670 <time_getWallclockSeconds>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR D0, [X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X8, 43c360 <.omp_outlined.+0xa60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X0, 43c388 <.omp_outlined.+0xa88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4ae430 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 43c46c <.omp_outlined.+0xb6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 43c3e0 <.omp_outlined.+0xae0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
HINT #0
HINT #0
LDR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X19, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 47df40 <hypre_alt_insert_new_nodes>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X12, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X19, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 43c498 <.omp_outlined.+0xb98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
HINT #0
HINT #0
HINT #0
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 43c47c <.omp_outlined.+0xb7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 43c498 <.omp_outlined.+0xb98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 43c498 <.omp_outlined.+0xb98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 43c4c0 <.omp_outlined.+0xbc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4ec4c4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1320	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f900 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X13, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X13, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 43c51c <.omp_outlined.+0xc1c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X8, 43c4ec <.omp_outlined.+0xbec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4ae530 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X8, 43d26c <.omp_outlined.+0x196c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD SP, SP, #464	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 4ae530 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FMOV D0, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D1, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVN X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X8, X9, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X8, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X17, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X0, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X14, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X15, [X29, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X18, X16, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 43c628 <.omp_outlined.+0xd28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
ADD SP, SP, #464	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined.#0x43b900–	0.22	0.08
○Loop 205 - par_lr_interp.c:1230-1231 - exec	0	0
▼Loop 199 - par_lr_interp.c:1244-1350 - exec–	0	0
▼Loop 200 - par_lr_interp.c:1244-1350 - exec–	0	0
▼Loop 198 - par_lr_interp.c:1244-1340 - exec–	0	0
▼Loop 197 - par_lr_interp.c:1244-1313 - exec–	0	0
▼Loop 201 - par_lr_interp.c:1264-1303 - exec–	0.01	0.01
○Loop 204 - par_lr_interp.c:1277-1285 - exec	0.04	0.01
○Loop 202 - par_lr_interp.c:1291-1303 - exec	0	0
○Loop 203 - par_lr_interp.c:1291-1303 - exec	0	0
○Loop 188 - par_lr_interp.c:1458-1459 - exec	0	0
○Loop 196 - par_lr_interp.c:1378-1382 - exec	0	0
○Loop 206 - par_lr_interp.c:1224-1225 - exec	0	0.01
○Loop 195 - par_lr_interp.c:1378-1382 - exec	0	0
○Loop 193 - par_lr_interp.c:1400-1403 - exec	0	0
▼Loop 171 - par_lr_interp.c:1469-1748 - exec–	0	0
▼Loop 170 - par_lr_interp.c:1469-1748 - exec–	0	0
▼Loop 169 - par_lr_interp.c:1469-1748 - exec–	0	0
▼Loop 168 - par_lr_interp.c:1469-1748 - exec–	0	0
▼Loop 173 - par_lr_interp.c:1609-1675 - exec–	0.04	0.01
○Loop 177 - par_lr_interp.c:1624-1628 - exec	0.05	0.02
○Loop 175 - par_lr_interp.c:1644-1651 - exec	0.04	0.01
○Loop 176 - par_lr_interp.c:1632-1637 - exec	0	0
○Loop 174 - par_lr_interp.c:1655-1660 - exec	0	0
○Loop 186 - par_lr_interp.c:1742-1743 - exec	0	0
○Loop 185 - par_lr_interp.c:1745-1745 - exec	0	0
▼Loop 180 - par_lr_interp.c:1494-1545 - exec–	0	0.01
○Loop 183 - par_lr_interp.c:1516-1526 - exec	0.04	0.01
○Loop 181 - par_lr_interp.c:1532-1545 - exec	0	0
○Loop 182 - par_lr_interp.c:1532-1545 - exec	0	0
○Loop 184 - par_lr_interp.c:1744-1745 - exec	0	0
▼Loop 178 - par_lr_interp.c:1555-1596 - exec–	0	0
○Loop 179 - par_lr_interp.c:1573-1596 - exec	0	0
○Loop 187 - par_lr_interp.c:1743-1743 - exec	0	0
○Loop 167 - par_lr_interp.c:1469-1748 - exec	0	0
○Loop 172 - par_lr_interp.c:1688-1700 - exec	0	0
○Loop 194 - par_lr_interp.c:1393-1396 - exec	0	0
○Loop 192 - par_lr_interp.c:1393-1396 - exec	0	0
○Loop 190 - par_lr_interp.c:1451-1452 - exec	0	0
○Loop 189 - par_lr_interp.c:1455-1456 - exec	0	0
○Loop 191 - par_lr_interp.c:1444-1445 - exec	0	0

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ASM code

Code clean check

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Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code