OV - exec - Loop 967

	Loop Id: 967	Module: exec	Source: par_lr_interp.c:1624-1628	Coverage: 0.05%

0x4571b0 LDR	X9, [X15, X10,LSL #3]    [1]

0x4571b4 LDR	X1, [X19, X9,LSL #3]    [2]

0x4571b8 CMP	X0, X1

0x4571bc CCMP	X9, X21, #4, #12

0x4571c0 B.NE	4571d4

0x4571c4 LDR	D21, [X11, X10,LSL #3]    [3]

0x4571c8 FMUL	D22, D21, D7

0x4571cc FCMPE	D22, #0

0x4571d0 B.MI	457488

0x4571d4 ADD	X9, X10, #1

0x4571d8 LDR	X10, [X15, X9,LSL #3]    [4]

0x4571dc LDR	X17, [X19, X10,LSL #3]    [10]

0x4571e0 CMP	X0, X17

0x4571e4 CCMP	X10, X21, #4, #12

0x4571e8 B.NE	4571fc

0x4571ec LDR	D23, [X11, X9,LSL #3]    [9]

0x4571f0 FMUL	D24, D23, D7

0x4571f4 FCMPE	D24, #0

0x4571f8 B.MI	457498

0x4571fc ADD	X17, X9, #1

0x457200 LDR	X10, [X15, X17,LSL #3]    [12]

0x457204 LDR	X1, [X19, X10,LSL #3]    [11]

0x457208 CMP	X0, X1

0x45720c CCMP	X10, X21, #4, #12

0x457210 B.NE	457224

0x457214 LDR	D25, [X11, X17,LSL #3]    [7]

0x457218 FMUL	D26, D25, D7

0x45721c FCMPE	D26, #0

0x457220 B.MI	457490

0x457224 ADD	X17, X9, #2

0x457228 LDR	X10, [X15, X17,LSL #3]    [6]

0x45722c LDR	X1, [X19, X10,LSL #3]    [8]

0x457230 CMP	X0, X1

0x457234 CCMP	X10, X21, #4, #12

0x457238 B.NE	45724c

0x45723c LDR	D27, [X11, X17,LSL #3]    [5]

0x457240 FMUL	D28, D27, D7

0x457244 FCMPE	D28, #0

0x457248 B.MI	457480

0x45724c ADD	X10, X9, #3

0x457250 CMP	X10, X16

0x457254 B.NE	4571b0

0x457480 FADD	D2, D2, D27

0x457484 B	45724c

0x457488 FADD	D2, D2, D21

0x45748c B	4571d4

0x457490 FADD	D2, D2, D25

0x457494 B	457224

0x457498 FADD	D2, D2, D23

0x45749c B	4571fc

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c: 1624 - 1628

--------------------------------------------------------------------------------

1624:                for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++)

1625:                {

1626:                  i2 = A_diag_j[jj1];

1627:                  if((P_marker[i2] >= jj_begin_row || i2 == i) && (sgn*A_diag_data[jj1]) < 0)

1628:                    sum += A_diag_data[jj1];

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	4.88
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P0, P1,
Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source	par_lr_interp.c:1624-1628
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.50
CQA cycles if no scalar integer	1.33
CQA cycles if FP arith vectorized	6.50
CQA cycles if fully vectorized	1.63
Front-end cycles	6.25
DIV/SQRT cycles	6.50
P0 cycles	6.50
P1 cycles	3.25
P2 cycles	3.25
P3 cycles	3.25
P4 cycles	3.25
P5 cycles	4.00
P6 cycles	2.75
P7 cycles	2.75
P8 cycles	2.50
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	50.00
Nb uops	50.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	1.23
Nb FLOP add-sub	4.00
Nb FLOP mul	4.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.77
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	4.88
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P0, P1,
Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source	par_lr_interp.c:1624-1628
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.50
CQA cycles if no scalar integer	1.33
CQA cycles if FP arith vectorized	6.50
CQA cycles if fully vectorized	1.63
Front-end cycles	6.25
DIV/SQRT cycles	6.50
P0 cycles	6.50
P1 cycles	3.25
P2 cycles	3.25
P3 cycles	3.25
P4 cycles	3.25
P5 cycles	4.00
P6 cycles	2.75
P7 cycles	2.75
P8 cycles	2.50
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	50.00
Nb uops	50.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	1.23
Nb FLOP add-sub	4.00
Nb FLOP mul	4.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.77
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source file and lines	par_lr_interp.c:1624-1628
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1624-1628.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 81 paths individually, rerun with max-paths=81
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 81 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.50 to 1.33 cycles (4.87x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.50 to 1.62 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

4: addition or subtraction
4: multiply

The binary loop is loading 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	50
loop length	200
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.50	6.50	3.25	3.25	3.25	3.25	4.00	2.75	2.75	2.50	4.00	4.00	4.00	0.00	0.00
cycles	6.50	6.50	3.25	3.25	3.25	3.25	4.00	2.75	2.75	2.50	4.00	4.00	4.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.25
Overall L1	6.50

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.50 cycles. At this rate:

15% of peak load performance is reached (14.77 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4571b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR X9, [X15, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X1, [X19, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
CCMP X9, X21, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.NE 4571d4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D21, [X11, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D22, D21, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMPE D22, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 457488 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x161c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X9, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X10, [X15, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X17, [X19, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X0, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
CCMP X10, X21, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.NE 4571fc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D23, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D24, D23, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMPE D24, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 457498 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x162c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X17, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X10, [X15, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X1, [X19, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
CCMP X10, X21, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.NE 457224 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x13b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D25, [X11, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D26, D25, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMPE D26, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 457490 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1624>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X17, X9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X10, [X15, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X1, [X19, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
CCMP X10, X21, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.NE 45724c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x13e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D27, [X11, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D28, D27, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMPE D28, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 457480 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1614>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X10, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 4571b0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1344>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FADD D2, D2, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
B 45724c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x13e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FADD D2, D2, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
B 4571d4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FADD D2, D2, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
B 457224 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x13b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FADD D2, D2, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
B 4571fc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source file and lines	par_lr_interp.c:1624-1628
Module	exec

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 81 paths individually, rerun with max-paths=81
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.50 to 1.33 cycles (4.87x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.50 to 1.62 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

4: addition or subtraction
4: multiply

The binary loop is loading 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	50
loop length	200
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.50	6.50	3.25	3.25	3.25	3.25	4.00	2.75	2.75	2.50	4.00	4.00	4.00	0.00	0.00
cycles	6.50	6.50	3.25	3.25	3.25	3.25	4.00	2.75	2.75	2.50	4.00	4.00	4.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.25
Overall L1	6.50

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.50 cycles. At this rate:

15% of peak load performance is reached (14.77 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4571b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR X9, [X15, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X1, [X19, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
CCMP X9, X21, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.NE 4571d4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D21, [X11, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D22, D21, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMPE D22, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 457488 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x161c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X9, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X10, [X15, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X17, [X19, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X0, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
CCMP X10, X21, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.NE 4571fc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D23, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D24, D23, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMPE D24, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 457498 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x162c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X17, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X10, [X15, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X1, [X19, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
CCMP X10, X21, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.NE 457224 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x13b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D25, [X11, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D26, D25, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMPE D26, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 457490 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1624>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X17, X9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X10, [X15, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X1, [X19, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
CCMP X10, X21, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.NE 45724c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x13e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D27, [X11, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D28, D27, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMPE D28, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 457480 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1614>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X10, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 4571b0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1344>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FADD D2, D2, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
B 45724c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x13e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FADD D2, D2, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
B 4571d4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FADD D2, D2, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
B 457224 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x13b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FADD D2, D2, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
B 4571fc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code