OV - exec - Loop 965

	Loop Id: 965	Module: exec	Source: par_lr_interp.c:1644-1651	Coverage: 0.03%

0x457bb8 LDR	X10, [X15, X13,LSL #3]    [9]

0x457bbc LDR	X23, [X19, X10,LSL #3]    [11]

0x457bc0 CMP	X0, X23

0x457bc4 B.GT	457bd8

0x457bc8 LDR	D21, [X11, X13,LSL #3]    [12]

0x457bcc FMUL	D23, D21, D7

0x457bd0 FCMPE	D23, #0

0x457bd4 B.MI	45811c

0x457bd8 CMP	X10, X21

0x457bdc B.EQ	458290

0x457be0 ADD	X10, X13, #1

0x457be4 LDR	X13, [X15, X10,LSL #3]    [7]

0x457be8 LDR	X17, [X19, X13,LSL #3]    [3]

0x457bec CMP	X0, X17

0x457bf0 B.GT	457c04

0x457bf4 LDR	D27, [X11, X10,LSL #3]    [14]

0x457bf8 FMUL	D28, D27, D7

0x457bfc FCMPE	D28, #0

0x457c00 B.MI	45810c

0x457c04 CMP	X13, X21

0x457c08 B.EQ	458274

0x457c0c ADD	X17, X10, #1

0x457c10 LDR	X13, [X15, X17,LSL #3]    [15]

0x457c14 LDR	X23, [X19, X13,LSL #3]    [16]

0x457c18 CMP	X0, X23

0x457c1c B.GT	457c30

0x457c20 LDR	D3, [X11, X17,LSL #3]    [1]

0x457c24 FMUL	D16, D3, D7

0x457c28 FCMPE	D16, #0

0x457c2c B.MI	4580fc

0x457c30 CMP	X13, X21

0x457c34 B.EQ	4582ac

0x457c38 ADD	X17, X10, #2

0x457c3c LDR	X13, [X15, X17,LSL #3]    [5]

0x457c40 LDR	X23, [X19, X13,LSL #3]    [10]

0x457c44 CMP	X0, X23

0x457c48 B.GT	457c5c

0x457c4c LDR	D20, [X11, X17,LSL #3]    [2]

0x457c50 FMUL	D21, D20, D7

0x457c54 FCMPE	D21, #0

0x457c58 B.MI	4580ec

0x457c5c CMP	X13, X21

0x457c60 B.EQ	4582c8

0x457c64 ADD	X13, X10, #3

0x457c68 CMP	X13, X16

0x457c6c B.NE	457bb8

0x4580ec LDR	D23, [X6, X23,LSL #3]    [6]

0x4580f0 FMADD	D2, D22, D20, D23

0x4580f4 STR	D2, [X6, X23,LSL #3]    [6]

0x4580f8 B	457c5c

0x4580fc LDR	D17, [X6, X23,LSL #3]    [13]

0x458100 FMADD	D18, D22, D3, D17

0x458104 STR	D18, [X6, X23,LSL #3]    [13]

0x458108 B	457c30

0x45810c LDR	D29, [X6, X17,LSL #3]    [4]

0x458110 FMADD	D30, D22, D27, D29

0x458114 STR	D30, [X6, X17,LSL #3]    [4]

0x458118 B	457c04

0x45811c LDR	D2, [X6, X23,LSL #3]    [8]

0x458120 FMADD	D24, D22, D21, D2

0x458124 STR	D24, [X6, X23,LSL #3]    [8]

0x458128 B	457bd8

0x458274 LDR	D31, [X11, X10,LSL #3]    [14]

0x458278 FMUL	D0, D31, D7

0x45827c FCMPE	D0, #0

0x458280 B.MI	458288

0x458284 B	457c0c

0x458288 FMADD	D1, D22, D31, D1

0x45828c B	457c0c

0x458290 LDR	D25, [X11, X13,LSL #3]    [12]

0x458294 FMUL	D26, D25, D7

0x458298 FCMPE	D26, #0

0x45829c B.MI	4582a4

0x4582a0 B	457be0

0x4582a4 FMADD	D1, D22, D25, D1

0x4582a8 B	457be0

0x4582ac LDR	D19, [X11, X17,LSL #3]    [1]

0x4582b0 FMUL	D4, D19, D7

0x4582b4 FCMPE	D4, #0

0x4582b8 B.MI	4582c0

0x4582bc B	457c38

0x4582c0 FMADD	D1, D22, D19, D1

0x4582c4 B	457c38

0x4582c8 LDR	D24, [X11, X17,LSL #3]    [2]

0x4582cc FMUL	D25, D24, D7

0x4582d0 FCMPE	D25, #0

0x4582d4 B.MI	4582dc

0x4582d8 B	457c64

0x4582dc FMADD	D1, D22, D24, D1

0x4582e0 B	457c64

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c: 1644 - 1651

--------------------------------------------------------------------------------

1644:                  for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++)

1645:                  {

1646:                    i2 = A_diag_j[jj1];

1647:                    if(P_marker[i2] >= jj_begin_row && (sgn*A_diag_data[jj1]) < 0)

1648:                       P_diag_data[P_marker[i2]] +=

1649:                       distribute*A_diag_data[jj1];

1650:                        if(i2 == i && (sgn*A_diag_data[jj1]) < 0)

1651:                          diagonal += distribute*A_diag_data[jj1];

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	2.72
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.29
Bottlenecks	P0, P1,
Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source	par_lr_interp.c:1644-1651
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.50
CQA cycles if no scalar integer	5.33
CQA cycles if FP arith vectorized	14.50
CQA cycles if fully vectorized	3.63
Front-end cycles	11.25
DIV/SQRT cycles	14.50
P0 cycles	14.50
P1 cycles	3.25
P2 cycles	3.25
P3 cycles	3.25
P4 cycles	3.25
P5 cycles	8.00
P6 cycles	6.75
P7 cycles	6.75
P8 cycles	6.50
P9 cycles	8.00
P10 cycles	8.00
P11 cycles	8.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	90.00
Nb uops	90.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	1.66
Nb FLOP add-sub	0.00
Nb FLOP mul	8.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.24
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	2.72
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.29
Bottlenecks	P0, P1,
Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source	par_lr_interp.c:1644-1651
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.50
CQA cycles if no scalar integer	5.33
CQA cycles if FP arith vectorized	14.50
CQA cycles if fully vectorized	3.63
Front-end cycles	11.25
DIV/SQRT cycles	14.50
P0 cycles	14.50
P1 cycles	3.25
P2 cycles	3.25
P3 cycles	3.25
P4 cycles	3.25
P5 cycles	8.00
P6 cycles	6.75
P7 cycles	6.75
P8 cycles	6.50
P9 cycles	8.00
P10 cycles	8.00
P11 cycles	8.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	90.00
Nb uops	90.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	1.66
Nb FLOP add-sub	0.00
Nb FLOP mul	8.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.24
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source file and lines	par_lr_interp.c:1644-1651
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1644-1651.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 6561 paths individually, rerun with max-paths=6561
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 6561 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.50 to 5.33 cycles (2.72x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 14.50 to 3.62 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 8 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

8: addition or subtraction (all inside FMA instructions)
16: multiply (8 inside FMA instructions)

The binary loop is loading 160 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

General properties

nb instructions	90
loop length	360
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	14.50	14.50	3.25	3.25	3.25	3.25	8.00	6.75	6.75	6.50	8.00	8.00	8.00	0.00	0.00
cycles	14.50	14.50	3.25	3.25	3.25	3.25	8.00	6.75	6.75	6.50	8.00	8.00	8.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.25
Overall L1	14.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.50 cycles. At this rate:

11% of peak load performance is reached (11.03 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.21 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 457bb8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR X10, [X15, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X23, [X19, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X0, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GT 457bd8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D21, [X11, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D23, D21, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMPE D23, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 45811c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x22b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X10, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 458290 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2424>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X13, [X15, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X17, [X19, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X0, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GT 457c04 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D27, [X11, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D28, D27, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMPE D28, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 45810c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x22a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X13, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 458274 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2408>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X17, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X13, [X15, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X23, [X19, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X0, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GT 457c30 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1dc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D3, [X11, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D16, D3, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMPE D16, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 4580fc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2290>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X13, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4582ac <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2440>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X17, X10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X13, [X15, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X23, [X19, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X0, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GT 457c5c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1df0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D20, [X11, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D21, D20, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMPE D21, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 4580ec <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X13, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4582c8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x245c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X13, X10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 457bb8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D23, [X6, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D2, D22, D20, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STR D2, [X6, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B 457c5c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1df0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D17, [X6, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D18, D22, D3, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STR D18, [X6, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B 457c30 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1dc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D29, [X6, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D30, D22, D27, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STR D30, [X6, X17,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B 457c04 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D2, [X6, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D24, D22, D21, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STR D24, [X6, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B 457bd8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D31, [X11, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D0, D31, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMPE D0, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 458288 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x241c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 457c0c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1da0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMADD D1, D22, D31, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
B 457c0c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1da0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D25, [X11, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D26, D25, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMPE D26, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 4582a4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2438>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 457be0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMADD D1, D22, D25, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
B 457be0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D19, [X11, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D4, D19, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMPE D4, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 4582c0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2454>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 457c38 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1dcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMADD D1, D22, D19, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
B 457c38 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1dcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D24, [X11, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D25, D24, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMPE D25, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 4582dc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2470>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 457c64 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1df8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMADD D1, D22, D24, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
B 457c64 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1df8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source file and lines	par_lr_interp.c:1644-1651
Module	exec

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 6561 paths individually, rerun with max-paths=6561
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.50 to 5.33 cycles (2.72x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 8 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

8: addition or subtraction (all inside FMA instructions)
16: multiply (8 inside FMA instructions)

The binary loop is loading 160 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

General properties

nb instructions	90
loop length	360
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	14.50	14.50	3.25	3.25	3.25	3.25	8.00	6.75	6.75	6.50	8.00	8.00	8.00	0.00	0.00
cycles	14.50	14.50	3.25	3.25	3.25	3.25	8.00	6.75	6.75	6.50	8.00	8.00	8.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.25
Overall L1	14.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.50 cycles. At this rate:

11% of peak load performance is reached (11.03 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.21 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 457bb8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR X10, [X15, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X23, [X19, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X0, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GT 457bd8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D21, [X11, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D23, D21, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMPE D23, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 45811c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x22b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X10, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 458290 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2424>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X13, [X15, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X17, [X19, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X0, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GT 457c04 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D27, [X11, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D28, D27, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMPE D28, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 45810c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x22a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X13, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 458274 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2408>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X17, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X13, [X15, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X23, [X19, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X0, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GT 457c30 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1dc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D3, [X11, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D16, D3, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMPE D16, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 4580fc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2290>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X13, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4582ac <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2440>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X17, X10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X13, [X15, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X23, [X19, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X0, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GT 457c5c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1df0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D20, [X11, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D21, D20, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMPE D21, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 4580ec <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X13, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4582c8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x245c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X13, X10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 457bb8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D23, [X6, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D2, D22, D20, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STR D2, [X6, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B 457c5c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1df0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D17, [X6, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D18, D22, D3, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STR D18, [X6, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B 457c30 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1dc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D29, [X6, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D30, D22, D27, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STR D30, [X6, X17,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B 457c04 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D2, [X6, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D24, D22, D21, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STR D24, [X6, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B 457bd8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D31, [X11, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D0, D31, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMPE D0, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 458288 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x241c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 457c0c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1da0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMADD D1, D22, D31, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
B 457c0c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1da0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D25, [X11, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D26, D25, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMPE D26, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 4582a4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2438>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 457be0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMADD D1, D22, D25, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
B 457be0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D19, [X11, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D4, D19, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMPE D4, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 4582c0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2454>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 457c38 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1dcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMADD D1, D22, D19, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
B 457c38 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1dcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D24, [X11, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D25, D24, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMPE D25, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 4582dc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2470>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 457c64 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1df8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMADD D1, D22, D24, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
B 457c64 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1df8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code