OV - exec - Loop 936

	Loop Id: 936	Module: exec	Source: par_multi_interp.c:385-410	Coverage: 0.04%

0x452198 CMN	X6, #1

0x45219c B.EQ	455618

0x4521a0 STR	XZR, [X18, X0,LSL #3]    [37]

0x4521a4 STR	XZR, [X16, X0,LSL #3]    [29]

0x4521a8 STR	X17, [X20, X0,LSL #3]    [40]

0x4521ac STR	X17, [X28, X0,LSL #3]    [7]

0x4521b0 ADD	X0, X0, #1

0x4521b4 LDR	X24, [X11, X0,LSL #3]    [42]

0x4521b8 CMP	X24, #1

0x4521bc B.EQ	45226c

0x4521c0 CMN	X24, #1

0x4521c4 B.EQ	4555fc

0x4521c8 STR	XZR, [X18, X0,LSL #3]    [24]

0x4521cc STR	XZR, [X16, X0,LSL #3]    [12]

0x4521d0 STR	X17, [X20, X0,LSL #3]    [26]

0x4521d4 STR	X17, [X28, X0,LSL #3]    [39]

0x4521d8 ADD	X7, X0, #1

0x4521dc LDR	X8, [X11, X7,LSL #3]    [41]

0x4521e0 CMP	X8, #1

0x4521e4 B.EQ	452294

0x4521e8 CMN	X8, #1

0x4521ec B.EQ	4555e0

0x4521f0 STR	XZR, [X18, X7,LSL #3]    [10]

0x4521f4 STR	XZR, [X16, X7,LSL #3]    [20]

0x4521f8 STR	X17, [X20, X7,LSL #3]    [35]

0x4521fc STR	X17, [X28, X7,LSL #3]    [31]

0x452200 ADD	X4, X0, #2

0x452204 LDR	X2, [X11, X4,LSL #3]    [8]

0x452208 CMP	X2, #1

0x45220c B.EQ	4522bc

0x452210 CMN	X2, #1

0x452214 B.EQ	4555c4

0x452218 STR	XZR, [X18, X4,LSL #3]    [6]

0x45221c STR	XZR, [X16, X4,LSL #3]    [15]

0x452220 STR	X17, [X20, X4,LSL #3]    [28]

0x452224 STR	X17, [X28, X4,LSL #3]    [22]

0x452228 LDR	X12, [SP, #304]    [13]

0x45222c ADD	X0, X0, #3

0x452230 CMP	X12, X0

0x452234 B.EQ	4522e4

0x452238 LDR	X6, [X11, X0,LSL #3]    [32]

0x45223c CMP	X6, #1

0x452240 B.NE	452198

0x452244 STR	X1, [X28, X0,LSL #3]    [7]

0x452248 STR	X0, [X9, X1,LSL #3]    [18]

0x45224c ADD	X1, X1, #1

0x452250 STR	XZR, [X20, X0,LSL #3]    [40]

0x452254 STR	X6, [X18, X0,LSL #3]    [37]

0x452258 STR	XZR, [X16, X0,LSL #3]    [29]

0x45225c ADD	X0, X0, #1

0x452260 LDR	X24, [X11, X0,LSL #3]    [42]

0x452264 CMP	X24, #1

0x452268 B.NE	4521c0

0x45226c STR	X1, [X28, X0,LSL #3]    [38]

0x452270 ADD	X7, X0, #1

0x452274 STR	X0, [X9, X1,LSL #3]    [4]

0x452278 ADD	X1, X1, #1

0x45227c STR	XZR, [X20, X0,LSL #3]    [25]

0x452280 STR	X24, [X18, X0,LSL #3]    [23]

0x452284 STR	XZR, [X16, X0,LSL #3]    [11]

0x452288 LDR	X8, [X11, X7,LSL #3]    [36]

0x45228c CMP	X8, #1

0x452290 B.NE	4521e8

0x452294 STR	X1, [X28, X7,LSL #3]    [30]

0x452298 ADD	X4, X0, #2

0x45229c STR	X7, [X9, X1,LSL #3]    [16]

0x4522a0 ADD	X1, X1, #1

0x4522a4 STR	XZR, [X20, X7,LSL #3]    [34]

0x4522a8 STR	X8, [X18, X7,LSL #3]    [9]

0x4522ac STR	XZR, [X16, X7,LSL #3]    [19]

0x4522b0 LDR	X2, [X11, X4,LSL #3]    [43]

0x4522b4 CMP	X2, #1

0x4522b8 B.NE	452210

0x4522bc STR	X1, [X28, X4,LSL #3]    [21]

0x4522c0 ADD	X0, X0, #3

0x4522c4 LDR	X12, [SP, #304]    [13]

0x4522c8 STR	X4, [X9, X1,LSL #3]    [17]

0x4522cc ADD	X1, X1, #1

0x4522d0 STR	XZR, [X20, X4,LSL #3]    [27]

0x4522d4 STR	X2, [X18, X4,LSL #3]    [5]

0x4522d8 STR	XZR, [X16, X4,LSL #3]    [14]

0x4522dc CMP	X12, X0

0x4522e0 B.NE	452238

0x4555c4 STR	X4, [X10, X5,LSL #3]    [2]

0x4555c8 SUB	X5, X5, #1

0x4555cc STR	XZR, [X18, X4,LSL #3]    [6]

0x4555d0 STR	XZR, [X16, X4,LSL #3]    [15]

0x4555d4 STR	X2, [X20, X4,LSL #3]    [28]

0x4555d8 STR	X2, [X28, X4,LSL #3]    [22]

0x4555dc B	452228

0x4555e0 STR	X7, [X10, X5,LSL #3]    [1]

0x4555e4 SUB	X5, X5, #1

0x4555e8 STR	XZR, [X18, X7,LSL #3]    [10]

0x4555ec STR	XZR, [X16, X7,LSL #3]    [20]

0x4555f0 STR	X8, [X20, X7,LSL #3]    [35]

0x4555f4 STR	X8, [X28, X7,LSL #3]    [31]

0x4555f8 B	452200

0x4555fc STR	X0, [X10, X5,LSL #3]    [33]

0x455600 SUB	X5, X5, #1

0x455604 STR	XZR, [X18, X0,LSL #3]    [24]

0x455608 STR	XZR, [X16, X0,LSL #3]    [12]

0x45560c STR	X24, [X20, X0,LSL #3]    [26]

0x455610 STR	X24, [X28, X0,LSL #3]    [39]

0x455614 B	4521d8

0x455618 STR	X0, [X10, X5,LSL #3]    [3]

0x45561c SUB	X5, X5, #1

0x455620 STR	XZR, [X18, X0,LSL #3]    [37]

0x455624 STR	XZR, [X16, X0,LSL #3]    [29]

0x455628 STR	X6, [X20, X0,LSL #3]    [40]

0x45562c STR	X6, [X28, X0,LSL #3]    [7]

0x455630 B	4521b0

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 385 - 410

--------------------------------------------------------------------------------

385:    for (i = 0; i < n_fine; i++)

386:    {

387:       if (CF_marker[i] == 1)

388:       {

389:          fine_to_coarse[i] = cnt; /* this C point is assigned index

390:                                      coarse_counter on coarse grid,

391:                                      and in column of P */

392:          C_array[cnt++] = i;

393:          assigned[i] = 0;

394:          P_diag_i[i+1] = 1; /* one element in row i1 of P */

395:          P_offd_i[i+1] = 0;

396:       }

397:       else if (CF_marker[i] == -1)

398:       {

399:          pass_array[p_cnt--] = i;

400:          P_diag_i[i+1] = 0;

401:          P_offd_i[i+1] = 0;

402:          assigned[i] = -1;

403:          fine_to_coarse[i] = -1;

404:       }

405:       else

406:       {

407:          P_diag_i[i+1] = 0;

408:          P_offd_i[i+1] = 0;

409:          assigned[i] = -1;

410:          fine_to_coarse[i] = -1;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.02
Bottlenecks	P10, P11, P13, P14,
Function	hypre_BoomerAMGBuildMultipass
Source	par_multi_interp.c:385-410
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	28.00
CQA cycles if no scalar integer	28.00
CQA cycles if FP arith vectorized	28.00
CQA cycles if fully vectorized	7.00
Front-end cycles	13.88
DIV/SQRT cycles	8.50
P0 cycles	8.50
P1 cycles	7.25
P2 cycles	7.25
P3 cycles	7.25
P4 cycles	7.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	28.00
P10 cycles	28.00
P11 cycles	9.00
P12 cycles	28.00
P13 cycles	28.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	111.00
Nb uops	111.00
Nb loads	NA
Nb stores	56.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.57
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	448.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.02
Bottlenecks	P10, P11, P13, P14,
Function	hypre_BoomerAMGBuildMultipass
Source	par_multi_interp.c:385-410
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	28.00
CQA cycles if no scalar integer	28.00
CQA cycles if FP arith vectorized	28.00
CQA cycles if fully vectorized	7.00
Front-end cycles	13.88
DIV/SQRT cycles	8.50
P0 cycles	8.50
P1 cycles	7.25
P2 cycles	7.25
P3 cycles	7.25
P4 cycles	7.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	28.00
P10 cycles	28.00
P11 cycles	9.00
P12 cycles	28.00
P13 cycles	28.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	111.00
Nb uops	111.00
Nb loads	NA
Nb stores	56.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.57
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	448.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass
Source file and lines	par_multi_interp.c:385-410
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:385-410.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 81 paths individually, rerun with max-paths=81
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 81 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 28.00 to 7.00 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 72 bytes. The binary loop is storing 448 bytes.

General properties

nb instructions	111
loop length	444
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	8.50	8.50	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	28.00	28.00	9.00	28.00	28.00
cycles	8.50	8.50	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	28.00	28.00	9.00	28.00	28.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.88
Overall L1	28.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.00 cycles. At this rate:

2% of peak load performance is reached (2.57 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 452238

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
CMN X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 455618 <hypre_BoomerAMGBuildMultipass+0x39f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR XZR, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X17, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X17, [X28, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X24, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 45226c <hypre_BoomerAMGBuildMultipass+0x64c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMN X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4555fc <hypre_BoomerAMGBuildMultipass+0x39dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR XZR, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X17, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X17, [X28, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X7, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X8, [X11, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452294 <hypre_BoomerAMGBuildMultipass+0x674>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMN X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4555e0 <hypre_BoomerAMGBuildMultipass+0x39c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR XZR, [X18, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X16, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X17, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X17, [X28, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, X0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X2, [X11, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4522bc <hypre_BoomerAMGBuildMultipass+0x69c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMN X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4555c4 <hypre_BoomerAMGBuildMultipass+0x39a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR XZR, [X18, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X16, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X17, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X17, [X28, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [SP, #304]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X12, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4522e4 <hypre_BoomerAMGBuildMultipass+0x6c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X6, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 452198 <hypre_BoomerAMGBuildMultipass+0x578>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X1, [X28, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X0, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X6, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X24, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 4521c0 <hypre_BoomerAMGBuildMultipass+0x5a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X1, [X28, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X7, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X24, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X11, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 4521e8 <hypre_BoomerAMGBuildMultipass+0x5c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X1, [X28, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, X0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X7, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [X18, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X16, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X2, [X11, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 452210 <hypre_BoomerAMGBuildMultipass+0x5f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X1, [X28, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X0, X0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X12, [SP, #304]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X4, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X2, [X18, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X16, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X12, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 452238 <hypre_BoomerAMGBuildMultipass+0x618>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X4, [X10, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X18, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X16, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X2, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X2, [X28, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 452228 <hypre_BoomerAMGBuildMultipass+0x608>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X7, [X10, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X18, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X16, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [X28, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 452200 <hypre_BoomerAMGBuildMultipass+0x5e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [X10, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X24, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X24, [X28, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4521d8 <hypre_BoomerAMGBuildMultipass+0x5b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [X10, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X6, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X6, [X28, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4521b0 <hypre_BoomerAMGBuildMultipass+0x590>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_BoomerAMGBuildMultipass
Source file and lines	par_multi_interp.c:385-410
Module	exec

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 81 paths individually, rerun with max-paths=81
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 72 bytes. The binary loop is storing 448 bytes.

General properties

nb instructions	111
loop length	444
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	8.50	8.50	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	28.00	28.00	9.00	28.00	28.00
cycles	8.50	8.50	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	28.00	28.00	9.00	28.00	28.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.88
Overall L1	28.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.00 cycles. At this rate:

2% of peak load performance is reached (2.57 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 452238

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
CMN X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 455618 <hypre_BoomerAMGBuildMultipass+0x39f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR XZR, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X17, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X17, [X28, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X24, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 45226c <hypre_BoomerAMGBuildMultipass+0x64c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMN X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4555fc <hypre_BoomerAMGBuildMultipass+0x39dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR XZR, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X17, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X17, [X28, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X7, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X8, [X11, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452294 <hypre_BoomerAMGBuildMultipass+0x674>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMN X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4555e0 <hypre_BoomerAMGBuildMultipass+0x39c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR XZR, [X18, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X16, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X17, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X17, [X28, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, X0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X2, [X11, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4522bc <hypre_BoomerAMGBuildMultipass+0x69c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMN X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4555c4 <hypre_BoomerAMGBuildMultipass+0x39a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR XZR, [X18, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X16, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X17, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X17, [X28, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [SP, #304]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X12, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4522e4 <hypre_BoomerAMGBuildMultipass+0x6c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X6, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 452198 <hypre_BoomerAMGBuildMultipass+0x578>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X1, [X28, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X0, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X6, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X24, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 4521c0 <hypre_BoomerAMGBuildMultipass+0x5a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X1, [X28, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X7, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X24, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X11, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 4521e8 <hypre_BoomerAMGBuildMultipass+0x5c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X1, [X28, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, X0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X7, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [X18, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X16, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X2, [X11, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 452210 <hypre_BoomerAMGBuildMultipass+0x5f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X1, [X28, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X0, X0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X12, [SP, #304]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X4, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X2, [X18, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X16, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X12, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 452238 <hypre_BoomerAMGBuildMultipass+0x618>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X4, [X10, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X18, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X16, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X2, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X2, [X28, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 452228 <hypre_BoomerAMGBuildMultipass+0x608>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X7, [X10, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X18, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X16, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [X28, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 452200 <hypre_BoomerAMGBuildMultipass+0x5e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [X10, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X24, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X24, [X28, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4521d8 <hypre_BoomerAMGBuildMultipass+0x5b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [X10, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X6, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X6, [X28, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4521b0 <hypre_BoomerAMGBuildMultipass+0x590>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code