OV - exec - Loop 926

	Loop Id: 926	Module: exec	Source: par_multi_interp.c:554-557	Coverage: 0.01%

0x452924 LDR	X1, [X21, X0,LSL #3]    [2]

0x452928 LDR	X3, [X20, X1,LSL #3]    [8]

0x45292c CMP	X3, X19

0x452930 B.EQ	452cb8

0x452934 ADD	X13, X0, #1

0x452938 LDR	X14, [X21, X13,LSL #3]    [11]

0x45293c LDR	X8, [X20, X14,LSL #3]    [13]

0x452940 CMP	X8, X19

0x452944 B.EQ	452cb8

0x452948 ADD	X6, X13, #1

0x45294c LDR	X7, [X21, X6,LSL #3]    [5]

0x452950 LDR	X2, [X20, X7,LSL #3]    [9]

0x452954 CMP	X2, X19

0x452958 B.EQ	452cb8

0x45295c ADD	X4, X0, #3

0x452960 LDR	X9, [X21, X4,LSL #3]    [1]

0x452964 LDR	X1, [X20, X9,LSL #3]    [15]

0x452968 CMP	X1, X19

0x45296c B.EQ	452cb8

0x452970 ADD	X3, X0, #4

0x452974 LDR	X13, [X21, X3,LSL #3]    [16]

0x452978 LDR	X14, [X20, X13,LSL #3]    [7]

0x45297c CMP	X14, X19

0x452980 B.EQ	452cb8

0x452984 ADD	X8, X0, #5

0x452988 LDR	X6, [X21, X8,LSL #3]    [14]

0x45298c LDR	X7, [X20, X6,LSL #3]    [10]

0x452990 CMP	X7, X19

0x452994 B.EQ	452cb8

0x452998 ADD	X2, X0, #6

0x45299c LDR	X4, [X21, X2,LSL #3]    [3]

0x4529a0 LDR	X9, [X20, X4,LSL #3]    [4]

0x4529a4 CMP	X9, X19

0x4529a8 B.EQ	452cb8

0x4529ac ADD	X1, X0, #7

0x4529b0 LDR	X3, [X21, X1,LSL #3]    [6]

0x4529b4 LDR	X13, [X20, X3,LSL #3]    [12]

0x4529b8 CMP	X13, X19

0x4529bc B.EQ	452cb8

0x4529c0 ADD	X0, X0, #8

0x4529c4 CMP	X0, X5

0x4529c8 B.NE	452924

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 554 - 557

--------------------------------------------------------------------------------

554:          for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

555:          {

556:             j1 = S_diag_j[j];

557:             if (assigned[j1] == pass-1)

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGBuildMultipass
Source	par_multi_interp.c:554-557
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.33
CQA cycles if no scalar integer	5.33
CQA cycles if FP arith vectorized	5.33
CQA cycles if fully vectorized	1.33
Front-end cycles	5.25
DIV/SQRT cycles	4.50
P0 cycles	4.50
P1 cycles	4.25
P2 cycles	4.25
P3 cycles	4.25
P4 cycles	4.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	5.33
P10 cycles	5.33
P11 cycles	5.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	42.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGBuildMultipass
Source	par_multi_interp.c:554-557
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.33
CQA cycles if no scalar integer	5.33
CQA cycles if FP arith vectorized	5.33
CQA cycles if fully vectorized	1.33
Front-end cycles	5.25
DIV/SQRT cycles	4.50
P0 cycles	4.50
P1 cycles	4.25
P2 cycles	4.25
P3 cycles	4.25
P4 cycles	4.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	5.33
P10 cycles	5.33
P11 cycles	5.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	42.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass
Source file and lines	par_multi_interp.c:554-557
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:554-557.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 5.33 to 1.33 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 128 bytes.

General properties

nb instructions	42
loop length	168
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	4.25	4.25	4.25	4.25	0.00	0.00	0.00	0.00	5.33	5.33	5.33	0.00	0.00
cycles	4.50	4.50	4.25	4.25	4.25	4.25	0.00	0.00	0.00	0.00	5.33	5.33	5.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.25
Data deps.	1.00
Overall L1	5.33

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.33 cycles. At this rate:

25% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 452924

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDR X1, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X3, [X20, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X3, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X13, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X14, [X21, X13,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [X20, X14,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X8, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X6, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X7, [X21, X6,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X2, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X2, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X4, X0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X1, [X20, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X1, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X3, X0, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X13, [X21, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X14, [X20, X13,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X14, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X8, X0, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X6, [X21, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X7, [X20, X6,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X7, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X2, X0, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X4, [X21, X2,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X9, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X9, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X1, X0, #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X3, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X13, [X20, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X13, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.NE 452924 <hypre_BoomerAMGBuildMultipass+0xd04>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	hypre_BoomerAMGBuildMultipass
Source file and lines	par_multi_interp.c:554-557
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:554-557.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 5.33 to 1.33 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 128 bytes.

General properties

nb instructions	42
loop length	168
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	4.25	4.25	4.25	4.25	0.00	0.00	0.00	0.00	5.33	5.33	5.33	0.00	0.00
cycles	4.50	4.50	4.25	4.25	4.25	4.25	0.00	0.00	0.00	0.00	5.33	5.33	5.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.25
Data deps.	1.00
Overall L1	5.33

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.33 cycles. At this rate:

25% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 452924

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDR X1, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X3, [X20, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X3, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X13, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X14, [X21, X13,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [X20, X14,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X8, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X6, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X7, [X21, X6,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X2, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X2, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X4, X0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X1, [X20, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X1, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X3, X0, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X13, [X21, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X14, [X20, X13,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X14, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X8, X0, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X6, [X21, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X7, [X20, X6,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X7, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X2, X0, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X4, [X21, X2,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X9, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X9, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X1, X0, #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X3, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X13, [X20, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X13, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.NE 452924 <hypre_BoomerAMGBuildMultipass+0xd04>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code