OV - exec - Loop 924

	Loop Id: 924	Module: exec	Source: par_multi_interp.c:550-576 [...]	Coverage: 0.04%

0x452834 ADD	X10, X28, X15,LSL #3

0x452838 LDR	X16, [X28, X15,LSL #3]

0x45283c UBFM	X14, X16, #61, #60

0x452840 LDR	X0, [X24, X16,LSL #3]

0x452844 ADD	X18, X14, #8

0x452848 LDR	X5, [X24, X18]

0x45284c CMP	X0, X5

0x452850 B.GE	4529cc

0x452854 SUB	X8, X5, X0

0x452858 ANDS	X6, X8, #4224

0x45285c B.EQ	452924

0x452860 CMP	X6, #1

0x452864 B.EQ	452908

0x452868 CMP	X6, #2

0x45286c B.EQ	4528f4

0x452870 CMP	X6, #3

0x452874 B.EQ	4528e0

0x452878 CMP	X6, #4

0x45287c B.EQ	4528cc

0x452880 CMP	X6, #5

0x452884 B.EQ	4528b8

0x452888 CMP	X6, #6

0x45288c B.EQ	4528a4

0x452890 LDR	X7, [X21, X0,LSL #3]

0x452894 ADD	X0, X0, #1

0x452898 LDR	X2, [X20, X7,LSL #3]

0x45289c CMP	X2, X19

0x4528a0 B.EQ	452cb8

0x4528a4 LDR	X4, [X21, X0,LSL #3]

0x4528a8 ADD	X0, X0, #1

0x4528ac LDR	X9, [X20, X4,LSL #3]

0x4528b0 CMP	X9, X19

0x4528b4 B.EQ	452cb8

0x4528b8 LDR	X1, [X21, X0,LSL #3]

0x4528bc ADD	X0, X0, #1

0x4528c0 LDR	X3, [X20, X1,LSL #3]

0x4528c4 CMP	X3, X19

0x4528c8 B.EQ	452cb8

0x4528cc LDR	X13, [X21, X0,LSL #3]

0x4528d0 ADD	X0, X0, #1

0x4528d4 LDR	X14, [X20, X13,LSL #3]

0x4528d8 CMP	X14, X19

0x4528dc B.EQ	452cb8

0x4528e0 LDR	X8, [X21, X0,LSL #3]

0x4528e4 ADD	X0, X0, #1

0x4528e8 LDR	X6, [X20, X8,LSL #3]

0x4528ec CMP	X6, X19

0x4528f0 B.EQ	452cb8

0x4528f4 LDR	X7, [X21, X0,LSL #3]

0x4528f8 ADD	X0, X0, #1

0x4528fc LDR	X2, [X20, X7,LSL #3]

0x452900 CMP	X2, X19

0x452904 B.EQ	452cb8

0x452908 LDR	X4, [X21, X0,LSL #3]

0x45290c LDR	X9, [X20, X4,LSL #3]

0x452910 CMP	X9, X19

0x452914 B.EQ	452cb8

0x452918 ADD	X0, X0, #1

0x45291c CMP	X0, X5

0x452920 B.EQ	4529cc

  (926) 0x452924 LDR	X1, [X21, X0,LSL #3]

  (926) 0x452928 LDR	X3, [X20, X1,LSL #3]

  (926) 0x45292c CMP	X3, X19

  (926) 0x452930 B.EQ	452cb8

  (926) 0x452934 ADD	X13, X0, #1

  (926) 0x452938 LDR	X14, [X21, X13,LSL #3]

  (926) 0x45293c LDR	X8, [X20, X14,LSL #3]

  (926) 0x452940 CMP	X8, X19

  (926) 0x452944 B.EQ	452cb8

  (926) 0x452948 ADD	X6, X13, #1

  (926) 0x45294c LDR	X7, [X21, X6,LSL #3]

  (926) 0x452950 LDR	X2, [X20, X7,LSL #3]

  (926) 0x452954 CMP	X2, X19

  (926) 0x452958 B.EQ	452cb8

  (926) 0x45295c ADD	X4, X0, #3

  (926) 0x452960 LDR	X9, [X21, X4,LSL #3]

  (926) 0x452964 LDR	X1, [X20, X9,LSL #3]

  (926) 0x452968 CMP	X1, X19

  (926) 0x45296c B.EQ	452cb8

  (926) 0x452970 ADD	X3, X0, #4

  (926) 0x452974 LDR	X13, [X21, X3,LSL #3]

  (926) 0x452978 LDR	X14, [X20, X13,LSL #3]

  (926) 0x45297c CMP	X14, X19

  (926) 0x452980 B.EQ	452cb8

  (926) 0x452984 ADD	X8, X0, #5

  (926) 0x452988 LDR	X6, [X21, X8,LSL #3]

  (926) 0x45298c LDR	X7, [X20, X6,LSL #3]

  (926) 0x452990 CMP	X7, X19

  (926) 0x452994 B.EQ	452cb8

  (926) 0x452998 ADD	X2, X0, #6

  (926) 0x45299c LDR	X4, [X21, X2,LSL #3]

  (926) 0x4529a0 LDR	X9, [X20, X4,LSL #3]

  (926) 0x4529a4 CMP	X9, X19

  (926) 0x4529a8 B.EQ	452cb8

  (926) 0x4529ac ADD	X1, X0, #7

  (926) 0x4529b0 LDR	X3, [X21, X1,LSL #3]

  (926) 0x4529b4 LDR	X13, [X20, X3,LSL #3]

  (926) 0x4529b8 CMP	X13, X19

  (926) 0x4529bc B.EQ	452cb8

  (926) 0x4529c0 ADD	X0, X0, #8

  (926) 0x4529c4 CMP	X0, X5

  (926) 0x4529c8 B.NE	452924

0x4529cc LDR	X18, [X17, X18]

0x4529d0 LDR	X0, [X17, X16,LSL #3]

0x4529d4 CMP	X0, X18

0x4529d8 B.GE	452b54

0x4529dc SUB	X5, X18, X0

0x4529e0 ANDS	X14, X5, #4224

0x4529e4 B.EQ	452aac

0x4529e8 CMP	X14, #1

0x4529ec B.EQ	452a90

0x4529f0 CMP	X14, #2

0x4529f4 B.EQ	452a7c

0x4529f8 CMP	X14, #3

0x4529fc B.EQ	452a68

0x452a00 CMP	X14, #4

0x452a04 B.EQ	452a54

0x452a08 CMP	X14, #5

0x452a0c B.EQ	452a40

0x452a10 CMP	X14, #6

0x452a14 B.EQ	452a2c

0x452a18 LDR	X8, [X25, X0,LSL #3]

0x452a1c ADD	X0, X0, #1

0x452a20 LDR	X6, [X26, X8,LSL #3]

0x452a24 CMP	X6, X19

0x452a28 B.EQ	452cb8

0x452a2c LDR	X7, [X25, X0,LSL #3]

0x452a30 ADD	X0, X0, #1

0x452a34 LDR	X2, [X26, X7,LSL #3]

0x452a38 CMP	X2, X19

0x452a3c B.EQ	452cb8

0x452a40 LDR	X4, [X25, X0,LSL #3]

0x452a44 ADD	X0, X0, #1

0x452a48 LDR	X9, [X26, X4,LSL #3]

0x452a4c CMP	X9, X19

0x452a50 B.EQ	452cb8

0x452a54 LDR	X1, [X25, X0,LSL #3]

0x452a58 ADD	X0, X0, #1

0x452a5c LDR	X3, [X26, X1,LSL #3]

0x452a60 CMP	X3, X19

0x452a64 B.EQ	452cb8

0x452a68 LDR	X13, [X25, X0,LSL #3]

0x452a6c ADD	X0, X0, #1

0x452a70 LDR	X5, [X26, X13,LSL #3]

0x452a74 CMP	X5, X19

0x452a78 B.EQ	452cb8

0x452a7c LDR	X14, [X25, X0,LSL #3]

0x452a80 ADD	X0, X0, #1

0x452a84 LDR	X8, [X26, X14,LSL #3]

0x452a88 CMP	X8, X19

0x452a8c B.EQ	452cb8

0x452a90 LDR	X6, [X25, X0,LSL #3]

0x452a94 LDR	X7, [X26, X6,LSL #3]

0x452a98 CMP	X7, X19

0x452a9c B.EQ	452cb8

0x452aa0 ADD	X0, X0, #1

0x452aa4 CMP	X0, X18

0x452aa8 B.EQ	452b54

  (925) 0x452aac LDR	X2, [X25, X0,LSL #3]

  (925) 0x452ab0 LDR	X4, [X26, X2,LSL #3]

  (925) 0x452ab4 CMP	X4, X19

  (925) 0x452ab8 B.EQ	452cb8

  (925) 0x452abc ADD	X9, X0, #1

  (925) 0x452ac0 LDR	X1, [X25, X9,LSL #3]

  (925) 0x452ac4 LDR	X3, [X26, X1,LSL #3]

  (925) 0x452ac8 CMP	X3, X19

  (925) 0x452acc B.EQ	452cb8

  (925) 0x452ad0 ADD	X13, X9, #1

  (925) 0x452ad4 LDR	X5, [X25, X13,LSL #3]

  (925) 0x452ad8 LDR	X14, [X26, X5,LSL #3]

  (925) 0x452adc CMP	X14, X19

  (925) 0x452ae0 B.EQ	452cb8

  (925) 0x452ae4 ADD	X8, X0, #3

  (925) 0x452ae8 LDR	X6, [X25, X8,LSL #3]

  (925) 0x452aec LDR	X7, [X26, X6,LSL #3]

  (925) 0x452af0 CMP	X7, X19

  (925) 0x452af4 B.EQ	452cb8

  (925) 0x452af8 ADD	X2, X0, #4

  (925) 0x452afc LDR	X4, [X25, X2,LSL #3]

  (925) 0x452b00 LDR	X9, [X26, X4,LSL #3]

  (925) 0x452b04 CMP	X9, X19

  (925) 0x452b08 B.EQ	452cb8

  (925) 0x452b0c ADD	X1, X0, #5

  (925) 0x452b10 LDR	X3, [X25, X1,LSL #3]

  (925) 0x452b14 LDR	X13, [X26, X3,LSL #3]

  (925) 0x452b18 CMP	X13, X19

  (925) 0x452b1c B.EQ	452cb8

  (925) 0x452b20 ADD	X5, X0, #6

  (925) 0x452b24 LDR	X14, [X25, X5,LSL #3]

  (925) 0x452b28 LDR	X8, [X26, X14,LSL #3]

  (925) 0x452b2c CMP	X8, X19

  (925) 0x452b30 B.EQ	452cb8

  (925) 0x452b34 ADD	X6, X0, #7

  (925) 0x452b38 LDR	X7, [X25, X6,LSL #3]

  (925) 0x452b3c LDR	X2, [X26, X7,LSL #3]

  (925) 0x452b40 CMP	X2, X19

  (925) 0x452b44 B.EQ	452cb8

  (925) 0x452b48 ADD	X0, X0, #8

  (925) 0x452b4c CMP	X0, X18

  (925) 0x452b50 B.NE	452aac

0x452b54 SUB	X15, X15, #1

0x452b58 CMP	X27, X15

0x452b5c B.LE	452834

0x452cb8 LDR	X18, [X28, X27,LSL #3]

0x452cbc UBFM	X4, X27, #61, #60

0x452cc0 ADD	X27, X27, #1

0x452cc4 STR	X18, [X10]

0x452cc8 STR	X16, [X28, X4]

0x452ccc STR	X30, [X20, X16,LSL #3]

0x452cd0 B	452b58

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 550 - 576

--------------------------------------------------------------------------------

550:       for (i = pass_array_size-1; i > cnt-1; i--)

551:       {

552:          i1 = pass_array[i];

553:          no_break = 1;

554:          for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

555:          {

556:             j1 = S_diag_j[j];

557:             if (assigned[j1] == pass-1)

[...]

568:             for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

569:             {

570:                j1 = S_offd_j[j];

571:                if (assigned_offd[j1] == pass-1)

572:                {

573:                   pass_array[i++] = pass_array[cnt];

574:                   pass_array[cnt++] = i1;

575:                   assigned[i1] = pass;

576:                   break;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	P0, P1,
Function	hypre_BoomerAMGBuildMultipass
Source	par_multi_interp.c:550-554,par_multi_interp.c:557-557,par_multi_interp.c:568-568,par_multi_interp.c:571-576
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.00
CQA cycles if no scalar integer	17.00
CQA cycles if FP arith vectorized	17.00
CQA cycles if fully vectorized	4.25
Front-end cycles	15.75
DIV/SQRT cycles	17.00
P0 cycles	17.00
P1 cycles	13.75
P2 cycles	13.75
P3 cycles	13.75
P4 cycles	13.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	12.50
P10 cycles	12.17
P11 cycles	12.33
P12 cycles	1.50
P13 cycles	1.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	126.00
Nb uops	126.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.41
Bytes prefetched	0.00
Bytes loaded	272.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	P0, P1,
Function	hypre_BoomerAMGBuildMultipass
Source	par_multi_interp.c:550-554,par_multi_interp.c:557-557,par_multi_interp.c:568-568,par_multi_interp.c:571-576
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.00
CQA cycles if no scalar integer	17.00
CQA cycles if FP arith vectorized	17.00
CQA cycles if fully vectorized	4.25
Front-end cycles	15.75
DIV/SQRT cycles	17.00
P0 cycles	17.00
P1 cycles	13.75
P2 cycles	13.75
P3 cycles	13.75
P4 cycles	13.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	12.50
P10 cycles	12.17
P11 cycles	12.33
P12 cycles	1.50
P13 cycles	1.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	126.00
Nb uops	126.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.41
Bytes prefetched	0.00
Bytes loaded	272.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass
Source file and lines	par_multi_interp.c:550-576
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:550-557,568-576.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:550-554,557,568,571-576.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 1820 paths individually, rerun with max-paths=1820
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 1820 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 17.00 to 4.25 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 272 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	126
loop length	504
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	17.00	17.00	13.75	13.75	13.75	13.75	0.00	0.00	0.00	0.00	12.50	12.17	12.33	1.50	1.50
cycles	17.00	17.00	13.75	13.75	13.75	13.75	0.00	0.00	0.00	0.00	12.50	12.17	12.33	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.75
Overall L1	17.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.41 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 452834

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADD X10, X28, X15,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X16, [X28, X15,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X14, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X24, X16,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X5, [X24, X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4529cc <hypre_BoomerAMGBuildMultipass+0xdac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB X8, X5, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ANDS X6, X8, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452924 <hypre_BoomerAMGBuildMultipass+0xd04>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452908 <hypre_BoomerAMGBuildMultipass+0xce8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4528f4 <hypre_BoomerAMGBuildMultipass+0xcd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4528e0 <hypre_BoomerAMGBuildMultipass+0xcc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4528cc <hypre_BoomerAMGBuildMultipass+0xcac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4528b8 <hypre_BoomerAMGBuildMultipass+0xc98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4528a4 <hypre_BoomerAMGBuildMultipass+0xc84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X7, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X2, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X4, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X9, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X3, [X20, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X3, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X14, [X20, X13,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X6, [X20, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X6, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X7, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X2, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X4, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4529cc <hypre_BoomerAMGBuildMultipass+0xdac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X17, X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X17, X16,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X0, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 452b54 <hypre_BoomerAMGBuildMultipass+0xf34>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB X5, X18, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ANDS X14, X5, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452aac <hypre_BoomerAMGBuildMultipass+0xe8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452a90 <hypre_BoomerAMGBuildMultipass+0xe70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452a7c <hypre_BoomerAMGBuildMultipass+0xe5c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452a68 <hypre_BoomerAMGBuildMultipass+0xe48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452a54 <hypre_BoomerAMGBuildMultipass+0xe34>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452a40 <hypre_BoomerAMGBuildMultipass+0xe20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452a2c <hypre_BoomerAMGBuildMultipass+0xe0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X6, [X26, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X6, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X7, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X2, [X26, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X4, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X9, [X26, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X3, [X26, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X3, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X5, [X26, X13,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X5, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X8, [X26, X14,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X6, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X7, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X0, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452b54 <hypre_BoomerAMGBuildMultipass+0xf34>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB X15, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X27, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 452834 <hypre_BoomerAMGBuildMultipass+0xc14>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X28, X27,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X4, X27, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X27, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X18, [X10]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X16, [X28, X4]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X30, [X20, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 452b58 <hypre_BoomerAMGBuildMultipass+0xf38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_BoomerAMGBuildMultipass
Source file and lines	par_multi_interp.c:550-576
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 1820 paths individually, rerun with max-paths=1820
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 272 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	126
loop length	504
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	17.00	17.00	13.75	13.75	13.75	13.75	0.00	0.00	0.00	0.00	12.50	12.17	12.33	1.50	1.50
cycles	17.00	17.00	13.75	13.75	13.75	13.75	0.00	0.00	0.00	0.00	12.50	12.17	12.33	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.75
Overall L1	17.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.41 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 452834

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADD X10, X28, X15,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X16, [X28, X15,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X14, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X24, X16,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X5, [X24, X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4529cc <hypre_BoomerAMGBuildMultipass+0xdac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB X8, X5, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ANDS X6, X8, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452924 <hypre_BoomerAMGBuildMultipass+0xd04>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452908 <hypre_BoomerAMGBuildMultipass+0xce8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4528f4 <hypre_BoomerAMGBuildMultipass+0xcd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4528e0 <hypre_BoomerAMGBuildMultipass+0xcc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4528cc <hypre_BoomerAMGBuildMultipass+0xcac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4528b8 <hypre_BoomerAMGBuildMultipass+0xc98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4528a4 <hypre_BoomerAMGBuildMultipass+0xc84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X7, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X2, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X4, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X9, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X3, [X20, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X3, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X14, [X20, X13,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X6, [X20, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X6, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X7, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X2, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X4, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4529cc <hypre_BoomerAMGBuildMultipass+0xdac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X17, X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X17, X16,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X0, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 452b54 <hypre_BoomerAMGBuildMultipass+0xf34>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB X5, X18, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ANDS X14, X5, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452aac <hypre_BoomerAMGBuildMultipass+0xe8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452a90 <hypre_BoomerAMGBuildMultipass+0xe70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452a7c <hypre_BoomerAMGBuildMultipass+0xe5c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452a68 <hypre_BoomerAMGBuildMultipass+0xe48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452a54 <hypre_BoomerAMGBuildMultipass+0xe34>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452a40 <hypre_BoomerAMGBuildMultipass+0xe20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452a2c <hypre_BoomerAMGBuildMultipass+0xe0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X6, [X26, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X6, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X7, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X2, [X26, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X4, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X9, [X26, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X3, [X26, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X3, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X5, [X26, X13,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X5, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X8, [X26, X14,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X6, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X7, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452cb8 <hypre_BoomerAMGBuildMultipass+0x1098>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X0, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452b54 <hypre_BoomerAMGBuildMultipass+0xf34>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB X15, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X27, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 452834 <hypre_BoomerAMGBuildMultipass+0xc14>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X28, X27,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X4, X27, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X27, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X18, [X10]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X16, [X28, X4]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X30, [X20, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 452b58 <hypre_BoomerAMGBuildMultipass+0xf38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code