OV - exec - Loop 903

0x453840 ADD	X24, X0, #8

0x453844 ADD	X8, X0, #16

0x453848 LDR	X17, [X14, X0]    [7]

0x45384c ADD	X7, X0, #24

0x453850 LDR	X1, [X3, X0]    [2]

0x453854 ADD	X27, X17, X1

0x453858 STR	X27, [X14, X0]    [7]

0x45385c LDR	X13, [X21, X0]    [3]

0x453860 LDR	X16, [X2, X0]    [12]

0x453864 ADD	X30, X13, X16

0x453868 STR	X30, [X21, X0]    [3]

0x45386c ADD	X0, X0, #32

0x453870 LDR	X4, [X14, X24]    [1]

0x453874 LDR	X10, [X3, X24]    [4]

0x453878 ADD	X9, X4, X10

0x45387c STR	X9, [X14, X24]    [1]

0x453880 LDR	X12, [X21, X24]    [9]

0x453884 LDR	X5, [X2, X24]    [10]

0x453888 ADD	X18, X12, X5

0x45388c STR	X18, [X21, X24]    [9]

0x453890 LDR	X23, [X14, X8]    [5]

0x453894 LDR	X11, [X3, X8]    [16]

0x453898 ADD	X15, X23, X11

0x45389c STR	X15, [X14, X8]    [5]

0x4538a0 LDR	X17, [X21, X8]    [13]

0x4538a4 LDR	X24, [X2, X8]    [8]

0x4538a8 ADD	X1, X17, X24

0x4538ac STR	X1, [X21, X8]    [13]

0x4538b0 LDR	X27, [X14, X7]    [15]

0x4538b4 LDR	X8, [X3, X7]    [11]

0x4538b8 ADD	X13, X27, X8

0x4538bc STR	X13, [X14, X7]    [15]

0x4538c0 LDR	X16, [X21, X7]    [6]

0x4538c4 LDR	X30, [X2, X7]    [14]

0x4538c8 ADD	X4, X16, X30

0x4538cc STR	X4, [X21, X7]    [6]

0x4538d0 CMP	X6, X0

0x4538d4 B.NE	453840

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1158 - 1161

--------------------------------------------------------------------------------

1158:    for (i=0; i < n_fine; i++)

1159:    {

1160:       P_diag_i[i+1] += P_diag_i[i];

1161:       P_offd_i[i+1] += P_offd_i[i];

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.68
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGBuildMultipass
Source	par_multi_interp.c:1158-1161
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	2.00
Front-end cycles	4.75
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	3.25
P2 cycles	3.25
P3 cycles	3.25
P4 cycles	3.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	8.00
P10 cycles	8.00
P11 cycles	8.00
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	38.00
Nb uops	38.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.68
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGBuildMultipass
Source	par_multi_interp.c:1158-1161
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	2.00
Front-end cycles	4.75
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	3.25
P2 cycles	3.25
P3 cycles	3.25
P4 cycles	3.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	8.00
P10 cycles	8.00
P11 cycles	8.00
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	38.00
Nb uops	38.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass
Source file and lines	par_multi_interp.c:1158-1161
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1158-1161.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 8.00 to 2.00 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 128 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	38
loop length	152
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	3.25	3.25	3.25	3.25	0.00	0.00	0.00	0.00	8.00	8.00	8.00	4.00	4.00
cycles	0.50	0.50	3.25	3.25	3.25	3.25	0.00	0.00	0.00	0.00	8.00	8.00	8.00	4.00	4.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.75
Data deps.	1.00
Overall L1	8.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (8.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 453840

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADD X24, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X8, X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X17, [X14, X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X7, X0, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X1, [X3, X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X27, X17, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X27, [X14, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X21, X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X2, X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X30, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X30, [X21, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X4, [X14, X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X3, X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X4, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X9, [X14, X24]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X21, X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X2, X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X12, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X18, [X21, X24]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X23, [X14, X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X3, X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X23, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X15, [X14, X8]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X17, [X21, X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X24, [X2, X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X17, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X1, [X21, X8]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X27, [X14, X7]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X3, X7]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X27, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X13, [X14, X7]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X21, X7]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X2, X7]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X4, X16, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X4, [X21, X7]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X6, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 453840 <hypre_BoomerAMGBuildMultipass+0x1c20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_BoomerAMGBuildMultipass
Source file and lines	par_multi_interp.c:1158-1161
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1158-1161.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 8.00 to 2.00 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 128 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	38
loop length	152
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	3.25	3.25	3.25	3.25	0.00	0.00	0.00	0.00	8.00	8.00	8.00	4.00	4.00
cycles	0.50	0.50	3.25	3.25	3.25	3.25	0.00	0.00	0.00	0.00	8.00	8.00	8.00	4.00	4.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.75
Data deps.	1.00
Overall L1	8.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (8.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 453840

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADD X24, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X8, X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X17, [X14, X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X7, X0, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X1, [X3, X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X27, X17, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X27, [X14, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X21, X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X2, X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X30, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X30, [X21, X0]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X4, [X14, X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X3, X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X4, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X9, [X14, X24]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X21, X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X2, X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X12, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X18, [X21, X24]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X23, [X14, X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X3, X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X23, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X15, [X14, X8]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X17, [X21, X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X24, [X2, X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X17, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X1, [X21, X8]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X27, [X14, X7]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X3, X7]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X27, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X13, [X14, X7]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X21, X7]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X2, X7]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X4, X16, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X4, [X21, X7]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X6, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 453840 <hypre_BoomerAMGBuildMultipass+0x1c20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code