OV - exec - Loop 884

0x452508 ADD	X18, X15, X9

0x45250c LDR	X14, [X15, X9]

0x452510 UBFM	X4, X14, #61, #60

0x452514 LDR	X0, [X16, X14,LSL #3]

0x452518 ADD	X27, X4, #8

0x45251c ADD	X2, X20, X4

0x452520 LDR	X8, [X16, X27]

0x452524 ADD	X21, X16, X27

0x452528 CMP	X0, X8

0x45252c B.GE	45254c

  (930) 0x452530 LDR	X6, [X10, X0,LSL #3]

  (930) 0x452534 LDR	X24, [X30, X6,LSL #3]

  (930) 0x452538 CMP	X24, #1

  (930) 0x45253c B.EQ	452c90

  (930) 0x452540 ADD	X0, X0, #1

  (930) 0x452544 CMP	X0, X8

  (930) 0x452548 B.LT	452530

0x45254c LDR	X6, [X17, X14,LSL #3]

0x452550 ADD	X28, X17, X27

0x452554 LDR	X1, [X17, X27]

0x452558 CMP	X6, X1

0x45255c B.GE	45257c

  (929) 0x452560 LDR	X4, [X11, X6,LSL #3]

  (929) 0x452564 LDR	X21, [X26, X4,LSL #3]

  (929) 0x452568 CMP	X21, #1

  (929) 0x45256c B.EQ	4526bc

  (929) 0x452570 ADD	X6, X6, #1

  (929) 0x452574 CMP	X6, X1

  (929) 0x452578 B.LT	452560

0x45257c LDR	X27, [X2]

0x452580 CMP	X27, #1

0x452584 B.EQ	4526e0

0x452588 SUB	X7, X7, #1

0x45258c CMP	X23, X7

0x452590 B.GT	4526fc

0x452594 UBFM	X9, X7, #61, #60

0x452598 B	452508

  (929) 0x4526bc LDR	X24, [X13, X27]

  (929) 0x4526c0 ADD	X6, X6, #1

  (929) 0x4526c4 ADD	X19, X19, #1

  (929) 0x4526c8 ADD	X0, X24, #1

  (929) 0x4526cc STR	X0, [X13, X27]

  (929) 0x4526d0 STR	X21, [X2]

  (929) 0x4526d4 LDR	X1, [X28]

  (929) 0x4526d8 CMP	X6, X1

  (929) 0x4526dc B.LT	452560

0x4526e0 LDR	X2, [X15, X23,LSL #3]

0x4526e4 UBFM	X3, X23, #61, #60

0x4526e8 ADD	X23, X23, #1

0x4526ec STR	X2, [X18]

0x4526f0 STR	X14, [X15, X3]

0x4526f4 CMP	X23, X7

0x4526f8 B.LE	452508

  (930) 0x452c90 LDR	X1, [X12, X27]

  (930) 0x452c94 ADD	X0, X0, #1

  (930) 0x452c98 ADD	X5, X5, #1

  (930) 0x452c9c ADD	X3, X1, #1

  (930) 0x452ca0 STR	X3, [X12, X27]

  (930) 0x452ca4 STR	X24, [X2]

  (930) 0x452ca8 LDR	X8, [X21]

  (930) 0x452cac CMP	X0, X8

  (930) 0x452cb0 B.LT	452530

0x452cb4 B	45254c

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 488 - 514

--------------------------------------------------------------------------------

488:    for (i = pass_array_size-1; i > cnt-1; i--)

489:    {

490:      i1 = pass_array[i];

491:      for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

492:      {

493:         j1 = S_diag_j[j];

494:         if (CF_marker[j1] == 1)

495:         {

496:            P_diag_i[i1+1]++;

497:            cnt_nz++;

498:            assigned[i1] = 1;

499:         }

500:      }

501:      for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

502:      {

503:         j1 = S_offd_j[j];

504:         if (CF_marker_offd[j1] == 1)

505:         {

506:            P_offd_i[i1+1]++;

507:            cnt_nz_offd++;

508:            assigned[i1] = 1;

509:         }

510:      }

511:      if (assigned[i1] == 1)

512:      {

513:         pass_array[i++] = pass_array[cnt];

514:         pass_array[cnt++] = i1;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass
Source	par_multi_interp.c:488-491,par_multi_interp.c:501-501,par_multi_interp.c:511-514
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.88
CQA cycles if no scalar integer	3.88
CQA cycles if FP arith vectorized	3.88
CQA cycles if fully vectorized	0.97
Front-end cycles	3.88
DIV/SQRT cycles	3.50
P0 cycles	3.50
P1 cycles	3.75
P2 cycles	3.75
P3 cycles	3.75
P4 cycles	3.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	3.00
P10 cycles	3.00
P11 cycles	3.00
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	31.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.58
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass
Source	par_multi_interp.c:488-491,par_multi_interp.c:501-501,par_multi_interp.c:511-514
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.88
CQA cycles if no scalar integer	3.88
CQA cycles if FP arith vectorized	3.88
CQA cycles if fully vectorized	0.97
Front-end cycles	3.88
DIV/SQRT cycles	3.50
P0 cycles	3.50
P1 cycles	3.75
P2 cycles	3.75
P3 cycles	3.75
P4 cycles	3.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	3.00
P10 cycles	3.00
P11 cycles	3.00
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	31.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.58
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass
Source file and lines	par_multi_interp.c:488-514
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:488-514.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:488-491,501,511-514.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=15
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 15 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.88 to 0.97 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 56 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	3.00	3.00	3.00	1.00	1.00
cycles	3.50	3.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	3.00	3.00	3.00	1.00	1.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.88
Overall L1	3.88

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.88 cycles. At this rate:

15% of peak load performance is reached (14.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (4.13 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 452508

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADD X18, X15, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X14, [X15, X9]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X4, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X16, X14,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X27, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X2, X20, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X8, [X16, X27]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X21, X16, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X0, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 45254c <hypre_BoomerAMGBuildMultipass+0x92c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X6, [X17, X14,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X28, X17, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X1, [X17, X27]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X6, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 45257c <hypre_BoomerAMGBuildMultipass+0x95c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X27, [X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4526e0 <hypre_BoomerAMGBuildMultipass+0xac0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB X7, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X23, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 4526fc <hypre_BoomerAMGBuildMultipass+0xadc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X9, X7, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 452508 <hypre_BoomerAMGBuildMultipass+0x8e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [X15, X23,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X3, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X2, [X18]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X14, [X15, X3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X23, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 452508 <hypre_BoomerAMGBuildMultipass+0x8e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
B 45254c <hypre_BoomerAMGBuildMultipass+0x92c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_BoomerAMGBuildMultipass
Source file and lines	par_multi_interp.c:488-514
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:488-514.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:488-491,501,511-514.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=15
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 15 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.88 to 0.97 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 56 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	3.00	3.00	3.00	1.00	1.00
cycles	3.50	3.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	3.00	3.00	3.00	1.00	1.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.88
Overall L1	3.88

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.88 cycles. At this rate:

15% of peak load performance is reached (14.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (4.13 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 452508

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADD X18, X15, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X14, [X15, X9]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X4, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X16, X14,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X27, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X2, X20, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X8, [X16, X27]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X21, X16, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X0, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 45254c <hypre_BoomerAMGBuildMultipass+0x92c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X6, [X17, X14,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X28, X17, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X1, [X17, X27]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X6, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 45257c <hypre_BoomerAMGBuildMultipass+0x95c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X27, [X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4526e0 <hypre_BoomerAMGBuildMultipass+0xac0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB X7, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X23, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 4526fc <hypre_BoomerAMGBuildMultipass+0xadc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X9, X7, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 452508 <hypre_BoomerAMGBuildMultipass+0x8e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [X15, X23,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X3, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X2, [X18]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X14, [X15, X3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X23, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 452508 <hypre_BoomerAMGBuildMultipass+0x8e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
B 45254c <hypre_BoomerAMGBuildMultipass+0x92c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code