OV - exec - Loop 878

      (875) 0x451a60 LDR	X30, [X1, #8]

      (875) 0x451a64 CMN	X18, #3

      (875) 0x451a68 ADD	X1, X1, #8

      (875) 0x451a6c CSINC	X19, X19, X19, #1

      (875) 0x451a70 CMP	X30, #1

      (875) 0x451a74 B.EQ	451b60

      (875) 0x451a8c LDR	X2, [X1, #16]

      (875) 0x451a90 CMN	X22, #3

      (875) 0x451a94 CSINC	X19, X19, X19, #1

      (875) 0x451a98 CMP	X2, #1

      (875) 0x451a9c B.EQ	451b80

      (875) 0x451ab4 LDR	X3, [X1, #32]

      (875) 0x451ab8 CMN	X0, #3

      (875) 0x451abc CSINC	X19, X19, X19, #1

      (875) 0x451ac0 CMP	X3, #1

      (875) 0x451ac4 B.EQ	451ba0

0x451ac8 LDR	X4, [X1, #40]

0x451acc CMN	X3, #3

0x451ad0 CSINC	X19, X19, X19, #1

0x451ad4 CMP	X4, #1

0x451ad8 B.EQ	451bb0

      (875) 0x451adc LDR	X6, [X1, #48]

      (875) 0x451ae0 CMN	X4, #3

      (875) 0x451ae4 CSINC	X19, X19, X19, #1

      (875) 0x451ae8 CMP	X6, #1

      (875) 0x451aec B.EQ	451bc0

    (876) 0x451af0 CMN	X6, #3

    (876) 0x451af4 CSINC	X19, X19, X19, #1

      (875) 0x451af8 ADD	X1, X1, #56

      (875) 0x451afc CMP	X1, X5

      (875) 0x451b00 B.EQ	451b1c

      (875) 0x451b04 LDR	X18, [X1]

      (875) 0x451b08 CMP	X18, #1

      (875) 0x451b0c B.NE	451a60

      (875) 0x451b60 LDR	X22, [X1, #8]

      (875) 0x451b64 ADD	X21, X21, #1

      (875) 0x451b68 CMP	X22, #1

      (875) 0x451b6c B.NE	451a8c

      (875) 0x451b80 LDR	X0, [X1, #24]

      (875) 0x451b84 ADD	X21, X21, #1

      (875) 0x451b88 CMP	X0, #1

      (875) 0x451b8c B.NE	451ab4

      (875) 0x451ba0 LDR	X4, [X1, #40]

      (875) 0x451ba4 ADD	X21, X21, #1

      (875) 0x451ba8 CMP	X4, #1

      (875) 0x451bac B.NE	451adc

  (877) 0x451bb0 LDR	X6, [X1, #48]

  (877) 0x451bb4 ADD	X21, X21, #1

  (877) 0x451bb8 CMP	X6, #1

  (877) 0x451bbc B.NE	451af0

      (875) 0x451bc0 ADD	X21, X21, #1

      (875) 0x451bc4 B	451af8

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 275 - 276

--------------------------------------------------------------------------------

275:       if (CF_marker[i] == 1) n_coarse++;

276:       else if (CF_marker[i] == -3) n_SF++;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	P2, P3, P4, P5,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.0
Source	par_multi_interp.c:275-276
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	0.75
CQA cycles if no scalar integer	0.75
CQA cycles if FP arith vectorized	0.75
CQA cycles if fully vectorized	0.19
Front-end cycles	0.63
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.33
P10 cycles	0.33
P11 cycles	0.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	5.00
Nb uops	5.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.67
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	P2, P3, P4, P5,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.0
Source	par_multi_interp.c:275-276
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	0.75
CQA cycles if no scalar integer	0.75
CQA cycles if FP arith vectorized	0.75
CQA cycles if fully vectorized	0.19
Front-end cycles	0.63
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.33
P10 cycles	0.33
P11 cycles	0.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	5.00
Nb uops	5.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.67
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass._omp_fn.0
Source file and lines	par_multi_interp.c:275-276
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:275-276.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 0.75 to 0.19 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes.

General properties

nb instructions	5
loop length	20
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

0.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	0.33	0.33	0.33	0.00	0.00
cycles	0.50	0.50	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	0.33	0.33	0.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	0.63
Overall L1	0.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 0.75 cycles. At this rate:

11% of peak load performance is reached (10.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 451ac8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDR X4, [X1, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMN X3, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
CSINC X19, X19, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.EQ 451bb0 <hypre_BoomerAMGBuildMultipass._omp_fn.0+0x2b0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	hypre_BoomerAMGBuildMultipass._omp_fn.0
Source file and lines	par_multi_interp.c:275-276
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:275-276.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 0.75 to 0.19 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes.

General properties

nb instructions	5
loop length	20
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

0.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	0.33	0.33	0.33	0.00	0.00
cycles	0.50	0.50	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	0.33	0.33	0.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	0.63
Overall L1	0.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 0.75 cycles. At this rate:

11% of peak load performance is reached (10.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 451ac8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDR X4, [X1, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMN X3, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
CSINC X19, X19, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.EQ 451bb0 <hypre_BoomerAMGBuildMultipass._omp_fn.0+0x2b0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code