OV - exec - Loop 852

	Loop Id: 852	Module: exec	Source: par_multi_interp.c:1605-1660	Coverage: 0.06%

0x4508d0 LDR	X0, [X17]

0x4508d4 LDR	X3, [SP, #144]

0x4508d8 UBFM	X16, X0, #61, #60

0x4508dc LDR	X14, [X8, X0,LSL #3]

0x4508e0 ADD	X15, X16, #8

0x4508e4 LDR	X2, [X8, X15]

0x4508e8 LDR	X28, [X3, X0,LSL #3]

0x4508ec ADD	X18, X28, X2

0x4508f0 SUB	X30, X18, X14

0x4508f4 CMP	X28, X30

0x4508f8 B.GE	450a28

0x4508fc LDR	X14, [SP, #184]

0x450900 LDR	X18, [X14, #8]

0x450904 ADD	X3, X18, X30,LSL #3

0x450908 ADD	X1, X18, X28,LSL #3

0x45090c SUB	X2, X3, X1

0x450910 SUB	X30, X2, #8

0x450914 UBFM	X14, X30, #3, #63

0x450918 ADD	X2, X14, #1

0x45091c ANDS	X30, X2, #4224

0x450920 B.EQ	4509b4

0x450924 CMP	X30, #1

0x450928 B.EQ	4509a0

0x45092c CMP	X30, #2

0x450930 B.EQ	450994

0x450934 CMP	X30, #3

0x450938 B.EQ	450988

0x45093c CMP	X30, #4

0x450940 B.EQ	45097c

0x450944 CMP	X30, #5

0x450948 B.EQ	450970

0x45094c CMP	X30, #6

0x450950 B.EQ	450964

0x450954 LDR	X28, [X18, X28,LSL #3]

0x450958 ADD	X1, X1, #8

0x45095c LDR	X18, [X22, X28,LSL #3]

0x450960 STR	X0, [X20, X18,LSL #3]

0x450964 LDR	X14, [X1], #8

0x450968 LDR	X2, [X22, X14,LSL #3]

0x45096c STR	X0, [X20, X2,LSL #3]

0x450970 LDR	X30, [X1], #8

0x450974 LDR	X28, [X22, X30,LSL #3]

0x450978 STR	X0, [X20, X28,LSL #3]

0x45097c LDR	X18, [X1], #8

0x450980 LDR	X14, [X22, X18,LSL #3]

0x450984 STR	X0, [X20, X14,LSL #3]

0x450988 LDR	X2, [X1], #8

0x45098c LDR	X30, [X22, X2,LSL #3]

0x450990 STR	X0, [X20, X30,LSL #3]

0x450994 LDR	X28, [X1], #8

0x450998 LDR	X18, [X22, X28,LSL #3]

0x45099c STR	X0, [X20, X18,LSL #3]

0x4509a0 LDR	X14, [X1], #8

0x4509a4 LDR	X2, [X22, X14,LSL #3]

0x4509a8 STR	X0, [X20, X2,LSL #3]

0x4509ac CMP	X3, X1

0x4509b0 B.EQ	450a24

  (862) 0x4509b4 ORR	X30, XZR, X1

  (862) 0x4509b8 ADD	X1, X1, #64

  (862) 0x4509bc LDR	X28, [X30], #8

  (862) 0x4509c0 LDR	X18, [X22, X28,LSL #3]

  (862) 0x4509c4 STR	X0, [X20, X18,LSL #3]

  (862) 0x4509c8 LDUR	X14, [X1, #456]

  (862) 0x4509cc LDR	X2, [X22, X14,LSL #3]

  (862) 0x4509d0 STR	X0, [X20, X2,LSL #3]

  (862) 0x4509d4 LDR	X30, [X30, #8]

  (862) 0x4509d8 LDR	X28, [X22, X30,LSL #3]

  (862) 0x4509dc STR	X0, [X20, X28,LSL #3]

  (862) 0x4509e0 LDUR	X18, [X1, #472]

  (862) 0x4509e4 LDR	X14, [X22, X18,LSL #3]

  (862) 0x4509e8 STR	X0, [X20, X14,LSL #3]

  (862) 0x4509ec LDUR	X2, [X1, #480]

  (862) 0x4509f0 LDR	X30, [X22, X2,LSL #3]

  (862) 0x4509f4 STR	X0, [X20, X30,LSL #3]

  (862) 0x4509f8 LDUR	X28, [X1, #488]

  (862) 0x4509fc LDR	X18, [X22, X28,LSL #3]

  (862) 0x450a00 STR	X0, [X20, X18,LSL #3]

  (862) 0x450a04 LDUR	X14, [X1, #496]

  (862) 0x450a08 LDR	X2, [X22, X14,LSL #3]

  (862) 0x450a0c STR	X0, [X20, X2,LSL #3]

  (862) 0x450a10 LDUR	X30, [X1, #504]

  (862) 0x450a14 LDR	X28, [X22, X30,LSL #3]

  (862) 0x450a18 STR	X0, [X20, X28,LSL #3]

  (862) 0x450a1c CMP	X3, X1

  (862) 0x450a20 B.NE	4509b4

0x450a24 LDR	X14, [X8, X0,LSL #3]

0x450a28 ADD	X30, X7, X15

0x450a2c LDR	X1, [X7, X0,LSL #3]

0x450a30 LDR	X3, [X7, X15]

0x450a34 ADD	X1, X1, #1

0x450a38 CMP	X1, X3

0x450a3c B.GE	45109c

0x450a40 LDR	X2, [SP, #112]

0x450a44 MOVI	D0, #0

0x450a48 STR	X5, [SP, #120]

0x450a4c LDR	X18, [SP, #160]

0x450a50 FMOV	D1, D0

0x450a54 LDR	X28, [SP, #200]

0x450a58 CMP	X2, #1

0x450a5c B.EQ	450f54

0x450a60 STR	X6, [SP, #128]

  (861) 0x450a64 LDR	X2, [X23, X1,LSL #3]

  (861) 0x450a68 LDR	X6, [X24, X2,LSL #3]

  (861) 0x450a6c CMN	X6, #3

  (861) 0x450a70 B.EQ	450a8c

  (861) 0x450a74 LDR	X5, [X27, X2,LSL #3]

  (861) 0x450a78 LDR	X6, [X27, X16]

  (861) 0x450a7c CMP	X5, X6

  (861) 0x450a80 B.NE	450a8c

  (861) 0x450a84 LDR	D4, [X4, X1,LSL #3]

  (861) 0x450a88 FADD	D0, D0, D4

  (861) 0x450a8c CMN	X2, #1

  (861) 0x450a90 B.EQ	450ac0

  (861) 0x450a94 LDR	X5, [X20, X2,LSL #3]

  (861) 0x450a98 CMP	X0, X5

  (861) 0x450a9c B.NE	450ac0

  (861) 0x450aa0 LDR	D5, [X4, X1,LSL #3]

  (861) 0x450aa4 UBFM	X3, X14, #61, #60

  (861) 0x450aa8 LDR	X6, [X18, X2,LSL #3]

  (861) 0x450aac FADD	D1, D1, D5

  (861) 0x450ab0 STR	D5, [X10, X14,LSL #3]

  (861) 0x450ab4 ADD	X14, X14, #1

  (861) 0x450ab8 STR	X6, [X28, X3]

  (861) 0x450abc LDR	X3, [X30]

  (861) 0x450ac0 ADD	X1, X1, #1

  (861) 0x450ac4 CMP	X3, X1

  (861) 0x450ac8 B.GT	450a64

0x450acc LDP	X5, X6, [SP, #120]

0x450ad0 LDR	X1, [SP, #136]

0x450ad4 LDR	X2, [X11, X15]

0x450ad8 LDR	X3, [X11, X0,LSL #3]

0x450adc LDR	X18, [X1, X0,LSL #3]

0x450ae0 ADD	X28, X18, X2

0x450ae4 SUB	X30, X28, X3

0x450ae8 CMP	X18, X30

0x450aec B.GE	450c1c

0x450af0 LDR	X3, [SP, #176]

0x450af4 LDR	X28, [X3, #8]

0x450af8 ADD	X30, X28, X30,LSL #3

0x450afc ADD	X1, X28, X18,LSL #3

0x450b00 SUB	X2, X30, X1

0x450b04 SUB	X3, X2, #8

0x450b08 UBFM	X2, X3, #3, #63

0x450b0c ADD	X3, X2, #1

0x450b10 ANDS	X2, X3, #4224

0x450b14 B.EQ	450ba8

0x450b18 CMP	X2, #1

0x450b1c B.EQ	450b94

0x450b20 CMP	X2, #2

0x450b24 B.EQ	450b88

0x450b28 CMP	X2, #3

0x450b2c B.EQ	450b7c

0x450b30 CMP	X2, #4

0x450b34 B.EQ	450b70

0x450b38 CMP	X2, #5

0x450b3c B.EQ	450b64

0x450b40 CMP	X2, #6

0x450b44 B.EQ	450b58

0x450b48 LDR	X18, [X28, X18,LSL #3]

0x450b4c ADD	X1, X1, #8

0x450b50 LDR	X28, [X21, X18,LSL #3]

0x450b54 STR	X0, [X19, X28,LSL #3]

0x450b58 LDR	X3, [X1], #8

0x450b5c LDR	X2, [X21, X3,LSL #3]

0x450b60 STR	X0, [X19, X2,LSL #3]

0x450b64 LDR	X18, [X1], #8

0x450b68 LDR	X28, [X21, X18,LSL #3]

0x450b6c STR	X0, [X19, X28,LSL #3]

0x450b70 LDR	X3, [X1], #8

0x450b74 LDR	X2, [X21, X3,LSL #3]

0x450b78 STR	X0, [X19, X2,LSL #3]

0x450b7c LDR	X18, [X1], #8

0x450b80 LDR	X28, [X21, X18,LSL #3]

0x450b84 STR	X0, [X19, X28,LSL #3]

0x450b88 LDR	X3, [X1], #8

0x450b8c LDR	X2, [X21, X3,LSL #3]

0x450b90 STR	X0, [X19, X2,LSL #3]

0x450b94 LDR	X18, [X1], #8

0x450b98 LDR	X28, [X21, X18,LSL #3]

0x450b9c STR	X0, [X19, X28,LSL #3]

0x450ba0 CMP	X30, X1

0x450ba4 B.EQ	450c18

  (859) 0x450ba8 ORR	X3, XZR, X1

  (859) 0x450bac ADD	X1, X1, #64

  (859) 0x450bb0 LDR	X2, [X3], #8

  (859) 0x450bb4 LDR	X18, [X21, X2,LSL #3]

  (859) 0x450bb8 STR	X0, [X19, X18,LSL #3]

  (859) 0x450bbc LDUR	X28, [X1, #456]

  (859) 0x450bc0 LDR	X2, [X21, X28,LSL #3]

  (859) 0x450bc4 STR	X0, [X19, X2,LSL #3]

  (859) 0x450bc8 LDR	X3, [X3, #8]

  (859) 0x450bcc LDR	X18, [X21, X3,LSL #3]

  (859) 0x450bd0 STR	X0, [X19, X18,LSL #3]

  (859) 0x450bd4 LDUR	X28, [X1, #472]

  (859) 0x450bd8 LDR	X2, [X21, X28,LSL #3]

  (859) 0x450bdc STR	X0, [X19, X2,LSL #3]

  (859) 0x450be0 LDUR	X3, [X1, #480]

  (859) 0x450be4 LDR	X18, [X21, X3,LSL #3]

  (859) 0x450be8 STR	X0, [X19, X18,LSL #3]

  (859) 0x450bec LDUR	X28, [X1, #488]

  (859) 0x450bf0 LDR	X2, [X21, X28,LSL #3]

  (859) 0x450bf4 STR	X0, [X19, X2,LSL #3]

  (859) 0x450bf8 LDUR	X3, [X1, #496]

  (859) 0x450bfc LDR	X18, [X21, X3,LSL #3]

  (859) 0x450c00 STR	X0, [X19, X18,LSL #3]

  (859) 0x450c04 LDUR	X28, [X1, #504]

  (859) 0x450c08 LDR	X2, [X21, X28,LSL #3]

  (859) 0x450c0c STR	X0, [X19, X2,LSL #3]

  (859) 0x450c10 CMP	X30, X1

  (859) 0x450c14 B.NE	450ba8

0x450c18 LDR	X3, [X11, X0,LSL #3]

0x450c1c ADD	X18, X12, X15

0x450c20 LDR	X1, [X12, X0,LSL #3]

0x450c24 LDR	X15, [X12, X15]

0x450c28 CMP	X1, X15

0x450c2c B.GE	4510a8

0x450c30 LDR	X30, [SP, #208]

0x450c34 CBZ	X30, 451014

0x450c38 LDR	X2, [SP, #112]

0x450c3c LDR	X28, [SP, #168]

0x450c40 LDR	X30, [SP, #192]

0x450c44 CMP	X2, #1

0x450c48 B.EQ	450fb4

0x450c4c STP	X7, X4, [SP, #120]

  (858) 0x450c50 LDR	X4, [X26, X1,LSL #3]

  (858) 0x450c54 LDR	X2, [X5, X4,LSL #3]

  (858) 0x450c58 LDR	X7, [X25, X2,LSL #3]

  (858) 0x450c5c CMN	X7, #3

  (858) 0x450c60 B.EQ	450c7c

  (858) 0x450c64 LDR	X4, [X13, X2,LSL #3]

  (858) 0x450c68 LDR	X7, [X27, X16]

  (858) 0x450c6c CMP	X4, X7

  (858) 0x450c70 B.NE	450c7c

  (858) 0x450c74 LDR	D16, [X6, X1,LSL #3]

  (858) 0x450c78 FADD	D0, D0, D16

  (858) 0x450c7c CMN	X2, #1

  (858) 0x450c80 B.EQ	450cb0

  (858) 0x450c84 LDR	X4, [X19, X2,LSL #3]

  (858) 0x450c88 CMP	X0, X4

  (858) 0x450c8c B.NE	450cb0

  (858) 0x450c90 LDR	D17, [X6, X1,LSL #3]

  (858) 0x450c94 UBFM	X15, X3, #61, #60

  (858) 0x450c98 LDR	X7, [X28, X2,LSL #3]

  (858) 0x450c9c FADD	D1, D1, D17

  (858) 0x450ca0 STR	D17, [X9, X3,LSL #3]

  (858) 0x450ca4 ADD	X3, X3, #1

  (858) 0x450ca8 STR	X7, [X30, X15]

  (858) 0x450cac LDR	X15, [X18]

  (858) 0x450cb0 ADD	X1, X1, #1

  (858) 0x450cb4 CMP	X15, X1

  (858) 0x450cb8 B.GT	450c50

0x450cbc LDP	X7, X4, [SP, #120]

0x450cc0 LDR	X18, [X11, X0,LSL #3]

0x450cc4 LDR	X1, [X7, X0,LSL #3]

0x450cc8 LDR	D22, [X4, X1,LSL #3]

0x450ccc FMUL	D23, D1, D22

0x450cd0 FCMP	D23, #0

0x450cd4 B.EQ	450ce0

0x450cd8 FNEG	D8, D0

0x450cdc FDIV	D8, D8, D23

0x450ce0 LDR	X16, [X8, X0,LSL #3]

0x450ce4 CMP	X16, X14

0x450ce8 B.GE	450dfc

0x450cec ADD	X14, X10, X14,LSL #3

0x450cf0 ADD	X0, X10, X16,LSL #3

0x450cf4 SUB	X28, X14, X0

0x450cf8 SUB	X30, X28, #8

0x450cfc UBFM	X15, X30, #3, #63

0x450d00 ADD	X2, X15, #1

0x450d04 ANDS	X1, X2, #4224

0x450d08 B.EQ	450d9c

0x450d0c CMP	X1, #1

0x450d10 B.EQ	450d88

0x450d14 CMP	X1, #2

0x450d18 B.EQ	450d7c

0x450d1c CMP	X1, #3

0x450d20 B.EQ	450d70

0x450d24 CMP	X1, #4

0x450d28 B.EQ	450d64

0x450d2c CMP	X1, #5

0x450d30 B.EQ	450d58

0x450d34 CMP	X1, #6

0x450d38 B.EQ	450d4c

0x450d3c LDR	D24, [X10, X16,LSL #3]

0x450d40 ADD	X0, X0, #8

0x450d44 FMUL	D25, D24, D8

0x450d48 STR	D25, [X10, X16,LSL #3]

0x450d4c LDR	D26, [X0]

0x450d50 FMUL	D27, D26, D8

0x450d54 STR	D27, [X0], #8

0x450d58 LDR	D28, [X0]

0x450d5c FMUL	D29, D28, D8

0x450d60 STR	D29, [X0], #8

0x450d64 LDR	D30, [X0]

0x450d68 FMUL	D31, D30, D8

0x450d6c STR	D31, [X0], #8

0x450d70 LDR	D2, [X0]

0x450d74 FMUL	D0, D2, D8

0x450d78 STR	D0, [X0], #8

0x450d7c LDR	D3, [X0]

0x450d80 FMUL	D1, D3, D8

0x450d84 STR	D1, [X0], #8

0x450d88 LDR	D4, [X0]

0x450d8c FMUL	D5, D4, D8

0x450d90 STR	D5, [X0], #8

0x450d94 CMP	X14, X0

0x450d98 B.EQ	450dfc

  (854) 0x450d9c LDR	D6, [X0]

  (854) 0x450da0 ORR	X16, XZR, X0

  (854) 0x450da4 FMUL	D7, D6, D8

  (854) 0x450da8 STR	D7, [X16], #8

  (854) 0x450dac LDR	D16, [X0, #8]

  (854) 0x450db0 FMUL	D17, D16, D8

  (854) 0x450db4 STR	D17, [X0, #8]

  (854) 0x450db8 LDR	D18, [X16, #8]

  (854) 0x450dbc FMUL	D19, D18, D8

  (854) 0x450dc0 STR	D19, [X16, #8]

  (854) 0x450dc4 LDP	D20, D21, [X0, #24]

  (854) 0x450dc8 LDP	D22, D23, [X0, #40]

  (854) 0x450dcc LDR	D24, [X0, #56]

  (854) 0x450dd0 FMUL	D25, D20, D8

  (854) 0x450dd4 FMUL	D26, D21, D8

  (854) 0x450dd8 FMUL	D27, D22, D8

  (854) 0x450ddc FMUL	D28, D23, D8

  (854) 0x450de0 FMUL	D29, D24, D8

  (854) 0x450de4 STP	D25, D26, [X0, #24]

  (854) 0x450de8 STP	D27, D28, [X0, #40]

  (854) 0x450dec ADD	X0, X0, #64

  (854) 0x450df0 STUR	D29, [X0, #504]

  (854) 0x450df4 CMP	X14, X0

  (854) 0x450df8 B.NE	450d9c

0x450dfc CMP	X3, X18

0x450e00 B.LE	450f18

0x450e04 ADD	X3, X9, X3,LSL #3

0x450e08 UBFM	X18, X18, #61, #60

0x450e0c ADD	X0, X9, X18

0x450e10 SUB	X14, X3, X0

0x450e14 SUB	X28, X14, #8

0x450e18 UBFM	X30, X28, #3, #63

0x450e1c ADD	X15, X30, #1

0x450e20 ANDS	X2, X15, #4224

0x450e24 B.EQ	450eb8

0x450e28 CMP	X2, #1

0x450e2c B.EQ	450ea4

0x450e30 CMP	X2, #2

0x450e34 B.EQ	450e98

0x450e38 CMP	X2, #3

0x450e3c B.EQ	450e8c

0x450e40 CMP	X2, #4

0x450e44 B.EQ	450e80

0x450e48 CMP	X2, #5

0x450e4c B.EQ	450e74

0x450e50 CMP	X2, #6

0x450e54 B.EQ	450e68

0x450e58 LDR	D30, [X9, X18]

0x450e5c ADD	X0, X0, #8

0x450e60 FMUL	D31, D30, D8

0x450e64 STR	D31, [X9, X18]

0x450e68 LDR	D2, [X0]

0x450e6c FMUL	D0, D2, D8

0x450e70 STR	D0, [X0], #8

0x450e74 LDR	D3, [X0]

0x450e78 FMUL	D1, D3, D8

0x450e7c STR	D1, [X0], #8

0x450e80 LDR	D4, [X0]

0x450e84 FMUL	D5, D4, D8

0x450e88 STR	D5, [X0], #8

0x450e8c LDR	D6, [X0]

0x450e90 FMUL	D7, D6, D8

0x450e94 STR	D7, [X0], #8

0x450e98 LDR	D16, [X0]

0x450e9c FMUL	D17, D16, D8

0x450ea0 STR	D17, [X0], #8

0x450ea4 LDR	D18, [X0]

0x450ea8 FMUL	D19, D18, D8

0x450eac STR	D19, [X0], #8

0x450eb0 CMP	X3, X0

0x450eb4 B.EQ	450f18

  (853) 0x450eb8 LDR	D20, [X0]

  (853) 0x450ebc ORR	X1, XZR, X0

  (853) 0x450ec0 FMUL	D21, D20, D8

  (853) 0x450ec4 STR	D21, [X1], #8

  (853) 0x450ec8 LDR	D22, [X0, #8]

  (853) 0x450ecc FMUL	D23, D22, D8

  (853) 0x450ed0 STR	D23, [X0, #8]

  (853) 0x450ed4 LDR	D24, [X1, #8]

  (853) 0x450ed8 FMUL	D25, D24, D8

  (853) 0x450edc STR	D25, [X1, #8]

  (853) 0x450ee0 LDP	D26, D27, [X0, #24]

  (853) 0x450ee4 LDP	D28, D29, [X0, #40]

  (853) 0x450ee8 LDR	D30, [X0, #56]

  (853) 0x450eec FMUL	D31, D26, D8

  (853) 0x450ef0 FMUL	D3, D27, D8

  (853) 0x450ef4 FMUL	D2, D28, D8

  (853) 0x450ef8 FMUL	D1, D29, D8

  (853) 0x450efc FMUL	D0, D30, D8

  (853) 0x450f00 STP	D31, D3, [X0, #24]

  (853) 0x450f04 STP	D2, D1, [X0, #40]

  (853) 0x450f08 ADD	X0, X0, #64

  (853) 0x450f0c STUR	D0, [X0, #504]

  (853) 0x450f10 CMP	X3, X0

  (853) 0x450f14 B.NE	450eb8

0x450f18 LDR	X16, [SP, #152]

0x450f1c ADD	X17, X17, #8

0x450f20 CMP	X16, X17

0x450f24 B.NE	4508d0

  (860) 0x450f54 LDR	X2, [X23, X1,LSL #3]

  (860) 0x450f58 LDR	X5, [X24, X2,LSL #3]

  (860) 0x450f5c CMN	X5, #3

  (860) 0x450f60 B.EQ	450f6c

  (860) 0x450f64 LDR	D2, [X4, X1,LSL #3]

  (860) 0x450f68 FADD	D0, D0, D2

  (860) 0x450f6c CMN	X2, #1

  (860) 0x450f70 B.EQ	450fa0

  (860) 0x450f74 LDR	X5, [X20, X2,LSL #3]

  (860) 0x450f78 CMP	X0, X5

  (860) 0x450f7c B.NE	450fa0

  (860) 0x450f80 LDR	D3, [X4, X1,LSL #3]

  (860) 0x450f84 UBFM	X3, X14, #61, #60

  (860) 0x450f88 LDR	X2, [X18, X2,LSL #3]

  (860) 0x450f8c FADD	D1, D1, D3

  (860) 0x450f90 STR	D3, [X10, X14,LSL #3]

  (860) 0x450f94 ADD	X14, X14, #1

  (860) 0x450f98 STR	X2, [X28, X3]

  (860) 0x450f9c LDR	X3, [X30]

  (860) 0x450fa0 ADD	X1, X1, #1

  (860) 0x450fa4 CMP	X3, X1

  (860) 0x450fa8 B.GT	450f54

0x450fac LDR	X5, [SP, #120]

0x450fb0 B	450ad0

  (857) 0x450fb4 LDR	X16, [X26, X1,LSL #3]

  (857) 0x450fb8 LDR	X2, [X5, X16,LSL #3]

  (857) 0x450fbc LDR	X16, [X25, X2,LSL #3]

  (857) 0x450fc0 CMN	X16, #3

  (857) 0x450fc4 B.EQ	450fd0

  (857) 0x450fc8 LDR	D6, [X6, X1,LSL #3]

  (857) 0x450fcc FADD	D0, D0, D6

  (857) 0x450fd0 CMN	X2, #1

  (857) 0x450fd4 B.EQ	451004

  (857) 0x450fd8 LDR	X16, [X19, X2,LSL #3]

  (857) 0x450fdc CMP	X0, X16

  (857) 0x450fe0 B.NE	451004

  (857) 0x450fe4 LDR	D7, [X6, X1,LSL #3]

  (857) 0x450fe8 UBFM	X15, X3, #61, #60

  (857) 0x450fec LDR	X16, [X28, X2,LSL #3]

  (857) 0x450ff0 FADD	D1, D1, D7

  (857) 0x450ff4 STR	D7, [X9, X3,LSL #3]

  (857) 0x450ff8 ADD	X3, X3, #1

  (857) 0x450ffc STR	X16, [X30, X15]

  (857) 0x451000 LDR	X15, [X18]

  (857) 0x451004 ADD	X1, X1, #1

  (857) 0x451008 CMP	X15, X1

  (857) 0x45100c B.GT	450fb4

0x451010 B	450cc0

0x451014 LDR	X2, [SP, #112]

0x451018 CMP	X2, #1

0x45101c B.EQ	4510b0

0x451020 LDR	X28, [SP, #168]

0x451024 STP	X5, X4, [SP, #120]

0x451028 LDR	X30, [SP, #192]

  (856) 0x45102c LDR	X2, [X26, X1,LSL #3]

  (856) 0x451030 LDR	X5, [X25, X2,LSL #3]

  (856) 0x451034 CMN	X5, #3

  (856) 0x451038 B.EQ	451054

  (856) 0x45103c LDR	X4, [X13, X2,LSL #3]

  (856) 0x451040 LDR	X5, [X27, X16]

  (856) 0x451044 CMP	X4, X5

  (856) 0x451048 B.NE	451054

  (856) 0x45104c LDR	D20, [X6, X1,LSL #3]

  (856) 0x451050 FADD	D0, D0, D20

  (856) 0x451054 CMN	X2, #1

  (856) 0x451058 B.EQ	451088

  (856) 0x45105c LDR	X4, [X19, X2,LSL #3]

  (856) 0x451060 CMP	X0, X4

  (856) 0x451064 B.NE	451088

  (856) 0x451068 LDR	D21, [X6, X1,LSL #3]

  (856) 0x45106c UBFM	X15, X3, #61, #60

  (856) 0x451070 LDR	X2, [X28, X2,LSL #3]

  (856) 0x451074 FADD	D1, D1, D21

  (856) 0x451078 STR	D21, [X9, X3,LSL #3]

  (856) 0x45107c ADD	X3, X3, #1

  (856) 0x451080 STR	X2, [X30, X15]

  (856) 0x451084 LDR	X15, [X18]

  (856) 0x451088 ADD	X1, X1, #1

  (856) 0x45108c CMP	X15, X1

  (856) 0x451090 B.GT	45102c

0x451094 LDP	X5, X4, [SP, #120]

0x451098 B	450cc0

0x45109c MOVI	D0, #0

0x4510a0 FMOV	D1, D0

0x4510a4 B	450ad0

0x4510a8 ORR	X18, XZR, X3

0x4510ac B	450cc4

0x4510b0 LDR	X28, [SP, #168]

0x4510b4 LDR	X30, [SP, #192]

0x4510b8 HINT	#0

0x4510bc HINT	#0

  (855) 0x4510c0 LDR	X2, [X26, X1,LSL #3]

  (855) 0x4510c4 LDR	X16, [X25, X2,LSL #3]

  (855) 0x4510c8 CMN	X16, #3

  (855) 0x4510cc B.EQ	4510d8

  (855) 0x4510d0 LDR	D18, [X6, X1,LSL #3]

  (855) 0x4510d4 FADD	D0, D0, D18

  (855) 0x4510d8 CMN	X2, #1

  (855) 0x4510dc B.EQ	45110c

  (855) 0x4510e0 LDR	X16, [X19, X2,LSL #3]

  (855) 0x4510e4 CMP	X0, X16

  (855) 0x4510e8 B.NE	45110c

  (855) 0x4510ec LDR	D19, [X6, X1,LSL #3]

  (855) 0x4510f0 UBFM	X15, X3, #61, #60

  (855) 0x4510f4 LDR	X16, [X28, X2,LSL #3]

  (855) 0x4510f8 FADD	D1, D1, D19

  (855) 0x4510fc STR	D19, [X9, X3,LSL #3]

  (855) 0x451100 ADD	X3, X3, #1

  (855) 0x451104 STR	X16, [X30, X15]

  (855) 0x451108 LDR	X15, [X18]

  (855) 0x45110c ADD	X1, X1, #1

  (855) 0x451110 CMP	X15, X1

  (855) 0x451114 B.GT	4510c0

0x451118 B	450cc0

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1605 - 1660

--------------------------------------------------------------------------------

1605:            for (i=thread_start; i < thread_stop; i++)

1606:            {

1607:              i1 = pass_array[i];

1608:              sum_C = 0;

1609:              sum_N = 0;

1610:              j_start = P_diag_start[i1];

1611:              j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1612:              for (j=j_start; j < j_end; j++)

1613:              {

1614:                 k1 = P_diag_pass[1][j];

1615:                 tmp_marker[C_array[k1]] = i1;

1616:              }

1617:              cnt = P_diag_i[i1];

1618:              for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1619:              {

1620:                 j1 = A_diag_j[j];

1621:                 if (CF_marker[j1] != -3 &&

1622:                    (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1623:                    sum_N += A_diag_data[j];

1624:                 if (j1 != -1 && tmp_marker[j1] == i1)

1625:                 {

1626:                    P_diag_data[cnt] = A_diag_data[j];

1627:                    P_diag_j[cnt++] = fine_to_coarse[j1];

1628:                    sum_C += A_diag_data[j];

1629:                 }

1630:              }

1631:              j_start = P_offd_start[i1];

1632:              j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1633:              for (j=j_start; j < j_end; j++)

1634:              {

1635:                 k1 = P_offd_pass[1][j];

1636:                 tmp_marker_offd[C_array_offd[k1]] = i1;

1637:              }

1638:              cnt_offd = P_offd_i[i1];

1639:              for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1640:              {

1641:                 if (col_offd_S_to_A)

1642:                     j1 = map_A_to_S[A_offd_j[j]];

1643:                 else

1644:                     j1 = A_offd_j[j];

1645:                 if (CF_marker_offd[j1] != -3 &&

1646:                   (num_functions == 1 || dof_func[i1] == dof_func_offd[j1]))

1647:                     sum_N += A_offd_data[j];

1648:                 if (j1 != -1 && tmp_marker_offd[j1] == i1)

1649:                 {

1650:                    P_offd_data[cnt_offd] = A_offd_data[j];

1651:                    P_offd_j[cnt_offd++] = map_S_to_new[j1];

1652:                    sum_C += A_offd_data[j];

1653:                 }

1654:              }

1655:              diagonal = A_diag_data[A_diag_i[i1]];

1656:              if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1657:              for (j=P_diag_i[i1]; j < cnt; j++)

1658:                 P_diag_data[j] *= alfa;

1659:              for (j=P_offd_i[i1]; j < cnt_offd; j++)

1660:                 P_offd_data[j] *= alfa;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	2.85
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.9
Source	par_multi_interp.c:1605-1618,par_multi_interp.c:1631-1639,par_multi_interp.c:1655-1660
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	38.00
CQA cycles if no scalar integer	13.33
CQA cycles if FP arith vectorized	38.00
CQA cycles if fully vectorized	9.50
Front-end cycles	33.50
DIV/SQRT cycles	25.00
P0 cycles	25.00
P1 cycles	23.50
P2 cycles	23.50
P3 cycles	23.50
P4 cycles	23.50
P5 cycles	9.00
P6 cycles	9.00
P7 cycles	9.00
P8 cycles	9.00
P9 cycles	38.00
P10 cycles	38.00
P11 cycles	38.00
P12 cycles	9.00
P13 cycles	9.00
P14 cycles	1.75 - 3.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	270.00
Nb uops	268.00
Nb loads	NA
Nb stores	32.00
Nb stack references	0.00
FLOP/cycle	0.42
Nb FLOP add-sub	0.00
Nb FLOP mul	15.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.05
Bytes prefetched	0.00
Bytes loaded	680.00
Bytes stored	272.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	2.85
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.9
Source	par_multi_interp.c:1605-1618,par_multi_interp.c:1631-1639,par_multi_interp.c:1655-1660
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	38.00
CQA cycles if no scalar integer	13.33
CQA cycles if FP arith vectorized	38.00
CQA cycles if fully vectorized	9.50
Front-end cycles	33.50
DIV/SQRT cycles	25.00
P0 cycles	25.00
P1 cycles	23.50
P2 cycles	23.50
P3 cycles	23.50
P4 cycles	23.50
P5 cycles	9.00
P6 cycles	9.00
P7 cycles	9.00
P8 cycles	9.00
P9 cycles	38.00
P10 cycles	38.00
P11 cycles	38.00
P12 cycles	9.00
P13 cycles	9.00
P14 cycles	1.75 - 3.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	270.00
Nb uops	268.00
Nb loads	NA
Nb stores	32.00
Nb stack references	0.00
FLOP/cycle	0.42
Nb FLOP add-sub	0.00
Nb FLOP mul	15.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.05
Bytes prefetched	0.00
Bytes loaded	680.00
Bytes stored	272.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass._omp_fn.9
Source file and lines	par_multi_interp.c:1605-1660
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1605-1660.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1605-1618,1631-1639,1655-1660.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 38.00 to 13.33 cycles (2.85x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 38.00 to 9.50 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

15: multiply
1: divide

The binary loop is loading 680 bytes. The binary loop is storing 272 bytes.

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	270
loop length	1080
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

33.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	25.00	25.00	23.50	23.50	23.50	23.50	9.00	9.00	9.00	9.00	38.00	38.00	38.00	9.00	9.00
cycles	25.00	25.00	23.50	23.50	23.50	23.50	9.00	9.00	9.00	9.00	38.00	38.00	38.00	9.00	9.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.75-3.50

Cycles summary

Front-end	33.50
Overall L1	38.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 38.00 cycles. At this rate:

18% of peak load performance is reached (17.89 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (7.16 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4508d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X0, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X16, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X2, [X8, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X28, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X30, X18, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X28, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 450a28 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X14, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X18, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X18, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X2, X3, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X30, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X14, X30, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X30, X2, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4509b4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x224>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4509a0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X30, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450994 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X30, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450988 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X30, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 45097c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X30, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450970 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X30, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450964 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x1d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X28, [X18, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X18, [X22, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X20, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X22, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X20, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X30, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X22, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X20, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X22, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X20, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X2, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X22, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X20, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X28, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X22, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X20, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X22, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X20, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X3, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450a24 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x294>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X30, X7, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X7, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X1, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 45109c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x90c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR X5, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FMOV D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR X28, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450f54 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x7c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X6, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X5, X6, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X1, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X11, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X28, X18, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X30, X28, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X18, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 450c1c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x48c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X3, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X3, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X30, X28, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X28, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X2, X30, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X2, X3, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X2, X3, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450ba8 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x418>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450b94 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x404>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450b88 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x3f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450b7c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x3ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450b70 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x3e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450b64 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x3d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450b58 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x3c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X28, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X28, [X21, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X19, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X21, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X21, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X19, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X21, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X21, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X19, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X21, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X21, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X19, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X30, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450c18 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x488>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X3, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X12, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X12, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X12, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X1, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4510a8 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x918>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X30, 451014 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x884>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450fb4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x824>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X7, X4, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X7, X4, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X18, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D22, [X4, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D23, D1, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FCMP D23, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.EQ 450ce0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x550>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FNEG D8, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FDIV D8, D8, D23	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50
LDR X16, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X16, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 450dfc <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x66c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X14, X10, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X10, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X28, X14, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X30, X28, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X15, X30, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X1, X2, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450d9c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x60c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450d88 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x5f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450d7c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x5ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450d70 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x5e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X1, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450d64 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x5d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X1, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450d58 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x5c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X1, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450d4c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x5bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D24, [X10, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMUL D25, D24, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D25, [X10, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D26, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D27, D26, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D27, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D28, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D29, D28, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D29, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D30, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D31, D30, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D31, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D2, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D0, D2, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D0, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D3, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D1, D3, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D1, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D4, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D5, D4, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D5, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP X14, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450dfc <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x66c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 450f18 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x788>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X3, X9, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X18, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X9, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X14, X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X28, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X30, X28, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X2, X15, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450eb8 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x728>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450ea4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450e98 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x708>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450e8c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x6fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450e80 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x6f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450e74 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x6e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450e68 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x6d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D30, [X9, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMUL D31, D30, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D31, [X9, X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D2, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D0, D2, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D0, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D3, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D1, D3, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D1, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D4, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D5, D4, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D5, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D6, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D7, D6, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D7, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D16, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D17, D16, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D17, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D18, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D19, D18, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D19, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450f18 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x788>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X16, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X17, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X16, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 4508d0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X5, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 450ad0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x340>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450cc0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x530>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4510b0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x920>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X28, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X5, X4, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X30, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X5, X4, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 450cc0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x530>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
B 450ad0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x340>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X18, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 450cc4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x534>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X28, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
HINT #0
B 450cc0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x530>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_BoomerAMGBuildMultipass._omp_fn.9
Source file and lines	par_multi_interp.c:1605-1660
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control.

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

15: multiply
1: divide

The binary loop is loading 680 bytes. The binary loop is storing 272 bytes.

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	270
loop length	1080
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

33.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	25.00	25.00	23.50	23.50	23.50	23.50	9.00	9.00	9.00	9.00	38.00	38.00	38.00	9.00	9.00
cycles	25.00	25.00	23.50	23.50	23.50	23.50	9.00	9.00	9.00	9.00	38.00	38.00	38.00	9.00	9.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.75-3.50

Cycles summary

Front-end	33.50
Overall L1	38.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 38.00 cycles. At this rate:

18% of peak load performance is reached (17.89 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (7.16 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4508d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X0, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X16, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X2, [X8, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X28, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X30, X18, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X28, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 450a28 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X14, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X18, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X18, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X2, X3, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X30, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X14, X30, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X30, X2, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4509b4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x224>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4509a0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X30, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450994 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X30, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450988 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X30, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 45097c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X30, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450970 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X30, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450964 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x1d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X28, [X18, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X18, [X22, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X20, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X22, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X20, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X30, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X22, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X20, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X22, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X20, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X2, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X22, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X20, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X28, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X22, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X20, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X22, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X20, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X3, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450a24 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x294>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X30, X7, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X7, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X1, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 45109c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x90c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR X5, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FMOV D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR X28, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450f54 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x7c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X6, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X5, X6, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X1, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X11, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X28, X18, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X30, X28, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X18, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 450c1c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x48c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X3, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X3, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X30, X28, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X28, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X2, X30, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X2, X3, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X2, X3, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450ba8 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x418>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450b94 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x404>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450b88 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x3f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450b7c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x3ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450b70 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x3e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450b64 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x3d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450b58 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x3c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X28, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X28, [X21, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X19, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X21, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X21, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X19, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X21, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X21, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X19, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X21, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X1], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X21, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X19, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X30, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450c18 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x488>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X3, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X12, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X12, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X12, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X1, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4510a8 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x918>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X30, 451014 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x884>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450fb4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x824>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X7, X4, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X7, X4, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X18, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D22, [X4, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D23, D1, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FCMP D23, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.EQ 450ce0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x550>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FNEG D8, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FDIV D8, D8, D23	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50
LDR X16, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X16, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 450dfc <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x66c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X14, X10, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X10, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X28, X14, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X30, X28, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X15, X30, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X1, X2, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450d9c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x60c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450d88 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x5f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450d7c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x5ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450d70 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x5e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X1, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450d64 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x5d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X1, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450d58 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x5c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X1, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450d4c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x5bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D24, [X10, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMUL D25, D24, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D25, [X10, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D26, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D27, D26, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D27, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D28, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D29, D28, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D29, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D30, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D31, D30, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D31, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D2, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D0, D2, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D0, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D3, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D1, D3, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D1, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D4, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D5, D4, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D5, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP X14, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450dfc <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x66c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 450f18 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x788>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X3, X9, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X18, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X9, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X14, X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X28, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X30, X28, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X2, X15, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450eb8 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x728>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450ea4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450e98 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x708>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450e8c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x6fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450e80 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x6f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450e74 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x6e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450e68 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x6d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D30, [X9, X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMUL D31, D30, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D31, [X9, X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D2, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D0, D2, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D0, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D3, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D1, D3, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D1, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D4, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D5, D4, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D5, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D6, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D7, D6, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D7, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D16, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D17, D16, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D17, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D18, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D19, D18, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D19, [X0], #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 450f18 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x788>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X16, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X17, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X16, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 4508d0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X5, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 450ad0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x340>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 450cc0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x530>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4510b0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x920>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X28, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X5, X4, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X30, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X5, X4, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 450cc0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x530>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
B 450ad0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x340>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X18, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 450cc4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x534>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X28, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
HINT #0
B 450cc0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x530>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code