OV - exec - Loop 845

	Loop Id: 845	Module: exec	Source: par_multi_interp.c:1811-1837	Coverage: 0.65%

0x44fd74 LDR	X8, [X28, X2,LSL #3]

0x44fd78 LDR	X30, [X28, X11]

0x44fd7c CMP	X30, X8

0x44fd80 B.EQ	44fdb8

0x44fd84 ADD	X1, X1, #1

0x44fd88 CMP	X1, X7

0x44fd8c B.EQ	44fdcc

0x44fd90 LDR	X2, [X9, X1,LSL #3]

0x44fd94 LDR	X15, [X26, X2,LSL #3]

0x44fd98 UBFM	X14, X2, #61, #60

0x44fd9c CMP	X3, X15

0x44fda0 B.EQ	450158

0x44fda4 LDR	X17, [X13, X2,LSL #3]

0x44fda8 CMN	X17, #3

0x44fdac B.EQ	44fd84

0x44fdb0 CMP	X0, #1

0x44fdb4 B.NE	44fd74

0x44fdb8 LDR	D2, [X21, X1,LSL #3]

0x44fdbc ADD	X1, X1, #1

0x44fdc0 FADD	D0, D0, D2

0x44fdc4 CMP	X1, X7

0x44fdc8 B.NE	44fd90

0x450158 LDR	X16, [SP, #152]

0x45015c ADD	X5, X14, #8

0x450160 LDR	X4, [X16, X2,LSL #3]

0x450164 LDR	X17, [X16, X5]

0x450168 CMP	X4, X17

0x45016c B.GE	4502d0

0x450170 SUB	X15, X17, X4

0x450174 ANDS	X14, X15, #4160

0x450178 B.EQ	450218

0x45017c CMP	X14, #1

0x450180 B.EQ	4501e4

0x450184 CMP	X14, #2

0x450188 B.EQ	4501b8

0x45018c LDR	X8, [X25, X4,LSL #3]

0x450190 LDR	D3, [X20, X4,LSL #3]

0x450194 ADD	X4, X4, #1

0x450198 LDR	D4, [X21, X1,LSL #3]

0x45019c LDR	X30, [X23, X8,LSL #3]

0x4501a0 FMUL	D5, D4, D3

0x4501a4 LDR	D6, [X20, X30,LSL #3]

0x4501a8 FADD	D1, D1, D5

0x4501ac FADD	D0, D0, D5

0x4501b0 FADD	D7, D6, D5

0x4501b4 STR	D7, [X20, X30,LSL #3]

0x4501b8 LDR	X16, [X25, X4,LSL #3]

0x4501bc LDR	D16, [X20, X4,LSL #3]

0x4501c0 ADD	X4, X4, #1

0x4501c4 LDR	D8, [X21, X1,LSL #3]

0x4501c8 LDR	X15, [X23, X16,LSL #3]

0x4501cc FMUL	D17, D8, D16

0x4501d0 LDR	D18, [X20, X15,LSL #3]

0x4501d4 FADD	D1, D1, D17

0x4501d8 FADD	D0, D0, D17

0x4501dc FADD	D19, D18, D17

0x4501e0 STR	D19, [X20, X15,LSL #3]

0x4501e4 LDR	X14, [X25, X4,LSL #3]

0x4501e8 LDR	D21, [X20, X4,LSL #3]

0x4501ec ADD	X4, X4, #1

0x4501f0 LDR	D20, [X21, X1,LSL #3]

0x4501f4 LDR	X8, [X23, X14,LSL #3]

0x4501f8 FMUL	D8, D20, D21

0x4501fc LDR	D22, [X20, X8,LSL #3]

0x450200 FADD	D1, D1, D8

0x450204 FADD	D0, D0, D8

0x450208 FADD	D23, D22, D8

0x45020c STR	D23, [X20, X8,LSL #3]

0x450210 CMP	X4, X17

0x450214 B.EQ	4502d0

  (847) 0x450218 LDR	X30, [X25, X4,LSL #3]

  (847) 0x45021c ADD	X8, X4, #1

  (847) 0x450220 ADD	X14, X4, #3

  (847) 0x450224 ADD	X15, X8, #1

  (847) 0x450228 LDR	D25, [X20, X4,LSL #3]

  (847) 0x45022c ADD	X4, X4, #4

  (847) 0x450230 LDR	D24, [X21, X1,LSL #3]

  (847) 0x450234 LDR	X30, [X23, X30,LSL #3]

  (847) 0x450238 LDR	X16, [X25, X8,LSL #3]

  (847) 0x45023c FMUL	D26, D24, D25

  (847) 0x450240 LDR	D27, [X20, X30,LSL #3]

  (847) 0x450244 LDR	X16, [X23, X16,LSL #3]

  (847) 0x450248 FADD	D28, D1, D26

  (847) 0x45024c FADD	D29, D0, D26

  (847) 0x450250 FADD	D30, D27, D26

  (847) 0x450254 STR	D30, [X20, X30,LSL #3]

  (847) 0x450258 LDR	D2, [X20, X8,LSL #3]

  (847) 0x45025c LDR	D31, [X21, X1,LSL #3]

  (847) 0x450260 LDR	D4, [X20, X16,LSL #3]

  (847) 0x450264 LDR	X30, [X25, X15,LSL #3]

  (847) 0x450268 FMUL	D5, D31, D2

  (847) 0x45026c LDR	X8, [X25, X14,LSL #3]

  (847) 0x450270 LDR	X30, [X23, X30,LSL #3]

  (847) 0x450274 LDR	X8, [X23, X8,LSL #3]

  (847) 0x450278 FADD	D3, D4, D5

  (847) 0x45027c FADD	D6, D28, D5

  (847) 0x450280 FADD	D7, D29, D5

  (847) 0x450284 STR	D3, [X20, X16,LSL #3]

  (847) 0x450288 LDR	D8, [X21, X1,LSL #3]

  (847) 0x45028c LDR	D16, [X20, X15,LSL #3]

  (847) 0x450290 LDR	D17, [X20, X30,LSL #3]

  (847) 0x450294 FMUL	D18, D8, D16

  (847) 0x450298 FADD	D19, D17, D18

  (847) 0x45029c FADD	D20, D6, D18

  (847) 0x4502a0 FADD	D21, D7, D18

  (847) 0x4502a4 STR	D19, [X20, X30,LSL #3]

  (847) 0x4502a8 LDR	D1, [X20, X14,LSL #3]

  (847) 0x4502ac LDR	D22, [X21, X1,LSL #3]

  (847) 0x4502b0 LDR	D0, [X20, X8,LSL #3]

  (847) 0x4502b4 FMUL	D8, D22, D1

  (847) 0x4502b8 FADD	D23, D0, D8

  (847) 0x4502bc FADD	D1, D20, D8

  (847) 0x4502c0 FADD	D0, D21, D8

  (847) 0x4502c4 STR	D23, [X20, X8,LSL #3]

  (847) 0x4502c8 CMP	X4, X17

  (847) 0x4502cc B.NE	450218

0x4502d0 LDR	X17, [SP, #144]

0x4502d4 LDR	X2, [X17, X2,LSL #3]

0x4502d8 LDR	X15, [X17, X5]

0x4502dc CMP	X2, X15

0x4502e0 B.GE	44fd84

0x4502e4 SUB	X5, X15, X2

0x4502e8 ANDS	X4, X5, #4160

0x4502ec B.EQ	45038c

0x4502f0 CMP	X4, #1

0x4502f4 B.EQ	450358

0x4502f8 CMP	X4, #2

0x4502fc B.EQ	45032c

0x450300 LDR	X14, [X24, X2,LSL #3]

0x450304 LDR	D25, [X19, X2,LSL #3]

0x450308 ADD	X2, X2, #1

0x45030c LDR	D24, [X21, X1,LSL #3]

0x450310 LDR	X16, [X22, X14,LSL #3]

0x450314 FMUL	D26, D24, D25

0x450318 LDR	D27, [X19, X16,LSL #3]

0x45031c FADD	D1, D1, D26

0x450320 FADD	D0, D0, D26

0x450324 FADD	D28, D27, D26

0x450328 STR	D28, [X19, X16,LSL #3]

0x45032c LDR	X30, [X24, X2,LSL #3]

0x450330 LDR	D30, [X19, X2,LSL #3]

0x450334 ADD	X2, X2, #1

0x450338 LDR	D29, [X21, X1,LSL #3]

0x45033c LDR	X8, [X22, X30,LSL #3]

0x450340 FMUL	D31, D29, D30

0x450344 LDR	D2, [X19, X8,LSL #3]

0x450348 FADD	D1, D1, D31

0x45034c FADD	D0, D0, D31

0x450350 FADD	D4, D2, D31

0x450354 STR	D4, [X19, X8,LSL #3]

0x450358 LDR	X17, [X24, X2,LSL #3]

0x45035c LDR	D3, [X19, X2,LSL #3]

0x450360 ADD	X2, X2, #1

0x450364 LDR	D5, [X21, X1,LSL #3]

0x450368 LDR	X5, [X22, X17,LSL #3]

0x45036c FMUL	D8, D5, D3

0x450370 LDR	D6, [X19, X5,LSL #3]

0x450374 FADD	D1, D1, D8

0x450378 FADD	D0, D0, D8

0x45037c FADD	D7, D6, D8

0x450380 STR	D7, [X19, X5,LSL #3]

0x450384 CMP	X2, X15

0x450388 B.EQ	44fd84

  (846) 0x45038c LDR	X14, [X24, X2,LSL #3]

  (846) 0x450390 ADD	X4, X2, #1

  (846) 0x450394 ADD	X30, X2, #3

  (846) 0x450398 ADD	X17, X4, #1

  (846) 0x45039c LDR	D8, [X21, X1,LSL #3]

  (846) 0x4503a0 LDR	D16, [X19, X2,LSL #3]

  (846) 0x4503a4 ADD	X2, X2, #4

  (846) 0x4503a8 LDR	X8, [X22, X14,LSL #3]

  (846) 0x4503ac LDR	X16, [X24, X4,LSL #3]

  (846) 0x4503b0 FMUL	D17, D8, D16

  (846) 0x4503b4 LDR	X14, [X24, X17,LSL #3]

  (846) 0x4503b8 LDR	D18, [X19, X8,LSL #3]

  (846) 0x4503bc LDR	X5, [X22, X16,LSL #3]

  (846) 0x4503c0 FADD	D19, D1, D17

  (846) 0x4503c4 FADD	D20, D0, D17

  (846) 0x4503c8 FADD	D21, D18, D17

  (846) 0x4503cc STR	D21, [X19, X8,LSL #3]

  (846) 0x4503d0 LDR	D1, [X19, X4,LSL #3]

  (846) 0x4503d4 LDR	D22, [X21, X1,LSL #3]

  (846) 0x4503d8 LDR	D0, [X19, X5,LSL #3]

  (846) 0x4503dc LDR	X4, [X24, X30,LSL #3]

  (846) 0x4503e0 FMUL	D23, D22, D1

  (846) 0x4503e4 LDR	X8, [X22, X14,LSL #3]

  (846) 0x4503e8 LDR	X16, [X22, X4,LSL #3]

  (846) 0x4503ec FADD	D24, D0, D23

  (846) 0x4503f0 FADD	D25, D19, D23

  (846) 0x4503f4 FADD	D26, D20, D23

  (846) 0x4503f8 STR	D24, [X19, X5,LSL #3]

  (846) 0x4503fc LDR	D27, [X21, X1,LSL #3]

  (846) 0x450400 LDR	D28, [X19, X17,LSL #3]

  (846) 0x450404 LDR	D29, [X19, X8,LSL #3]

  (846) 0x450408 FMUL	D30, D27, D28

  (846) 0x45040c FADD	D31, D29, D30

  (846) 0x450410 FADD	D4, D25, D30

  (846) 0x450414 FADD	D5, D26, D30

  (846) 0x450418 STR	D31, [X19, X8,LSL #3]

  (846) 0x45041c LDR	D6, [X21, X1,LSL #3]

  (846) 0x450420 LDR	D3, [X19, X30,LSL #3]

  (846) 0x450424 LDR	D2, [X19, X16,LSL #3]

  (846) 0x450428 FMUL	D8, D6, D3

  (846) 0x45042c FADD	D7, D2, D8

  (846) 0x450430 FADD	D1, D4, D8

  (846) 0x450434 FADD	D0, D5, D8

  (846) 0x450438 STR	D7, [X19, X16,LSL #3]

  (846) 0x45043c CMP	X2, X15

  (846) 0x450440 B.NE	45038c

0x450444 B	44fd84

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1811 - 1837

--------------------------------------------------------------------------------

1811:                 for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1812:                 {

1813:                j1 = A_diag_j[j];

1814:                if (tmp_marker[j1] == i1)

1815:                {

1816:                   for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++)

1817:                   {

1818:                  k1 = P_diag_j[k];

1819:                      alfa = A_diag_data[j]*P_diag_data[k];

1820:                      P_diag_data[tmp_array[k1]] += alfa;

1821:                      sum_C += alfa;

1822:                      sum_N += alfa;

1823:                       }

1824:                   for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++)

1825:                   {

1826:                  k1 = P_offd_j[k];

1827:                      alfa = A_diag_data[j]*P_offd_data[k];

1828:                      P_offd_data[tmp_array_offd[k1]] += alfa;

1829:                      sum_C += alfa;

1830:                      sum_N += alfa;

1831:                       }

1832:                    }

1833:                    else

1834:                    {

1835:                       if (CF_marker[j1] != -3 &&

1836:                 (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1837:                  sum_N += A_diag_data[j];

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.60
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.10
Source	par_multi_interp.c:1811-1811,par_multi_interp.c:1814-1816,par_multi_interp.c:1819-1824,par_multi_interp.c:1827-1830,par_multi_interp.c:1835-1837
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.00
CQA cycles if no scalar integer	10.00
CQA cycles if FP arith vectorized	16.00
CQA cycles if fully vectorized	4.00
Front-end cycles	14.75
DIV/SQRT cycles	8.50
P0 cycles	8.50
P1 cycles	7.00
P2 cycles	7.00
P3 cycles	7.00
P4 cycles	7.00
P5 cycles	7.75
P6 cycles	7.75
P7 cycles	7.75
P8 cycles	7.75
P9 cycles	16.00
P10 cycles	16.00
P11 cycles	16.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	118.00
Nb uops	118.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	1.56
Nb FLOP add-sub	19.00
Nb FLOP mul	6.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	336.00
Bytes stored	48.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.60
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.10
Source	par_multi_interp.c:1811-1811,par_multi_interp.c:1814-1816,par_multi_interp.c:1819-1824,par_multi_interp.c:1827-1830,par_multi_interp.c:1835-1837
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.00
CQA cycles if no scalar integer	10.00
CQA cycles if FP arith vectorized	16.00
CQA cycles if fully vectorized	4.00
Front-end cycles	14.75
DIV/SQRT cycles	8.50
P0 cycles	8.50
P1 cycles	7.00
P2 cycles	7.00
P3 cycles	7.00
P4 cycles	7.00
P5 cycles	7.75
P6 cycles	7.75
P7 cycles	7.75
P8 cycles	7.75
P9 cycles	16.00
P10 cycles	16.00
P11 cycles	16.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	118.00
Nb uops	118.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	1.56
Nb FLOP add-sub	19.00
Nb FLOP mul	6.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	336.00
Bytes stored	48.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass._omp_fn.10
Source file and lines	par_multi_interp.c:1811-1837
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1811-1837.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1811,1814-1816,1819-1824,1827-1830,1835-1837.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 68 paths individually, rerun with max-paths=68
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 68 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.00 to 10.00 cycles (1.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 16.00 to 4.00 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 25 FP arithmetical operations:

19: addition or subtraction
6: multiply

The binary loop is loading 336 bytes. The binary loop is storing 48 bytes.

Arithmetic intensity

Arithmetic intensity is 0.07 FP operations per loaded or stored byte.

General properties

nb instructions	118
loop length	472
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

14.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	8.50	8.50	7.00	7.00	7.00	7.00	7.75	7.75	7.75	7.75	16.00	16.00	16.00	0.00	0.00
cycles	8.50	8.50	7.00	7.00	7.00	7.00	7.75	7.75	7.75	7.75	16.00	16.00	16.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.75
Overall L1	16.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

21% of peak load performance is reached (21.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 44fd90

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR X8, [X28, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X30, [X28, X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X30, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 44fdb8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X1, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 44fdcc <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x708>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X15, [X26, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
UBFM X14, X2, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X3, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 450158 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xa94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X17, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMN X17, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 44fd84 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 44fd74 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D2, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FADD D0, D0, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
CMP X1, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 44fd90 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X16, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X5, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X4, [X16, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X17, [X16, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X4, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 4502d0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X15, X17, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ANDS X14, X15, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 450218 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xb54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4501e4 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xb20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4501b8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xaf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X25, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D3, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D4, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X30, [X23, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
FMUL D5, D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D6, [X20, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D1, D1, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D0, D0, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D7, D6, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D7, [X20, X30,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR X16, [X25, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D16, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D8, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X15, [X23, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
FMUL D17, D8, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D18, [X20, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D1, D1, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D0, D0, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D19, D18, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D19, [X20, X15,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR X14, [X25, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D21, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D20, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X8, [X23, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
FMUL D8, D20, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D22, [X20, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D1, D1, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D0, D0, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D23, D22, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D23, [X20, X8,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
CMP X4, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4502d0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X17, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X2, [X17, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X15, [X17, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X2, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 44fd84 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X5, X15, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ANDS X4, X5, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 45038c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xcc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 450358 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 45032c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [X24, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D25, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D24, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X16, [X22, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
FMUL D26, D24, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D27, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D1, D1, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D0, D0, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D28, D27, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D28, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR X30, [X24, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D30, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D29, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X8, [X22, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
FMUL D31, D29, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D2, [X19, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D1, D1, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D0, D0, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D4, D2, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D4, [X19, X8,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR X17, [X24, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D3, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D5, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X5, [X22, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
FMUL D8, D5, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D6, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D1, D1, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D0, D0, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D7, D6, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D7, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
CMP X2, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 44fd84 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44fd84 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_BoomerAMGBuildMultipass._omp_fn.10
Source file and lines	par_multi_interp.c:1811-1837
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 68 paths individually, rerun with max-paths=68
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 25 FP arithmetical operations:

19: addition or subtraction
6: multiply

The binary loop is loading 336 bytes. The binary loop is storing 48 bytes.

Arithmetic intensity

Arithmetic intensity is 0.07 FP operations per loaded or stored byte.

General properties

nb instructions	118
loop length	472
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

14.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	8.50	8.50	7.00	7.00	7.00	7.00	7.75	7.75	7.75	7.75	16.00	16.00	16.00	0.00	0.00
cycles	8.50	8.50	7.00	7.00	7.00	7.00	7.75	7.75	7.75	7.75	16.00	16.00	16.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.75
Overall L1	16.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

21% of peak load performance is reached (21.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 44fd90

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR X8, [X28, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X30, [X28, X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X30, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 44fdb8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X1, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 44fdcc <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x708>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X15, [X26, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
UBFM X14, X2, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X3, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 450158 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xa94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X17, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMN X17, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 44fd84 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 44fd74 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D2, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FADD D0, D0, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
CMP X1, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 44fd90 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X16, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X5, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X4, [X16, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X17, [X16, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X4, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 4502d0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X15, X17, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ANDS X14, X15, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 450218 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xb54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4501e4 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xb20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4501b8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xaf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X25, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D3, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D4, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X30, [X23, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
FMUL D5, D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D6, [X20, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D1, D1, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D0, D0, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D7, D6, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D7, [X20, X30,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR X16, [X25, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D16, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D8, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X15, [X23, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
FMUL D17, D8, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D18, [X20, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D1, D1, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D0, D0, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D19, D18, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D19, [X20, X15,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR X14, [X25, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D21, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D20, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X8, [X23, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
FMUL D8, D20, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D22, [X20, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D1, D1, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D0, D0, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D23, D22, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D23, [X20, X8,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
CMP X4, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4502d0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X17, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X2, [X17, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X15, [X17, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X2, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 44fd84 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X5, X15, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ANDS X4, X5, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 45038c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xcc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 450358 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 45032c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [X24, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D25, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D24, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X16, [X22, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
FMUL D26, D24, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D27, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D1, D1, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D0, D0, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D28, D27, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D28, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR X30, [X24, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D30, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D29, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X8, [X22, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
FMUL D31, D29, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D2, [X19, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D1, D1, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D0, D0, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D4, D2, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D4, [X19, X8,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR X17, [X24, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D3, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D5, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X5, [X22, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
FMUL D8, D5, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D6, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D1, D1, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D0, D0, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D7, D6, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D7, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
CMP X2, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 44fd84 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 44fd84 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code