OV - exec - Loop 813

	Loop Id: 813	Module: exec	Source: par_multi_interp.c:944-970	Coverage: 0.49%

0x44c514 ADD	X2, X2, #1

0x44c518 CMP	X2, X15

0x44c51c B.GE	44c820

0x44c520 LDR	X3, [X27, X2,LSL #3]

0x44c524 LDR	X4, [X25, X3,LSL #3]

0x44c528 UBFM	X5, X3, #61, #60

0x44c52c CMP	X4, X13

0x44c530 B.NE	44c514

0x44c534 ADD	X5, X5, #8

0x44c538 LDR	X15, [X9, X3,LSL #3]

0x44c53c LDR	X12, [X23, X5]

0x44c540 ADD	X14, X15, X12

0x44c544 CMP	X15, X14

0x44c548 B.GE	44c6a4

0x44c54c LDR	X16, [SP, #136]

0x44c550 LDUR	X16, [X16, #504]

0x44c554 ADD	X14, X16, X14,LSL #3

0x44c558 ADD	X4, X16, X15,LSL #3

0x44c55c SUB	X12, X14, X4

0x44c560 SUB	X12, X12, #8

0x44c564 UBFM	X12, X12, #3, #63

0x44c568 ADD	X12, X12, #1

0x44c56c ANDS	X12, X12, #4160

0x44c570 B.EQ	44c604

0x44c574 CMP	X12, #1

0x44c578 B.EQ	44c5d4

0x44c57c CMP	X12, #2

0x44c580 B.EQ	44c5ac

0x44c584 LDR	X16, [X16, X15,LSL #3]

0x44c588 LDR	X15, [X20, X16,LSL #3]

0x44c58c CMP	X0, X15

0x44c590 B.EQ	44c5a8

0x44c594 LDR	X12, [X23, X1]

0x44c598 ADD	X11, X11, #1

0x44c59c ADD	X15, X12, #1

0x44c5a0 STR	X15, [X23, X1]

0x44c5a4 STR	X0, [X20, X16,LSL #3]

0x44c5a8 ADD	X4, X4, #8

0x44c5ac LDR	X16, [X4]

0x44c5b0 LDR	X12, [X20, X16,LSL #3]

0x44c5b4 CMP	X0, X12

0x44c5b8 B.EQ	44c5d0

0x44c5bc LDR	X15, [X23, X1]

0x44c5c0 ADD	X11, X11, #1

0x44c5c4 ADD	X12, X15, #1

0x44c5c8 STR	X12, [X23, X1]

0x44c5cc STR	X0, [X20, X16,LSL #3]

0x44c5d0 ADD	X4, X4, #8

0x44c5d4 LDR	X16, [X4]

0x44c5d8 LDR	X15, [X20, X16,LSL #3]

0x44c5dc CMP	X0, X15

0x44c5e0 B.EQ	44c5f8

0x44c5e4 LDR	X12, [X23, X1]

0x44c5e8 ADD	X11, X11, #1

0x44c5ec ADD	X15, X12, #1

0x44c5f0 STR	X15, [X23, X1]

0x44c5f4 STR	X0, [X20, X16,LSL #3]

0x44c5f8 ADD	X4, X4, #8

0x44c5fc CMP	X14, X4

0x44c600 B.EQ	44c6a4

  (815) 0x44c604 LDR	X16, [X4]

  (815) 0x44c608 LDR	X12, [X20, X16,LSL #3]

  (815) 0x44c60c CMP	X0, X12

  (815) 0x44c610 B.EQ	44c628

  (815) 0x44c614 LDR	X15, [X23, X1]

  (815) 0x44c618 ADD	X11, X11, #1

  (815) 0x44c61c ADD	X12, X15, #1

  (815) 0x44c620 STR	X12, [X23, X1]

  (815) 0x44c624 STR	X0, [X20, X16,LSL #3]

  (815) 0x44c628 LDR	X16, [X4, #8]

  (815) 0x44c62c ADD	X12, X4, #8

  (815) 0x44c630 LDR	X4, [X20, X16,LSL #3]

  (815) 0x44c634 CMP	X0, X4

  (815) 0x44c638 B.EQ	44c650

  (815) 0x44c63c LDR	X15, [X23, X1]

  (815) 0x44c640 ADD	X11, X11, #1

  (815) 0x44c644 ADD	X4, X15, #1

  (815) 0x44c648 STR	X4, [X23, X1]

  (815) 0x44c64c STR	X0, [X20, X16,LSL #3]

  (815) 0x44c650 LDR	X15, [X12, #8]

  (815) 0x44c654 ADD	X4, X12, #24

  (815) 0x44c658 LDR	X16, [X20, X15,LSL #3]

  (815) 0x44c65c CMP	X0, X16

  (815) 0x44c660 B.EQ	44c678

  (815) 0x44c664 LDR	X16, [X23, X1]

  (815) 0x44c668 ADD	X11, X11, #1

  (815) 0x44c66c ADD	X16, X16, #1

  (815) 0x44c670 STR	X16, [X23, X1]

  (815) 0x44c674 STR	X0, [X20, X15,LSL #3]

  (815) 0x44c678 LDR	X12, [X12, #16]

  (815) 0x44c67c LDR	X15, [X20, X12,LSL #3]

  (815) 0x44c680 CMP	X0, X15

  (815) 0x44c684 B.EQ	44c69c

  (815) 0x44c688 LDR	X16, [X23, X1]

  (815) 0x44c68c ADD	X11, X11, #1

  (815) 0x44c690 ADD	X15, X16, #1

  (815) 0x44c694 STR	X15, [X23, X1]

  (815) 0x44c698 STR	X0, [X20, X12,LSL #3]

  (815) 0x44c69c CMP	X14, X4

  (815) 0x44c6a0 B.NE	44c604

0x44c6a4 LDR	X12, [X8, X3,LSL #3]

0x44c6a8 LDR	X3, [X21, X5]

0x44c6ac ADD	X5, X12, X3

0x44c6b0 CMP	X12, X5

0x44c6b4 B.GE	44c810

0x44c6b8 LDR	X14, [SP, #144]

0x44c6bc LDUR	X16, [X14, #504]

0x44c6c0 ADD	X15, X16, X5,LSL #3

0x44c6c4 ADD	X3, X16, X12,LSL #3

0x44c6c8 SUB	X4, X15, X3

0x44c6cc SUB	X5, X4, #8

0x44c6d0 UBFM	X14, X5, #3, #63

0x44c6d4 ADD	X4, X14, #1

0x44c6d8 ANDS	X5, X4, #4160

0x44c6dc B.EQ	44c770

0x44c6e0 CMP	X5, #1

0x44c6e4 B.EQ	44c740

0x44c6e8 CMP	X5, #2

0x44c6ec B.EQ	44c718

0x44c6f0 LDR	X16, [X16, X12,LSL #3]

0x44c6f4 LDR	X12, [X19, X16,LSL #3]

0x44c6f8 CMP	X0, X12

0x44c6fc B.EQ	44c714

0x44c700 LDR	X14, [X21, X1]

0x44c704 ADD	X10, X10, #1

0x44c708 ADD	X4, X14, #1

0x44c70c STR	X4, [X21, X1]

0x44c710 STR	X0, [X19, X16,LSL #3]

0x44c714 ADD	X3, X3, #8

0x44c718 LDR	X5, [X3]

0x44c71c LDR	X16, [X19, X5,LSL #3]

0x44c720 CMP	X0, X16

0x44c724 B.EQ	44c73c

0x44c728 LDR	X12, [X21, X1]

0x44c72c ADD	X10, X10, #1

0x44c730 ADD	X14, X12, #1

0x44c734 STR	X14, [X21, X1]

0x44c738 STR	X0, [X19, X5,LSL #3]

0x44c73c ADD	X3, X3, #8

0x44c740 LDR	X4, [X3]

0x44c744 LDR	X5, [X19, X4,LSL #3]

0x44c748 CMP	X0, X5

0x44c74c B.EQ	44c764

0x44c750 LDR	X16, [X21, X1]

0x44c754 ADD	X10, X10, #1

0x44c758 ADD	X12, X16, #1

0x44c75c STR	X12, [X21, X1]

0x44c760 STR	X0, [X19, X4,LSL #3]

0x44c764 ADD	X3, X3, #8

0x44c768 CMP	X15, X3

0x44c76c B.EQ	44c810

  (814) 0x44c770 LDR	X14, [X3]

  (814) 0x44c774 LDR	X4, [X19, X14,LSL #3]

  (814) 0x44c778 CMP	X0, X4

  (814) 0x44c77c B.EQ	44c794

  (814) 0x44c780 LDR	X5, [X21, X1]

  (814) 0x44c784 ADD	X10, X10, #1

  (814) 0x44c788 ADD	X16, X5, #1

  (814) 0x44c78c STR	X16, [X21, X1]

  (814) 0x44c790 STR	X0, [X19, X14,LSL #3]

  (814) 0x44c794 LDR	X12, [X3, #8]

  (814) 0x44c798 ADD	X4, X3, #8

  (814) 0x44c79c LDR	X3, [X19, X12,LSL #3]

  (814) 0x44c7a0 CMP	X0, X3

  (814) 0x44c7a4 B.EQ	44c7bc

  (814) 0x44c7a8 LDR	X14, [X21, X1]

  (814) 0x44c7ac ADD	X10, X10, #1

  (814) 0x44c7b0 ADD	X5, X14, #1

  (814) 0x44c7b4 STR	X5, [X21, X1]

  (814) 0x44c7b8 STR	X0, [X19, X12,LSL #3]

  (814) 0x44c7bc LDR	X16, [X4, #8]

  (814) 0x44c7c0 ADD	X3, X4, #24

  (814) 0x44c7c4 LDR	X12, [X19, X16,LSL #3]

  (814) 0x44c7c8 CMP	X0, X12

  (814) 0x44c7cc B.EQ	44c7e4

  (814) 0x44c7d0 LDR	X14, [X21, X1]

  (814) 0x44c7d4 ADD	X10, X10, #1

  (814) 0x44c7d8 ADD	X5, X14, #1

  (814) 0x44c7dc STR	X5, [X21, X1]

  (814) 0x44c7e0 STR	X0, [X19, X16,LSL #3]

  (814) 0x44c7e4 LDR	X4, [X4, #16]

  (814) 0x44c7e8 LDR	X16, [X19, X4,LSL #3]

  (814) 0x44c7ec CMP	X0, X16

  (814) 0x44c7f0 B.EQ	44c808

  (814) 0x44c7f4 LDR	X12, [X21, X1]

  (814) 0x44c7f8 ADD	X10, X10, #1

  (814) 0x44c7fc ADD	X14, X12, #1

  (814) 0x44c800 STR	X14, [X21, X1]

  (814) 0x44c804 STR	X0, [X19, X4,LSL #3]

  (814) 0x44c808 CMP	X15, X3

  (814) 0x44c80c B.NE	44c770

0x44c810 LDR	X15, [X17]

0x44c814 ADD	X2, X2, #1

0x44c818 CMP	X2, X15

0x44c81c B.LT	44c520

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 944 - 970

--------------------------------------------------------------------------------

944:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

945:              {

946:                 j1 = S_diag_j[j];

947:                 if (assigned[j1] == pass-1)

948:                 {

949:                    j_start = P_diag_start[j1];

950:                    j_end = j_start+P_diag_i[j1+1];

951:                    for (k=j_start; k < j_end; k++)

952:                    {

953:                       k1 = P_diag_pass[pass-1][k];

954:                       if (P_marker[k1] != i1)

955:                       {

956:                          cnt_nz++;

957:                          P_diag_i[i1+1]++;

958:                          P_marker[k1] = i1;

959:                       }

960:                    }

961:                    j_start = P_offd_start[j1];

962:                    j_end = j_start+P_offd_i[j1+1];

963:                    for (k=j_start; k < j_end; k++)

964:                    {

965:                       k1 = P_offd_pass[pass-1][k];

966:                       if (P_marker_offd[k1] != i1)

967:                       {

968:                          cnt_nz_offd++;

969:                          P_offd_i[i1+1]++;

970:                          P_marker_offd[k1] = i1;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:944-944,par_multi_interp.c:947-958,par_multi_interp.c:961-970
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.38
CQA cycles if no scalar integer	14.38
CQA cycles if FP arith vectorized	14.38
CQA cycles if fully vectorized	3.59
Front-end cycles	14.38
DIV/SQRT cycles	9.50
P0 cycles	9.50
P1 cycles	13.75
P2 cycles	13.75
P3 cycles	13.75
P4 cycles	13.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	13.67
P10 cycles	13.67
P11 cycles	13.67
P12 cycles	6.00
P13 cycles	6.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	115.00
Nb uops	115.00
Nb loads	NA
Nb stores	12.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.82
Bytes prefetched	0.00
Bytes loaded	232.00
Bytes stored	96.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:944-944,par_multi_interp.c:947-958,par_multi_interp.c:961-970
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.38
CQA cycles if no scalar integer	14.38
CQA cycles if FP arith vectorized	14.38
CQA cycles if fully vectorized	3.59
Front-end cycles	14.38
DIV/SQRT cycles	9.50
P0 cycles	9.50
P1 cycles	13.75
P2 cycles	13.75
P3 cycles	13.75
P4 cycles	13.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	13.67
P10 cycles	13.67
P11 cycles	13.67
P12 cycles	6.00
P13 cycles	6.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	115.00
Nb uops	115.00
Nb loads	NA
Nb stores	12.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.82
Bytes prefetched	0.00
Bytes loaded	232.00
Bytes stored	96.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:944-970
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:944-970.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:944,947-958,961-970.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 65026 paths individually, rerun with max-paths=65026
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 65026 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 14.38 to 3.59 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 232 bytes. The binary loop is storing 96 bytes.

General properties

nb instructions	115
loop length	460
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

14.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	9.50	9.50	13.75	13.75	13.75	13.75	0.00	0.00	0.00	0.00	13.67	13.67	13.67	6.00	6.00
cycles	9.50	9.50	13.75	13.75	13.75	13.75	0.00	0.00	0.00	0.00	13.67	13.67	13.67	6.00	6.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.38
Overall L1	14.38

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.38 cycles. At this rate:

16% of peak load performance is reached (16.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.68 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 44c520

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X2, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 44c820 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x4e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X3, [X27, X2,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X25, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X5, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X4, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 44c514 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X15, [X9, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X23, X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X15, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X15, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 44c6a4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x364>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X16, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X16, [X16, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X16, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X16, X15,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X12, X14, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X12, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X12, X12, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X12, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ANDS X12, X12, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44c604 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x2c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44c5d4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x294>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X12, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44c5ac <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x26c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X16, [X16, X15,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X20, X16,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X0, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44c5a8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x268>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X12, [X23, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X15, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X15, [X23, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X0, [X20, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X16, [X4]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X20, X16,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X0, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44c5d0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x290>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [X23, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X12, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X12, [X23, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X0, [X20, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X16, [X4]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X20, X16,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X0, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44c5f8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X12, [X23, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X15, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X15, [X23, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X0, [X20, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X14, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44c6a4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x364>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X12, [X8, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X21, X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, X12, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X12, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 44c810 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x4d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X16, [X14, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X16, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X3, X16, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X4, X15, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X5, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X14, X5, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ANDS X5, X4, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44c770 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x430>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44c740 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x400>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X5, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44c718 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x3d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X16, [X16, X12,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X0, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44c714 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x3d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [X21, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X4, [X21, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X0, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X5, [X3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X0, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44c73c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X12, [X21, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X14, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X14, [X21, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X0, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X4, [X3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44c764 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x424>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X16, [X21, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X12, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X12, [X21, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X0, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X15, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44c810 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x4d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [X17]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X2, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 44c520 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:944-970
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 65026 paths individually, rerun with max-paths=65026
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 232 bytes. The binary loop is storing 96 bytes.

General properties

nb instructions	115
loop length	460
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

14.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	9.50	9.50	13.75	13.75	13.75	13.75	0.00	0.00	0.00	0.00	13.67	13.67	13.67	6.00	6.00
cycles	9.50	9.50	13.75	13.75	13.75	13.75	0.00	0.00	0.00	0.00	13.67	13.67	13.67	6.00	6.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.38
Overall L1	14.38

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.38 cycles. At this rate:

16% of peak load performance is reached (16.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.68 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 44c520

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X2, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 44c820 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x4e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X3, [X27, X2,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X25, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X5, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X4, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 44c514 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X15, [X9, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X23, X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X15, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X15, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 44c6a4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x364>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X16, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X16, [X16, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X16, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X16, X15,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X12, X14, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X12, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X12, X12, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X12, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ANDS X12, X12, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44c604 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x2c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44c5d4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x294>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X12, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44c5ac <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x26c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X16, [X16, X15,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X20, X16,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X0, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44c5a8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x268>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X12, [X23, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X15, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X15, [X23, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X0, [X20, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X16, [X4]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X20, X16,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X0, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44c5d0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x290>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [X23, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X12, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X12, [X23, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X0, [X20, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X16, [X4]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X20, X16,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X0, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44c5f8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X12, [X23, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X15, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X15, [X23, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X0, [X20, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X14, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44c6a4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x364>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X12, [X8, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X21, X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, X12, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X12, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 44c810 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x4d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X16, [X14, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X16, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X3, X16, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X4, X15, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X5, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X14, X5, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ANDS X5, X4, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44c770 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x430>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44c740 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x400>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X5, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44c718 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x3d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X16, [X16, X12,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X0, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44c714 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x3d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [X21, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X4, [X21, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X0, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X5, [X3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X0, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44c73c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X12, [X21, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X14, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X14, [X21, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X0, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X4, [X3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44c764 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x424>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X16, [X21, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X12, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X12, [X21, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X0, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X15, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44c810 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x4d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [X17]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X2, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 44c520 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code