OV - exec - Loop 810

	Loop Id: 810	Module: exec	Source: par_multi_interp.c:939-999 [...]	Coverage: 0.05%

0x44c4e4 LDR	X1, [SP, #104]

0x44c4e8 LDR	X0, [X1, X18,LSL #3]

0x44c4ec UBFM	X3, X0, #61, #60

0x44c4f0 STR	X11, [X9, X0,LSL #3]

0x44c4f4 ADD	X1, X3, #8

0x44c4f8 STR	X10, [X8, X0,LSL #3]

0x44c4fc LDR	X15, [X7, X1]

0x44c500 ADD	X17, X7, X1

0x44c504 LDR	X2, [X7, X0,LSL #3]

0x44c508 CMP	X2, X15

0x44c50c B.LT	44c520

0x44c510 B	44c820

  (813) 0x44c514 ADD	X2, X2, #1

  (813) 0x44c518 CMP	X2, X15

  (813) 0x44c51c B.GE	44c820

  (813) 0x44c520 LDR	X3, [X27, X2,LSL #3]

  (813) 0x44c524 LDR	X4, [X25, X3,LSL #3]

  (813) 0x44c528 UBFM	X5, X3, #61, #60

  (813) 0x44c52c CMP	X4, X13

  (813) 0x44c530 B.NE	44c514

  (813) 0x44c534 ADD	X5, X5, #8

  (813) 0x44c538 LDR	X15, [X9, X3,LSL #3]

  (813) 0x44c53c LDR	X12, [X23, X5]

  (813) 0x44c540 ADD	X14, X15, X12

  (813) 0x44c544 CMP	X15, X14

  (813) 0x44c548 B.GE	44c6a4

  (813) 0x44c54c LDR	X16, [SP, #136]

  (813) 0x44c550 LDUR	X16, [X16, #504]

  (813) 0x44c554 ADD	X14, X16, X14,LSL #3

  (813) 0x44c558 ADD	X4, X16, X15,LSL #3

  (813) 0x44c55c SUB	X12, X14, X4

  (813) 0x44c560 SUB	X12, X12, #8

  (813) 0x44c564 UBFM	X12, X12, #3, #63

  (813) 0x44c568 ADD	X12, X12, #1

  (813) 0x44c56c ANDS	X12, X12, #4160

  (813) 0x44c570 B.EQ	44c604

  (813) 0x44c574 CMP	X12, #1

  (813) 0x44c578 B.EQ	44c5d4

  (813) 0x44c57c CMP	X12, #2

  (813) 0x44c580 B.EQ	44c5ac

  (813) 0x44c584 LDR	X16, [X16, X15,LSL #3]

  (813) 0x44c588 LDR	X15, [X20, X16,LSL #3]

  (813) 0x44c58c CMP	X0, X15

  (813) 0x44c590 B.EQ	44c5a8

  (813) 0x44c594 LDR	X12, [X23, X1]

  (813) 0x44c598 ADD	X11, X11, #1

  (813) 0x44c59c ADD	X15, X12, #1

  (813) 0x44c5a0 STR	X15, [X23, X1]

  (813) 0x44c5a4 STR	X0, [X20, X16,LSL #3]

  (813) 0x44c5a8 ADD	X4, X4, #8

  (813) 0x44c5ac LDR	X16, [X4]

  (813) 0x44c5b0 LDR	X12, [X20, X16,LSL #3]

  (813) 0x44c5b4 CMP	X0, X12

  (813) 0x44c5b8 B.EQ	44c5d0

  (813) 0x44c5bc LDR	X15, [X23, X1]

  (813) 0x44c5c0 ADD	X11, X11, #1

  (813) 0x44c5c4 ADD	X12, X15, #1

  (813) 0x44c5c8 STR	X12, [X23, X1]

  (813) 0x44c5cc STR	X0, [X20, X16,LSL #3]

  (813) 0x44c5d0 ADD	X4, X4, #8

  (813) 0x44c5d4 LDR	X16, [X4]

  (813) 0x44c5d8 LDR	X15, [X20, X16,LSL #3]

  (813) 0x44c5dc CMP	X0, X15

  (813) 0x44c5e0 B.EQ	44c5f8

  (813) 0x44c5e4 LDR	X12, [X23, X1]

  (813) 0x44c5e8 ADD	X11, X11, #1

  (813) 0x44c5ec ADD	X15, X12, #1

  (813) 0x44c5f0 STR	X15, [X23, X1]

  (813) 0x44c5f4 STR	X0, [X20, X16,LSL #3]

  (813) 0x44c5f8 ADD	X4, X4, #8

  (813) 0x44c5fc CMP	X14, X4

  (813) 0x44c600 B.EQ	44c6a4

    (815) 0x44c604 LDR	X16, [X4]

    (815) 0x44c608 LDR	X12, [X20, X16,LSL #3]

    (815) 0x44c60c CMP	X0, X12

    (815) 0x44c610 B.EQ	44c628

    (815) 0x44c614 LDR	X15, [X23, X1]

    (815) 0x44c618 ADD	X11, X11, #1

    (815) 0x44c61c ADD	X12, X15, #1

    (815) 0x44c620 STR	X12, [X23, X1]

    (815) 0x44c624 STR	X0, [X20, X16,LSL #3]

    (815) 0x44c628 LDR	X16, [X4, #8]

    (815) 0x44c62c ADD	X12, X4, #8

    (815) 0x44c630 LDR	X4, [X20, X16,LSL #3]

    (815) 0x44c634 CMP	X0, X4

    (815) 0x44c638 B.EQ	44c650

    (815) 0x44c63c LDR	X15, [X23, X1]

    (815) 0x44c640 ADD	X11, X11, #1

    (815) 0x44c644 ADD	X4, X15, #1

    (815) 0x44c648 STR	X4, [X23, X1]

    (815) 0x44c64c STR	X0, [X20, X16,LSL #3]

    (815) 0x44c650 LDR	X15, [X12, #8]

    (815) 0x44c654 ADD	X4, X12, #24

    (815) 0x44c658 LDR	X16, [X20, X15,LSL #3]

    (815) 0x44c65c CMP	X0, X16

    (815) 0x44c660 B.EQ	44c678

    (815) 0x44c664 LDR	X16, [X23, X1]

    (815) 0x44c668 ADD	X11, X11, #1

    (815) 0x44c66c ADD	X16, X16, #1

    (815) 0x44c670 STR	X16, [X23, X1]

    (815) 0x44c674 STR	X0, [X20, X15,LSL #3]

    (815) 0x44c678 LDR	X12, [X12, #16]

    (815) 0x44c67c LDR	X15, [X20, X12,LSL #3]

    (815) 0x44c680 CMP	X0, X15

    (815) 0x44c684 B.EQ	44c69c

    (815) 0x44c688 LDR	X16, [X23, X1]

    (815) 0x44c68c ADD	X11, X11, #1

    (815) 0x44c690 ADD	X15, X16, #1

    (815) 0x44c694 STR	X15, [X23, X1]

    (815) 0x44c698 STR	X0, [X20, X12,LSL #3]

    (815) 0x44c69c CMP	X14, X4

    (815) 0x44c6a0 B.NE	44c604

  (813) 0x44c6a4 LDR	X12, [X8, X3,LSL #3]

  (813) 0x44c6a8 LDR	X3, [X21, X5]

  (813) 0x44c6ac ADD	X5, X12, X3

  (813) 0x44c6b0 CMP	X12, X5

  (813) 0x44c6b4 B.GE	44c810

  (813) 0x44c6b8 LDR	X14, [SP, #144]

  (813) 0x44c6bc LDUR	X16, [X14, #504]

  (813) 0x44c6c0 ADD	X15, X16, X5,LSL #3

  (813) 0x44c6c4 ADD	X3, X16, X12,LSL #3

  (813) 0x44c6c8 SUB	X4, X15, X3

  (813) 0x44c6cc SUB	X5, X4, #8

  (813) 0x44c6d0 UBFM	X14, X5, #3, #63

  (813) 0x44c6d4 ADD	X4, X14, #1

  (813) 0x44c6d8 ANDS	X5, X4, #4160

  (813) 0x44c6dc B.EQ	44c770

  (813) 0x44c6e0 CMP	X5, #1

  (813) 0x44c6e4 B.EQ	44c740

  (813) 0x44c6e8 CMP	X5, #2

  (813) 0x44c6ec B.EQ	44c718

  (813) 0x44c6f0 LDR	X16, [X16, X12,LSL #3]

  (813) 0x44c6f4 LDR	X12, [X19, X16,LSL #3]

  (813) 0x44c6f8 CMP	X0, X12

  (813) 0x44c6fc B.EQ	44c714

  (813) 0x44c700 LDR	X14, [X21, X1]

  (813) 0x44c704 ADD	X10, X10, #1

  (813) 0x44c708 ADD	X4, X14, #1

  (813) 0x44c70c STR	X4, [X21, X1]

  (813) 0x44c710 STR	X0, [X19, X16,LSL #3]

  (813) 0x44c714 ADD	X3, X3, #8

  (813) 0x44c718 LDR	X5, [X3]

  (813) 0x44c71c LDR	X16, [X19, X5,LSL #3]

  (813) 0x44c720 CMP	X0, X16

  (813) 0x44c724 B.EQ	44c73c

  (813) 0x44c728 LDR	X12, [X21, X1]

  (813) 0x44c72c ADD	X10, X10, #1

  (813) 0x44c730 ADD	X14, X12, #1

  (813) 0x44c734 STR	X14, [X21, X1]

  (813) 0x44c738 STR	X0, [X19, X5,LSL #3]

  (813) 0x44c73c ADD	X3, X3, #8

  (813) 0x44c740 LDR	X4, [X3]

  (813) 0x44c744 LDR	X5, [X19, X4,LSL #3]

  (813) 0x44c748 CMP	X0, X5

  (813) 0x44c74c B.EQ	44c764

  (813) 0x44c750 LDR	X16, [X21, X1]

  (813) 0x44c754 ADD	X10, X10, #1

  (813) 0x44c758 ADD	X12, X16, #1

  (813) 0x44c75c STR	X12, [X21, X1]

  (813) 0x44c760 STR	X0, [X19, X4,LSL #3]

  (813) 0x44c764 ADD	X3, X3, #8

  (813) 0x44c768 CMP	X15, X3

  (813) 0x44c76c B.EQ	44c810

    (814) 0x44c770 LDR	X14, [X3]

    (814) 0x44c774 LDR	X4, [X19, X14,LSL #3]

    (814) 0x44c778 CMP	X0, X4

    (814) 0x44c77c B.EQ	44c794

    (814) 0x44c780 LDR	X5, [X21, X1]

    (814) 0x44c784 ADD	X10, X10, #1

    (814) 0x44c788 ADD	X16, X5, #1

    (814) 0x44c78c STR	X16, [X21, X1]

    (814) 0x44c790 STR	X0, [X19, X14,LSL #3]

    (814) 0x44c794 LDR	X12, [X3, #8]

    (814) 0x44c798 ADD	X4, X3, #8

    (814) 0x44c79c LDR	X3, [X19, X12,LSL #3]

    (814) 0x44c7a0 CMP	X0, X3

    (814) 0x44c7a4 B.EQ	44c7bc

    (814) 0x44c7a8 LDR	X14, [X21, X1]

    (814) 0x44c7ac ADD	X10, X10, #1

    (814) 0x44c7b0 ADD	X5, X14, #1

    (814) 0x44c7b4 STR	X5, [X21, X1]

    (814) 0x44c7b8 STR	X0, [X19, X12,LSL #3]

    (814) 0x44c7bc LDR	X16, [X4, #8]

    (814) 0x44c7c0 ADD	X3, X4, #24

    (814) 0x44c7c4 LDR	X12, [X19, X16,LSL #3]

    (814) 0x44c7c8 CMP	X0, X12

    (814) 0x44c7cc B.EQ	44c7e4

    (814) 0x44c7d0 LDR	X14, [X21, X1]

    (814) 0x44c7d4 ADD	X10, X10, #1

    (814) 0x44c7d8 ADD	X5, X14, #1

    (814) 0x44c7dc STR	X5, [X21, X1]

    (814) 0x44c7e0 STR	X0, [X19, X16,LSL #3]

    (814) 0x44c7e4 LDR	X4, [X4, #16]

    (814) 0x44c7e8 LDR	X16, [X19, X4,LSL #3]

    (814) 0x44c7ec CMP	X0, X16

    (814) 0x44c7f0 B.EQ	44c808

    (814) 0x44c7f4 LDR	X12, [X21, X1]

    (814) 0x44c7f8 ADD	X10, X10, #1

    (814) 0x44c7fc ADD	X14, X12, #1

    (814) 0x44c800 STR	X14, [X21, X1]

    (814) 0x44c804 STR	X0, [X19, X4,LSL #3]

    (814) 0x44c808 CMP	X15, X3

    (814) 0x44c80c B.NE	44c770

  (813) 0x44c810 LDR	X15, [X17]

  (813) 0x44c814 ADD	X2, X2, #1

  (813) 0x44c818 CMP	X2, X15

  (813) 0x44c81c B.LT	44c520

0x44c820 LDR	X2, [X6, X0,LSL #3]

0x44c824 ADD	X15, X6, X1

0x44c828 LDR	X14, [X6, X1]

0x44c82c CMP	X2, X14

0x44c830 B.LT	44c844

0x44c834 B	44c944

  (811) 0x44c838 ADD	X2, X2, #1

  (811) 0x44c83c CMP	X2, X14

  (811) 0x44c840 B.GE	44c944

  (811) 0x44c844 LDR	X17, [X26, X2,LSL #3]

  (811) 0x44c848 LDR	X3, [X24, X17,LSL #3]

  (811) 0x44c84c UBFM	X5, X17, #61, #60

  (811) 0x44c850 CMP	X3, X13

  (811) 0x44c854 B.NE	44c838

  (811) 0x44c858 ADD	X4, X28, X5

  (811) 0x44c85c LDR	X16, [X30, X17,LSL #3]

  (811) 0x44c860 LDR	X12, [X4, #8]

  (811) 0x44c864 ADD	X17, X16, X12

  (811) 0x44c868 CMP	X16, X17

  (811) 0x44c86c B.GE	44c838

  (811) 0x44c870 LDR	X14, [SP, #96]

  (811) 0x44c874 LDR	X12, [X14, X22]

  (811) 0x44c878 ADD	X5, X12, X17,LSL #3

  (811) 0x44c87c ADD	X3, X12, X16,LSL #3

  (811) 0x44c880 SUB	X4, X5, X3

  (811) 0x44c884 SUB	X17, X4, #8

  (811) 0x44c888 UBFM	X14, X17, #3, #63

  (811) 0x44c88c ADD	X4, X14, #1

  (811) 0x44c890 ANDS	X17, X4, #4160

  (811) 0x44c894 B.EQ	44cb74

  (811) 0x44c898 CMP	X17, #1

  (811) 0x44c89c B.EQ	44c900

  (811) 0x44c8a0 CMP	X17, #2

  (811) 0x44c8a4 B.EQ	44c8d4

  (811) 0x44c8a8 LDR	X16, [X12, X16,LSL #3]

  (811) 0x44c8ac TBNZ	X16, #63, 44cc7c

  (811) 0x44c8b0 LDR	X12, [X19, X16,LSL #3]

  (811) 0x44c8b4 CMP	X0, X12

  (811) 0x44c8b8 B.EQ	44c8d0

  (811) 0x44c8bc LDR	X14, [X21, X1]

  (811) 0x44c8c0 ADD	X10, X10, #1

  (811) 0x44c8c4 ADD	X4, X14, #1

  (811) 0x44c8c8 STR	X4, [X21, X1]

  (811) 0x44c8cc STR	X0, [X19, X16,LSL #3]

  (811) 0x44c8d0 ADD	X3, X3, #8

  (811) 0x44c8d4 LDR	X4, [X3]

  (811) 0x44c8d8 TBNZ	X4, #63, 44cc54

  (811) 0x44c8dc LDR	X17, [X19, X4,LSL #3]

  (811) 0x44c8e0 CMP	X0, X17

  (811) 0x44c8e4 B.EQ	44c8fc

  (811) 0x44c8e8 LDR	X16, [X21, X1]

  (811) 0x44c8ec ADD	X10, X10, #1

  (811) 0x44c8f0 ADD	X12, X16, #1

  (811) 0x44c8f4 STR	X12, [X21, X1]

  (811) 0x44c8f8 STR	X0, [X19, X4,LSL #3]

  (811) 0x44c8fc ADD	X3, X3, #8

  (811) 0x44c900 LDR	X14, [X3]

  (811) 0x44c904 TBNZ	X14, #63, 44cc2c

  (811) 0x44c908 LDR	X12, [X19, X14,LSL #3]

  (811) 0x44c90c CMP	X0, X12

  (811) 0x44c910 B.EQ	44c928

  (811) 0x44c914 LDR	X4, [X21, X1]

  (811) 0x44c918 ADD	X10, X10, #1

  (811) 0x44c91c ADD	X17, X4, #1

  (811) 0x44c920 STR	X17, [X21, X1]

  (811) 0x44c924 STR	X0, [X19, X14,LSL #3]

  (811) 0x44c928 ADD	X3, X3, #8

  (811) 0x44c92c CMP	X5, X3

  (811) 0x44c930 B.NE	44cb74

  (811) 0x44c934 LDR	X14, [X15]

  (811) 0x44c938 ADD	X2, X2, #1

  (811) 0x44c93c CMP	X2, X14

  (811) 0x44c940 B.LT	44c844

0x44c944 LDR	X5, [SP, #112]

0x44c948 ADD	X18, X18, #1

0x44c94c CMP	X5, X18

0x44c950 B.GT	44c4e4

    (812) 0x44cacc LDR	X16, [X19, X17,LSL #3]

    (812) 0x44cad0 CMP	X0, X16

    (812) 0x44cad4 B.EQ	44caec

    (812) 0x44cad8 LDR	X14, [X21, X1]

    (812) 0x44cadc ADD	X10, X10, #1

    (812) 0x44cae0 ADD	X12, X14, #1

    (812) 0x44cae4 STR	X12, [X21, X1]

    (812) 0x44cae8 STR	X0, [X19, X17,LSL #3]

    (812) 0x44caec LDR	X4, [X3, #8]

    (812) 0x44caf0 ADD	X3, X3, #8

    (812) 0x44caf4 TBNZ	X4, #63, 44cbac

    (812) 0x44caf8 LDR	X12, [X19, X4,LSL #3]

    (812) 0x44cafc CMP	X0, X12

    (812) 0x44cb00 B.EQ	44cb18

    (812) 0x44cb04 LDR	X17, [X21, X1]

    (812) 0x44cb08 ADD	X10, X10, #1

    (812) 0x44cb0c ADD	X16, X17, #1

    (812) 0x44cb10 STR	X16, [X21, X1]

    (812) 0x44cb14 STR	X0, [X19, X4,LSL #3]

    (812) 0x44cb18 LDR	X16, [X3, #8]

    (812) 0x44cb1c TBNZ	X16, #63, 44cbd8

    (812) 0x44cb20 LDR	X14, [X19, X16,LSL #3]

    (812) 0x44cb24 CMP	X0, X14

    (812) 0x44cb28 B.EQ	44cb40

    (812) 0x44cb2c LDR	X4, [X21, X1]

    (812) 0x44cb30 ADD	X10, X10, #1

    (812) 0x44cb34 ADD	X12, X4, #1

    (812) 0x44cb38 STR	X12, [X21, X1]

    (812) 0x44cb3c STR	X0, [X19, X16,LSL #3]

    (812) 0x44cb40 LDR	X17, [X3, #16]

    (812) 0x44cb44 TBNZ	X17, #63, 44cc04

    (812) 0x44cb48 LDR	X12, [X19, X17,LSL #3]

    (812) 0x44cb4c CMP	X0, X12

    (812) 0x44cb50 B.EQ	44cb68

    (812) 0x44cb54 LDR	X16, [X21, X1]

    (812) 0x44cb58 ADD	X10, X10, #1

    (812) 0x44cb5c ADD	X14, X16, #1

    (812) 0x44cb60 STR	X14, [X21, X1]

    (812) 0x44cb64 STR	X0, [X19, X17,LSL #3]

    (812) 0x44cb68 ADD	X3, X3, #24

    (812) 0x44cb6c CMP	X5, X3

    (812) 0x44cb70 B.EQ	44c934

    (812) 0x44cb74 LDR	X17, [X3]

    (812) 0x44cb78 TBZ	X17, #63, 44cacc

    (812) 0x44cb7c ORN	X4, XZR, X17

    (812) 0x44cb80 LDR	X17, [X20, X4,LSL #3]

    (812) 0x44cb84 CMP	X0, X17

    (812) 0x44cb88 B.EQ	44caec

    (812) 0x44cb8c LDR	X16, [X23, X1]

    (812) 0x44cb90 ADD	X11, X11, #1

    (812) 0x44cb94 ADD	X3, X3, #8

    (812) 0x44cb98 ADD	X14, X16, #1

    (812) 0x44cb9c STR	X14, [X23, X1]

    (812) 0x44cba0 STR	X0, [X20, X4,LSL #3]

    (812) 0x44cba4 LDR	X4, [X3]

    (812) 0x44cba8 TBZ	X4, #63, 44caf8

    (812) 0x44cbac ORN	X14, XZR, X4

    (812) 0x44cbb0 LDR	X4, [X20, X14,LSL #3]

    (812) 0x44cbb4 CMP	X0, X4

    (812) 0x44cbb8 B.EQ	44cb18

    (812) 0x44cbbc LDR	X12, [X23, X1]

    (812) 0x44cbc0 ADD	X11, X11, #1

    (812) 0x44cbc4 ADD	X17, X12, #1

    (812) 0x44cbc8 STR	X17, [X23, X1]

    (812) 0x44cbcc STR	X0, [X20, X14,LSL #3]

    (812) 0x44cbd0 LDR	X16, [X3, #8]

    (812) 0x44cbd4 TBZ	X16, #63, 44cb20

    (812) 0x44cbd8 ORN	X17, XZR, X16

    (812) 0x44cbdc LDR	X16, [X20, X17,LSL #3]

    (812) 0x44cbe0 CMP	X0, X16

    (812) 0x44cbe4 B.EQ	44cb40

    (812) 0x44cbe8 LDR	X14, [X23, X1]

    (812) 0x44cbec ADD	X11, X11, #1

    (812) 0x44cbf0 ADD	X4, X14, #1

    (812) 0x44cbf4 STR	X4, [X23, X1]

    (812) 0x44cbf8 STR	X0, [X20, X17,LSL #3]

    (812) 0x44cbfc LDR	X17, [X3, #16]

    (812) 0x44cc00 TBZ	X17, #63, 44cb48

    (812) 0x44cc04 ORN	X4, XZR, X17

    (812) 0x44cc08 LDR	X17, [X20, X4,LSL #3]

    (812) 0x44cc0c CMP	X0, X17

    (812) 0x44cc10 B.EQ	44cb68

    (812) 0x44cc14 LDR	X12, [X23, X1]

    (812) 0x44cc18 ADD	X11, X11, #1

    (812) 0x44cc1c ADD	X16, X12, #1

    (812) 0x44cc20 STR	X16, [X23, X1]

    (812) 0x44cc24 STR	X0, [X20, X4,LSL #3]

    (812) 0x44cc28 B	44cb68

  (811) 0x44cc2c ORN	X16, XZR, X14

  (811) 0x44cc30 LDR	X14, [X20, X16,LSL #3]

  (811) 0x44cc34 CMP	X0, X14

  (811) 0x44cc38 B.EQ	44c928

  (811) 0x44cc3c LDR	X12, [X23, X1]

  (811) 0x44cc40 ADD	X11, X11, #1

  (811) 0x44cc44 ADD	X4, X12, #1

  (811) 0x44cc48 STR	X4, [X23, X1]

  (811) 0x44cc4c STR	X0, [X20, X16,LSL #3]

  (811) 0x44cc50 B	44c928

  (811) 0x44cc54 ORN	X14, XZR, X4

  (811) 0x44cc58 LDR	X4, [X20, X14,LSL #3]

  (811) 0x44cc5c CMP	X0, X4

  (811) 0x44cc60 B.EQ	44c8fc

  (811) 0x44cc64 LDR	X17, [X23, X1]

  (811) 0x44cc68 ADD	X11, X11, #1

  (811) 0x44cc6c ADD	X16, X17, #1

  (811) 0x44cc70 STR	X16, [X23, X1]

  (811) 0x44cc74 STR	X0, [X20, X14,LSL #3]

  (811) 0x44cc78 B	44c8fc

  (811) 0x44cc7c ORN	X17, XZR, X16

  (811) 0x44cc80 LDR	X16, [X20, X17,LSL #3]

  (811) 0x44cc84 CMP	X0, X16

  (811) 0x44cc88 B.EQ	44c8d0

  (811) 0x44cc8c LDR	X12, [X23, X1]

  (811) 0x44cc90 ADD	X11, X11, #1

  (811) 0x44cc94 ADD	X14, X12, #1

  (811) 0x44cc98 STR	X14, [X23, X1]

  (811) 0x44cc9c STR	X0, [X20, X17,LSL #3]

  (811) 0x44cca0 B	44c8d0

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 939 - 999

--------------------------------------------------------------------------------

939:           for (i=thread_start; i < thread_stop; i++)

940:           {

941:              i1 = pass_array[i];

942:              P_diag_start[i1] = cnt_nz;

943:              P_offd_start[i1] = cnt_nz_offd;

944:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

945:              {

946:                 j1 = S_diag_j[j];

947:                 if (assigned[j1] == pass-1)

948:                 {

949:                    j_start = P_diag_start[j1];

950:                    j_end = j_start+P_diag_i[j1+1];

951:                    for (k=j_start; k < j_end; k++)

952:                    {

953:                       k1 = P_diag_pass[pass-1][k];

954:                       if (P_marker[k1] != i1)

955:                       {

956:                          cnt_nz++;

957:                          P_diag_i[i1+1]++;

958:                          P_marker[k1] = i1;

959:                       }

960:                    }

961:                    j_start = P_offd_start[j1];

962:                    j_end = j_start+P_offd_i[j1+1];

963:                    for (k=j_start; k < j_end; k++)

964:                    {

965:                       k1 = P_offd_pass[pass-1][k];

966:                       if (P_marker_offd[k1] != i1)

967:                       {

968:                          cnt_nz_offd++;

969:                          P_offd_i[i1+1]++;

970:                          P_marker_offd[k1] = i1;

[...]

976:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

977:              {

978:                 j1 = S_offd_j[j];

979:                 if (assigned_offd[j1] == pass-1)

980:                 {

981:                    j_start = Pext_start[j1];

982:                    j_end = j_start+Pext_i[j1+1];

983:                    for (k=j_start; k < j_end; k++)

984:                    {

985:                       k1 = Pext_pass[pass][k];

986:                       if (k1 < 0)

987:                       {

988:                          if (P_marker[-k1-1] != i1)

989:                          {

990:                             cnt_nz++;

991:                             P_diag_i[i1+1]++;

992:                             P_marker[-k1-1] = i1;

993:                          }

994:                       }

995:                       else if (P_marker_offd[k1] != i1)

996:                       {

997:                          cnt_nz_offd++;

998:                          P_offd_i[i1+1]++;

999:                          P_marker_offd[k1] = i1;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:939-944,par_multi_interp.c:976-976
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.75
Front-end cycles	2.75
DIV/SQRT cycles	2.50
P0 cycles	2.50
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	3.00
P10 cycles	3.00
P11 cycles	3.00
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	22.00
Nb uops	22.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:939-944,par_multi_interp.c:976-976
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.75
Front-end cycles	2.75
DIV/SQRT cycles	2.50
P0 cycles	2.50
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	3.00
P10 cycles	3.00
P11 cycles	3.00
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	22.00
Nb uops	22.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:939-999
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:939-970,976-999.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:939-944,976.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.75 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 56 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	22
loop length	88
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	3.00	3.00	3.00	1.00	1.00
cycles	2.50	2.50	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	3.00	3.00	3.00	1.00	1.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.75
Overall L1	3.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

19% of peak load performance is reached (18.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (5.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 44c4e4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X1, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X1, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X3, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [X7, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X17, X7, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X2, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 44c520 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
B 44c820 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x4e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X6, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X14, [X6, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 44c844 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
B 44c944 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x604>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X5, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X5, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 44c4e4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:939-999
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.75 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 56 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	22
loop length	88
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	3.00	3.00	3.00	1.00	1.00
cycles	2.50	2.50	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	3.00	3.00	3.00	1.00	1.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.75
Overall L1	3.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

19% of peak load performance is reached (18.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (5.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 44c4e4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X1, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X1, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X3, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [X7, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X17, X7, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X2, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 44c520 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
B 44c820 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x4e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X6, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X14, [X6, X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 44c844 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
B 44c944 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x604>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X5, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X5, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 44c4e4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code