OV - exec - Loop 808

	Loop Id: 808	Module: exec	Source: par_multi_interp.c:1030-1034	Coverage: 0.02%

0x44cdf0 ADD	X15, X0, #1

0x44cdf4 ADD	X13, X0, #3

0x44cdf8 LDR	X3, [X10, X0,LSL #3]    [6]

0x44cdfc ADD	X14, X15, #1

0x44ce00 ADD	X0, X0, #4

0x44ce04 LDR	X16, [X2]    [3]

0x44ce08 LDR	X11, [X9, X3,LSL #3]    [9]

0x44ce0c ADD	X4, X11, X16

0x44ce10 STR	X4, [X9, X3,LSL #3]    [9]

0x44ce14 LDR	X17, [X8, X3,LSL #3]    [9]

0x44ce18 LDR	X30, [X1]    [10]

0x44ce1c ADD	X11, X17, X30

0x44ce20 STR	X11, [X8, X3,LSL #3]    [9]

0x44ce24 LDR	X3, [X10, X15,LSL #3]    [5]

0x44ce28 LDR	X15, [X2]    [3]

0x44ce2c LDR	X16, [X9, X3,LSL #3]    [4]

0x44ce30 ADD	X4, X16, X15

0x44ce34 STR	X4, [X9, X3,LSL #3]    [4]

0x44ce38 LDR	X17, [X8, X3,LSL #3]    [4]

0x44ce3c LDR	X30, [X1]    [10]

0x44ce40 ADD	X11, X17, X30

0x44ce44 STR	X11, [X8, X3,LSL #3]    [4]

0x44ce48 LDR	X3, [X10, X14,LSL #3]    [7]

0x44ce4c LDR	X14, [X2]    [3]

0x44ce50 LDR	X16, [X9, X3,LSL #3]    [8]

0x44ce54 ADD	X15, X16, X14

0x44ce58 STR	X15, [X9, X3,LSL #3]    [8]

0x44ce5c LDR	X4, [X8, X3,LSL #3]    [8]

0x44ce60 LDR	X17, [X1]    [10]

0x44ce64 ADD	X30, X4, X17

0x44ce68 STR	X30, [X8, X3,LSL #3]    [8]

0x44ce6c LDR	X3, [X10, X13,LSL #3]    [2]

0x44ce70 LDR	X13, [X2]    [3]

0x44ce74 LDR	X11, [X9, X3,LSL #3]    [1]

0x44ce78 ADD	X16, X11, X13

0x44ce7c STR	X16, [X9, X3,LSL #3]    [1]

0x44ce80 LDR	X14, [X8, X3,LSL #3]    [1]

0x44ce84 LDR	X15, [X1]    [10]

0x44ce88 ADD	X4, X14, X15

0x44ce8c STR	X4, [X8, X3,LSL #3]    [1]

0x44ce90 CMP	X12, X0

0x44ce94 B.GT	44cdf0

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1030 - 1034

--------------------------------------------------------------------------------

1030:               for (i=thread_start; i < thread_stop; i++)

1031:                {

1032:                    i1 = pass_array[i];

1033:                    P_diag_start[i1] += cnt_nz_per_thread[my_thread_num-1];

1034:                    P_offd_start[i1] += cnt_nz_offd_per_thread[my_thread_num-1];

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.78
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:1030-1034
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.33
CQA cycles if no scalar integer	9.33
CQA cycles if FP arith vectorized	9.33
CQA cycles if fully vectorized	2.33
Front-end cycles	5.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	3.25
P2 cycles	3.25
P3 cycles	3.25
P4 cycles	3.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	9.33
P10 cycles	9.33
P11 cycles	9.33
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	42.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.78
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:1030-1034
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.33
CQA cycles if no scalar integer	9.33
CQA cycles if FP arith vectorized	9.33
CQA cycles if fully vectorized	2.33
Front-end cycles	5.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	3.25
P2 cycles	3.25
P3 cycles	3.25
P4 cycles	3.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	9.33
P10 cycles	9.33
P11 cycles	9.33
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	42.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:1030-1034
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1030-1034.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 9.33 to 2.33 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 160 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	42
loop length	168
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	3.25	3.25	3.25	3.25	0.00	0.00	0.00	0.00	9.33	9.33	9.33	4.00	4.00
cycles	0.50	0.50	3.25	3.25	3.25	3.25	0.00	0.00	0.00	0.00	9.33	9.33	9.33	4.00	4.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.25
Data deps.	1.00
Overall L1	9.33

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.33 cycles. At this rate:

17% of peak load performance is reached (17.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (6.86 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 44cdf0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADD X15, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X13, X0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X3, [X10, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, X0, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X16, [X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X9, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X4, X11, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X4, [X9, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X17, [X8, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X17, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X8, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X10, X15,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X4, X16, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X4, [X9, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X17, [X8, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X17, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X8, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X10, X14,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X16, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X15, [X9, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X8, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X30, X4, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X30, [X8, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X10, X13,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X9, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X11, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X16, [X9, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X8, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X4, X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X4, [X8, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X12, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 44cdf0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xab0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:1030-1034
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 9.33 to 2.33 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 160 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	42
loop length	168
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	3.25	3.25	3.25	3.25	0.00	0.00	0.00	0.00	9.33	9.33	9.33	4.00	4.00
cycles	0.50	0.50	3.25	3.25	3.25	3.25	0.00	0.00	0.00	0.00	9.33	9.33	9.33	4.00	4.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.25
Data deps.	1.00
Overall L1	9.33

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.33 cycles. At this rate:

17% of peak load performance is reached (17.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (6.86 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 44cdf0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADD X15, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X13, X0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X3, [X10, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, X0, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X16, [X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X9, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X4, X11, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X4, [X9, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X17, [X8, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X17, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X8, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X10, X15,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X4, X16, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X4, [X9, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X17, [X8, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X17, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X8, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X10, X14,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X16, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X15, [X9, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X8, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X30, X4, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X30, [X8, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X10, X13,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X9, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X11, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X16, [X9, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X8, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X4, X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X4, [X8, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X12, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 44cdf0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xab0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code