OV - exec - Loop 805

	Loop Id: 805	Module: exec	Source: par_multi_interp.c:1075-1099	Coverage: 0.49%

0x44cf2c ADD	X2, X2, #1

0x44cf30 CMP	X2, X28

0x44cf34 B.GE	44d204

0x44cf38 LDR	X8, [X27, X2,LSL #3]

0x44cf3c LDR	X11, [X25, X8,LSL #3]

0x44cf40 UBFM	X15, X8, #61, #60

0x44cf44 CMP	X11, X13

0x44cf48 B.NE	44cf2c

0x44cf4c ADD	X12, X15, #8

0x44cf50 LDR	X17, [X9, X8,LSL #3]

0x44cf54 LDR	X14, [X23, X12]

0x44cf58 ADD	X15, X17, X14

0x44cf5c CMP	X17, X15

0x44cf60 B.GE	44d0a0

0x44cf64 LDR	X28, [SP, #144]

0x44cf68 LDUR	X28, [X28, #504]

0x44cf6c ADD	X15, X28, X15,LSL #3

0x44cf70 ADD	X11, X28, X17,LSL #3

0x44cf74 SUB	X14, X15, X11

0x44cf78 SUB	X14, X14, #8

0x44cf7c UBFM	X14, X14, #3, #63

0x44cf80 ADD	X14, X14, #1

0x44cf84 ANDS	X14, X14, #4160

0x44cf88 B.EQ	44d010

0x44cf8c CMP	X14, #1

0x44cf90 B.EQ	44cfe4

0x44cf94 CMP	X14, #2

0x44cf98 B.EQ	44cfc0

0x44cf9c LDR	X28, [X28, X17,LSL #3]

0x44cfa0 LDR	X17, [X20, X28,LSL #3]

0x44cfa4 CMP	X17, X0

0x44cfa8 B.EQ	44cfbc

0x44cfac LDR	X14, [X5, X22]

0x44cfb0 STR	X28, [X14, X3,LSL #3]

0x44cfb4 ADD	X3, X3, #1

0x44cfb8 STR	X0, [X20, X28,LSL #3]

0x44cfbc ADD	X11, X11, #8

0x44cfc0 LDR	X28, [X11]

0x44cfc4 LDR	X17, [X20, X28,LSL #3]

0x44cfc8 CMP	X17, X0

0x44cfcc B.EQ	44cfe0

0x44cfd0 LDR	X14, [X5, X22]

0x44cfd4 STR	X28, [X14, X3,LSL #3]

0x44cfd8 ADD	X3, X3, #1

0x44cfdc STR	X0, [X20, X28,LSL #3]

0x44cfe0 ADD	X11, X11, #8

0x44cfe4 LDR	X28, [X11]

0x44cfe8 LDR	X17, [X20, X28,LSL #3]

0x44cfec CMP	X17, X0

0x44cff0 B.EQ	44d004

0x44cff4 LDR	X14, [X5, X22]

0x44cff8 STR	X28, [X14, X3,LSL #3]

0x44cffc ADD	X3, X3, #1

0x44d000 STR	X0, [X20, X28,LSL #3]

0x44d004 ADD	X11, X11, #8

0x44d008 CMP	X15, X11

0x44d00c B.EQ	44d0a0

  (807) 0x44d010 LDR	X28, [X11]

  (807) 0x44d014 LDR	X17, [X20, X28,LSL #3]

  (807) 0x44d018 CMP	X17, X0

  (807) 0x44d01c B.EQ	44d030

  (807) 0x44d020 LDR	X14, [X5, X22]

  (807) 0x44d024 STR	X28, [X14, X3,LSL #3]

  (807) 0x44d028 ADD	X3, X3, #1

  (807) 0x44d02c STR	X0, [X20, X28,LSL #3]

  (807) 0x44d030 LDR	X28, [X11, #8]

  (807) 0x44d034 ADD	X14, X11, #8

  (807) 0x44d038 LDR	X11, [X20, X28,LSL #3]

  (807) 0x44d03c CMP	X11, X0

  (807) 0x44d040 B.EQ	44d054

  (807) 0x44d044 LDR	X17, [X5, X22]

  (807) 0x44d048 STR	X28, [X17, X3,LSL #3]

  (807) 0x44d04c ADD	X3, X3, #1

  (807) 0x44d050 STR	X0, [X20, X28,LSL #3]

  (807) 0x44d054 LDR	X17, [X14, #8]

  (807) 0x44d058 ADD	X11, X14, #24

  (807) 0x44d05c LDR	X28, [X20, X17,LSL #3]

  (807) 0x44d060 CMP	X28, X0

  (807) 0x44d064 B.EQ	44d078

  (807) 0x44d068 LDR	X28, [X5, X22]

  (807) 0x44d06c STR	X17, [X28, X3,LSL #3]

  (807) 0x44d070 ADD	X3, X3, #1

  (807) 0x44d074 STR	X0, [X20, X17,LSL #3]

  (807) 0x44d078 LDR	X14, [X14, #16]

  (807) 0x44d07c LDR	X17, [X20, X14,LSL #3]

  (807) 0x44d080 CMP	X17, X0

  (807) 0x44d084 B.EQ	44d098

  (807) 0x44d088 LDR	X28, [X5, X22]

  (807) 0x44d08c STR	X14, [X28, X3,LSL #3]

  (807) 0x44d090 ADD	X3, X3, #1

  (807) 0x44d094 STR	X0, [X20, X14,LSL #3]

  (807) 0x44d098 CMP	X15, X11

  (807) 0x44d09c B.NE	44d010

0x44d0a0 LDR	X15, [SP, #136]

0x44d0a4 LDR	X12, [X21, X12]

0x44d0a8 LDR	X14, [X15, X8,LSL #3]

0x44d0ac ADD	X11, X14, X12

0x44d0b0 CMP	X14, X11

0x44d0b4 B.GE	44d1f4

0x44d0b8 LDR	X8, [SP, #152]

0x44d0bc LDUR	X17, [X8, #504]

0x44d0c0 ADD	X28, X17, X11,LSL #3

0x44d0c4 ADD	X8, X17, X14,LSL #3

0x44d0c8 SUB	X12, X28, X8

0x44d0cc SUB	X15, X12, #8

0x44d0d0 UBFM	X11, X15, #3, #63

0x44d0d4 ADD	X12, X11, #1

0x44d0d8 ANDS	X15, X12, #4160

0x44d0dc B.EQ	44d164

0x44d0e0 CMP	X15, #1

0x44d0e4 B.EQ	44d138

0x44d0e8 CMP	X15, #2

0x44d0ec B.EQ	44d114

0x44d0f0 LDR	X17, [X17, X14,LSL #3]

0x44d0f4 LDR	X14, [X19, X17,LSL #3]

0x44d0f8 CMP	X14, X0

0x44d0fc B.EQ	44d110

0x44d100 LDR	X11, [X4, X22]

0x44d104 STR	X17, [X11, X1,LSL #3]

0x44d108 ADD	X1, X1, #1

0x44d10c STR	X0, [X19, X17,LSL #3]

0x44d110 ADD	X8, X8, #8

0x44d114 LDR	X12, [X8]

0x44d118 LDR	X15, [X19, X12,LSL #3]

0x44d11c CMP	X15, X0

0x44d120 B.EQ	44d134

0x44d124 LDR	X17, [X4, X22]

0x44d128 STR	X12, [X17, X1,LSL #3]

0x44d12c ADD	X1, X1, #1

0x44d130 STR	X0, [X19, X12,LSL #3]

0x44d134 ADD	X8, X8, #8

0x44d138 LDR	X11, [X8]

0x44d13c LDR	X14, [X19, X11,LSL #3]

0x44d140 CMP	X14, X0

0x44d144 B.EQ	44d158

0x44d148 LDR	X12, [X4, X22]

0x44d14c STR	X11, [X12, X1,LSL #3]

0x44d150 ADD	X1, X1, #1

0x44d154 STR	X0, [X19, X11,LSL #3]

0x44d158 ADD	X8, X8, #8

0x44d15c CMP	X8, X28

0x44d160 B.EQ	44d1f4

  (806) 0x44d164 LDR	X15, [X8]

  (806) 0x44d168 LDR	X17, [X19, X15,LSL #3]

  (806) 0x44d16c CMP	X17, X0

  (806) 0x44d170 B.EQ	44d184

  (806) 0x44d174 LDR	X11, [X4, X22]

  (806) 0x44d178 STR	X15, [X11, X1,LSL #3]

  (806) 0x44d17c ADD	X1, X1, #1

  (806) 0x44d180 STR	X0, [X19, X15,LSL #3]

  (806) 0x44d184 LDR	X14, [X8, #8]

  (806) 0x44d188 ADD	X12, X8, #8

  (806) 0x44d18c LDR	X8, [X19, X14,LSL #3]

  (806) 0x44d190 CMP	X8, X0

  (806) 0x44d194 B.EQ	44d1a8

  (806) 0x44d198 LDR	X15, [X4, X22]

  (806) 0x44d19c STR	X14, [X15, X1,LSL #3]

  (806) 0x44d1a0 ADD	X1, X1, #1

  (806) 0x44d1a4 STR	X0, [X19, X14,LSL #3]

  (806) 0x44d1a8 LDR	X17, [X12, #8]

  (806) 0x44d1ac ADD	X8, X12, #24

  (806) 0x44d1b0 LDR	X11, [X19, X17,LSL #3]

  (806) 0x44d1b4 CMP	X11, X0

  (806) 0x44d1b8 B.EQ	44d1cc

  (806) 0x44d1bc LDR	X14, [X4, X22]

  (806) 0x44d1c0 STR	X17, [X14, X1,LSL #3]

  (806) 0x44d1c4 ADD	X1, X1, #1

  (806) 0x44d1c8 STR	X0, [X19, X17,LSL #3]

  (806) 0x44d1cc LDR	X12, [X12, #16]

  (806) 0x44d1d0 LDR	X15, [X19, X12,LSL #3]

  (806) 0x44d1d4 CMP	X15, X0

  (806) 0x44d1d8 B.EQ	44d1ec

  (806) 0x44d1dc LDR	X17, [X4, X22]

  (806) 0x44d1e0 STR	X12, [X17, X1,LSL #3]

  (806) 0x44d1e4 ADD	X1, X1, #1

  (806) 0x44d1e8 STR	X0, [X19, X12,LSL #3]

  (806) 0x44d1ec CMP	X8, X28

  (806) 0x44d1f0 B.NE	44d164

0x44d1f4 LDR	X28, [X30]

0x44d1f8 ADD	X2, X2, #1

0x44d1fc CMP	X2, X28

0x44d200 B.LT	44cf38

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1075 - 1099

--------------------------------------------------------------------------------

1075:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1076:              {

1077:                 j1 = S_diag_j[j];

1078:                 if (assigned[j1] == pass-1)

1079:                 {

1080:                    j_start = P_diag_start[j1];

1081:                    j_end = j_start+P_diag_i[j1+1];

1082:                    for (k=j_start; k < j_end; k++)

1083:                    {

1084:                       k1 = P_diag_pass[pass-1][k];

1085:                       if (P_marker[k1] != -i1-1)

1086:                       {

1087:                           P_diag_pass[pass][cnt_nz++] = k1;

1088:                           P_marker[k1] = -i1-1;

1089:                       }

1090:                    }

1091:                    j_start = P_offd_start[j1];

1092:                    j_end = j_start+P_offd_i[j1+1];

1093:                    for (k=j_start; k < j_end; k++)

1094:                    {

1095:                       k1 = P_offd_pass[pass-1][k];

1096:                       if (P_marker_offd[k1] != -i1-1)

1097:                       {

1098:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1099:                          P_marker_offd[k1] = -i1-1;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:1075-1075,par_multi_interp.c:1078-1088,par_multi_interp.c:1091-1099
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.00
CQA cycles if no scalar integer	14.00
CQA cycles if FP arith vectorized	14.00
CQA cycles if fully vectorized	3.50
Front-end cycles	13.75
DIV/SQRT cycles	9.50
P0 cycles	9.50
P1 cycles	12.25
P2 cycles	12.25
P3 cycles	12.25
P4 cycles	12.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	14.00
P10 cycles	14.00
P11 cycles	14.00
P12 cycles	6.00
P13 cycles	6.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	110.00
Nb uops	110.00
Nb loads	NA
Nb stores	12.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	240.00
Bytes stored	96.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:1075-1075,par_multi_interp.c:1078-1088,par_multi_interp.c:1091-1099
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.00
CQA cycles if no scalar integer	14.00
CQA cycles if FP arith vectorized	14.00
CQA cycles if fully vectorized	3.50
Front-end cycles	13.75
DIV/SQRT cycles	9.50
P0 cycles	9.50
P1 cycles	12.25
P2 cycles	12.25
P3 cycles	12.25
P4 cycles	12.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	14.00
P10 cycles	14.00
P11 cycles	14.00
P12 cycles	6.00
P13 cycles	6.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	110.00
Nb uops	110.00
Nb loads	NA
Nb stores	12.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	240.00
Bytes stored	96.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:1075-1099
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1075-1099.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1075,1078-1088,1091-1099.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 65026 paths individually, rerun with max-paths=65026
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 65026 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 14.00 to 3.50 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 240 bytes. The binary loop is storing 96 bytes.

General properties

nb instructions	110
loop length	440
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	9.50	9.50	12.25	12.25	12.25	12.25	0.00	0.00	0.00	0.00	14.00	14.00	14.00	6.00	6.00
cycles	9.50	9.50	12.25	12.25	12.25	12.25	0.00	0.00	0.00	0.00	14.00	14.00	14.00	6.00	6.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.75
Overall L1	14.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.00 cycles. At this rate:

17% of peak load performance is reached (17.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (6.86 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 44cf38

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X2, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 44d204 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xec4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X27, X2,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X25, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X15, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X11, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 44cf2c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xbec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X12, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X17, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X23, X12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X17, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X17, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 44d0a0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xd60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X28, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X28, [X28, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X28, X15,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X11, X28, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X14, X15, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X14, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X14, X14, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ANDS X14, X14, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44d010 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xcd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44cfe4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xca4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44cfc0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xc80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X28, [X28, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X20, X28,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X17, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44cfbc <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xc7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [X5, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X28, [X14, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X20, X28,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X11, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X28, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X20, X28,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X17, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44cfe0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xca0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [X5, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X28, [X14, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X20, X28,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X11, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X28, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X20, X28,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X17, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44d004 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xcc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [X5, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X28, [X14, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X20, X28,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X11, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X15, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44d0a0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xd60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X21, X12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X15, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X14, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X14, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 44d1f4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xeb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X17, [X8, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X28, X17, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X8, X17, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X12, X28, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X15, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X11, X15, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X12, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ANDS X15, X12, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44d164 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xe24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44d138 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xdf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44d114 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xdd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X17, [X17, X14,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X19, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44d110 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xdd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X4, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X17, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X19, X17,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X8, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X12, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X19, X12,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X15, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44d134 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xdf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X17, [X4, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X12, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X19, X12,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X8, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X11, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X19, X11,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44d158 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xe18>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X12, [X4, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X11, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X19, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X8, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X8, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44d1f4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xeb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X28, [X30]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X2, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 44cf38 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xbf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:1075-1099
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 65026 paths individually, rerun with max-paths=65026
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 240 bytes. The binary loop is storing 96 bytes.

General properties

nb instructions	110
loop length	440
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	9.50	9.50	12.25	12.25	12.25	12.25	0.00	0.00	0.00	0.00	14.00	14.00	14.00	6.00	6.00
cycles	9.50	9.50	12.25	12.25	12.25	12.25	0.00	0.00	0.00	0.00	14.00	14.00	14.00	6.00	6.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.75
Overall L1	14.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.00 cycles. At this rate:

17% of peak load performance is reached (17.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (6.86 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 44cf38

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X2, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 44d204 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xec4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X27, X2,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X25, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X15, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X11, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 44cf2c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xbec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X12, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X17, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X23, X12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X17, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X17, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 44d0a0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xd60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X28, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X28, [X28, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X28, X15,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X11, X28, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X14, X15, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X14, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X14, X14, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ANDS X14, X14, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44d010 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xcd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44cfe4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xca4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44cfc0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xc80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X28, [X28, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X20, X28,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X17, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44cfbc <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xc7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [X5, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X28, [X14, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X20, X28,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X11, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X28, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X20, X28,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X17, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44cfe0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xca0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [X5, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X28, [X14, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X20, X28,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X11, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X28, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X20, X28,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X17, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44d004 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xcc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [X5, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X28, [X14, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X20, X28,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X11, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X15, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44d0a0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xd60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X21, X12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X15, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X14, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X14, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 44d1f4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xeb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X17, [X8, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X28, X17, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X8, X17, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X12, X28, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X15, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X11, X15, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X12, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ANDS X15, X12, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44d164 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xe24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44d138 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xdf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44d114 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xdd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X17, [X17, X14,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X19, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44d110 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xdd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X4, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X17, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X19, X17,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X8, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X12, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X19, X12,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X15, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44d134 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xdf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X17, [X4, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X12, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X19, X12,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X8, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X11, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X19, X11,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44d158 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xe18>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X12, [X4, X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X11, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X19, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X8, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X8, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44d1f4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xeb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X28, [X30]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X2, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 44cf38 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xbf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code