OV - exec - Loop 802

	Loop Id: 802	Module: exec	Source: par_multi_interp.c:1072-1125	Coverage: 0.03%

0x44cf00 LDR	X17, [SP, #104]

0x44cf04 LDR	X10, [X17, X18,LSL #3]

0x44cf08 UBFM	X30, X10, #61, #60

0x44cf0c LDR	X2, [X7, X10,LSL #3]

0x44cf10 ORN	X0, XZR, X10

0x44cf14 ADD	X16, X30, #8

0x44cf18 LDR	X28, [X7, X16]

0x44cf1c ADD	X30, X7, X16

0x44cf20 CMP	X28, X2

0x44cf24 B.GT	44cf38

0x44cf28 B	44d204

  (805) 0x44cf2c ADD	X2, X2, #1

  (805) 0x44cf30 CMP	X2, X28

  (805) 0x44cf34 B.GE	44d204

  (805) 0x44cf38 LDR	X8, [X27, X2,LSL #3]

  (805) 0x44cf3c LDR	X11, [X25, X8,LSL #3]

  (805) 0x44cf40 UBFM	X15, X8, #61, #60

  (805) 0x44cf44 CMP	X11, X13

  (805) 0x44cf48 B.NE	44cf2c

  (805) 0x44cf4c ADD	X12, X15, #8

  (805) 0x44cf50 LDR	X17, [X9, X8,LSL #3]

  (805) 0x44cf54 LDR	X14, [X23, X12]

  (805) 0x44cf58 ADD	X15, X17, X14

  (805) 0x44cf5c CMP	X17, X15

  (805) 0x44cf60 B.GE	44d0a0

  (805) 0x44cf64 LDR	X28, [SP, #144]

  (805) 0x44cf68 LDUR	X28, [X28, #504]

  (805) 0x44cf6c ADD	X15, X28, X15,LSL #3

  (805) 0x44cf70 ADD	X11, X28, X17,LSL #3

  (805) 0x44cf74 SUB	X14, X15, X11

  (805) 0x44cf78 SUB	X14, X14, #8

  (805) 0x44cf7c UBFM	X14, X14, #3, #63

  (805) 0x44cf80 ADD	X14, X14, #1

  (805) 0x44cf84 ANDS	X14, X14, #4160

  (805) 0x44cf88 B.EQ	44d010

  (805) 0x44cf8c CMP	X14, #1

  (805) 0x44cf90 B.EQ	44cfe4

  (805) 0x44cf94 CMP	X14, #2

  (805) 0x44cf98 B.EQ	44cfc0

  (805) 0x44cf9c LDR	X28, [X28, X17,LSL #3]

  (805) 0x44cfa0 LDR	X17, [X20, X28,LSL #3]

  (805) 0x44cfa4 CMP	X17, X0

  (805) 0x44cfa8 B.EQ	44cfbc

  (805) 0x44cfac LDR	X14, [X5, X22]

  (805) 0x44cfb0 STR	X28, [X14, X3,LSL #3]

  (805) 0x44cfb4 ADD	X3, X3, #1

  (805) 0x44cfb8 STR	X0, [X20, X28,LSL #3]

  (805) 0x44cfbc ADD	X11, X11, #8

  (805) 0x44cfc0 LDR	X28, [X11]

  (805) 0x44cfc4 LDR	X17, [X20, X28,LSL #3]

  (805) 0x44cfc8 CMP	X17, X0

  (805) 0x44cfcc B.EQ	44cfe0

  (805) 0x44cfd0 LDR	X14, [X5, X22]

  (805) 0x44cfd4 STR	X28, [X14, X3,LSL #3]

  (805) 0x44cfd8 ADD	X3, X3, #1

  (805) 0x44cfdc STR	X0, [X20, X28,LSL #3]

  (805) 0x44cfe0 ADD	X11, X11, #8

  (805) 0x44cfe4 LDR	X28, [X11]

  (805) 0x44cfe8 LDR	X17, [X20, X28,LSL #3]

  (805) 0x44cfec CMP	X17, X0

  (805) 0x44cff0 B.EQ	44d004

  (805) 0x44cff4 LDR	X14, [X5, X22]

  (805) 0x44cff8 STR	X28, [X14, X3,LSL #3]

  (805) 0x44cffc ADD	X3, X3, #1

  (805) 0x44d000 STR	X0, [X20, X28,LSL #3]

  (805) 0x44d004 ADD	X11, X11, #8

  (805) 0x44d008 CMP	X15, X11

  (805) 0x44d00c B.EQ	44d0a0

    (807) 0x44d010 LDR	X28, [X11]

    (807) 0x44d014 LDR	X17, [X20, X28,LSL #3]

    (807) 0x44d018 CMP	X17, X0

    (807) 0x44d01c B.EQ	44d030

    (807) 0x44d020 LDR	X14, [X5, X22]

    (807) 0x44d024 STR	X28, [X14, X3,LSL #3]

    (807) 0x44d028 ADD	X3, X3, #1

    (807) 0x44d02c STR	X0, [X20, X28,LSL #3]

    (807) 0x44d030 LDR	X28, [X11, #8]

    (807) 0x44d034 ADD	X14, X11, #8

    (807) 0x44d038 LDR	X11, [X20, X28,LSL #3]

    (807) 0x44d03c CMP	X11, X0

    (807) 0x44d040 B.EQ	44d054

    (807) 0x44d044 LDR	X17, [X5, X22]

    (807) 0x44d048 STR	X28, [X17, X3,LSL #3]

    (807) 0x44d04c ADD	X3, X3, #1

    (807) 0x44d050 STR	X0, [X20, X28,LSL #3]

    (807) 0x44d054 LDR	X17, [X14, #8]

    (807) 0x44d058 ADD	X11, X14, #24

    (807) 0x44d05c LDR	X28, [X20, X17,LSL #3]

    (807) 0x44d060 CMP	X28, X0

    (807) 0x44d064 B.EQ	44d078

    (807) 0x44d068 LDR	X28, [X5, X22]

    (807) 0x44d06c STR	X17, [X28, X3,LSL #3]

    (807) 0x44d070 ADD	X3, X3, #1

    (807) 0x44d074 STR	X0, [X20, X17,LSL #3]

    (807) 0x44d078 LDR	X14, [X14, #16]

    (807) 0x44d07c LDR	X17, [X20, X14,LSL #3]

    (807) 0x44d080 CMP	X17, X0

    (807) 0x44d084 B.EQ	44d098

    (807) 0x44d088 LDR	X28, [X5, X22]

    (807) 0x44d08c STR	X14, [X28, X3,LSL #3]

    (807) 0x44d090 ADD	X3, X3, #1

    (807) 0x44d094 STR	X0, [X20, X14,LSL #3]

    (807) 0x44d098 CMP	X15, X11

    (807) 0x44d09c B.NE	44d010

  (805) 0x44d0a0 LDR	X15, [SP, #136]

  (805) 0x44d0a4 LDR	X12, [X21, X12]

  (805) 0x44d0a8 LDR	X14, [X15, X8,LSL #3]

  (805) 0x44d0ac ADD	X11, X14, X12

  (805) 0x44d0b0 CMP	X14, X11

  (805) 0x44d0b4 B.GE	44d1f4

  (805) 0x44d0b8 LDR	X8, [SP, #152]

  (805) 0x44d0bc LDUR	X17, [X8, #504]

  (805) 0x44d0c0 ADD	X28, X17, X11,LSL #3

  (805) 0x44d0c4 ADD	X8, X17, X14,LSL #3

  (805) 0x44d0c8 SUB	X12, X28, X8

  (805) 0x44d0cc SUB	X15, X12, #8

  (805) 0x44d0d0 UBFM	X11, X15, #3, #63

  (805) 0x44d0d4 ADD	X12, X11, #1

  (805) 0x44d0d8 ANDS	X15, X12, #4160

  (805) 0x44d0dc B.EQ	44d164

  (805) 0x44d0e0 CMP	X15, #1

  (805) 0x44d0e4 B.EQ	44d138

  (805) 0x44d0e8 CMP	X15, #2

  (805) 0x44d0ec B.EQ	44d114

  (805) 0x44d0f0 LDR	X17, [X17, X14,LSL #3]

  (805) 0x44d0f4 LDR	X14, [X19, X17,LSL #3]

  (805) 0x44d0f8 CMP	X14, X0

  (805) 0x44d0fc B.EQ	44d110

  (805) 0x44d100 LDR	X11, [X4, X22]

  (805) 0x44d104 STR	X17, [X11, X1,LSL #3]

  (805) 0x44d108 ADD	X1, X1, #1

  (805) 0x44d10c STR	X0, [X19, X17,LSL #3]

  (805) 0x44d110 ADD	X8, X8, #8

  (805) 0x44d114 LDR	X12, [X8]

  (805) 0x44d118 LDR	X15, [X19, X12,LSL #3]

  (805) 0x44d11c CMP	X15, X0

  (805) 0x44d120 B.EQ	44d134

  (805) 0x44d124 LDR	X17, [X4, X22]

  (805) 0x44d128 STR	X12, [X17, X1,LSL #3]

  (805) 0x44d12c ADD	X1, X1, #1

  (805) 0x44d130 STR	X0, [X19, X12,LSL #3]

  (805) 0x44d134 ADD	X8, X8, #8

  (805) 0x44d138 LDR	X11, [X8]

  (805) 0x44d13c LDR	X14, [X19, X11,LSL #3]

  (805) 0x44d140 CMP	X14, X0

  (805) 0x44d144 B.EQ	44d158

  (805) 0x44d148 LDR	X12, [X4, X22]

  (805) 0x44d14c STR	X11, [X12, X1,LSL #3]

  (805) 0x44d150 ADD	X1, X1, #1

  (805) 0x44d154 STR	X0, [X19, X11,LSL #3]

  (805) 0x44d158 ADD	X8, X8, #8

  (805) 0x44d15c CMP	X8, X28

  (805) 0x44d160 B.EQ	44d1f4

    (806) 0x44d164 LDR	X15, [X8]

    (806) 0x44d168 LDR	X17, [X19, X15,LSL #3]

    (806) 0x44d16c CMP	X17, X0

    (806) 0x44d170 B.EQ	44d184

    (806) 0x44d174 LDR	X11, [X4, X22]

    (806) 0x44d178 STR	X15, [X11, X1,LSL #3]

    (806) 0x44d17c ADD	X1, X1, #1

    (806) 0x44d180 STR	X0, [X19, X15,LSL #3]

    (806) 0x44d184 LDR	X14, [X8, #8]

    (806) 0x44d188 ADD	X12, X8, #8

    (806) 0x44d18c LDR	X8, [X19, X14,LSL #3]

    (806) 0x44d190 CMP	X8, X0

    (806) 0x44d194 B.EQ	44d1a8

    (806) 0x44d198 LDR	X15, [X4, X22]

    (806) 0x44d19c STR	X14, [X15, X1,LSL #3]

    (806) 0x44d1a0 ADD	X1, X1, #1

    (806) 0x44d1a4 STR	X0, [X19, X14,LSL #3]

    (806) 0x44d1a8 LDR	X17, [X12, #8]

    (806) 0x44d1ac ADD	X8, X12, #24

    (806) 0x44d1b0 LDR	X11, [X19, X17,LSL #3]

    (806) 0x44d1b4 CMP	X11, X0

    (806) 0x44d1b8 B.EQ	44d1cc

    (806) 0x44d1bc LDR	X14, [X4, X22]

    (806) 0x44d1c0 STR	X17, [X14, X1,LSL #3]

    (806) 0x44d1c4 ADD	X1, X1, #1

    (806) 0x44d1c8 STR	X0, [X19, X17,LSL #3]

    (806) 0x44d1cc LDR	X12, [X12, #16]

    (806) 0x44d1d0 LDR	X15, [X19, X12,LSL #3]

    (806) 0x44d1d4 CMP	X15, X0

    (806) 0x44d1d8 B.EQ	44d1ec

    (806) 0x44d1dc LDR	X17, [X4, X22]

    (806) 0x44d1e0 STR	X12, [X17, X1,LSL #3]

    (806) 0x44d1e4 ADD	X1, X1, #1

    (806) 0x44d1e8 STR	X0, [X19, X12,LSL #3]

    (806) 0x44d1ec CMP	X8, X28

    (806) 0x44d1f0 B.NE	44d164

  (805) 0x44d1f4 LDR	X28, [X30]

  (805) 0x44d1f8 ADD	X2, X2, #1

  (805) 0x44d1fc CMP	X2, X28

  (805) 0x44d200 B.LT	44cf38

0x44d204 LDR	X0, [X6, X10,LSL #3]

0x44d208 ADD	X14, X6, X16

0x44d20c ORN	X10, XZR, X10

0x44d210 LDR	X15, [X6, X16]

0x44d214 CMP	X15, X0

0x44d218 B.GT	44d22c

0x44d21c B	44d328

  (803) 0x44d220 ADD	X0, X0, #1

  (803) 0x44d224 CMP	X0, X15

  (803) 0x44d228 B.GE	44d328

  (803) 0x44d22c LDR	X16, [X26, X0,LSL #3]

  (803) 0x44d230 LDR	X30, [X24, X16,LSL #3]

  (803) 0x44d234 UBFM	X11, X16, #61, #60

  (803) 0x44d238 CMP	X30, X13

  (803) 0x44d23c B.NE	44d220

  (803) 0x44d240 LDR	X8, [SP, #120]

  (803) 0x44d244 LDR	X28, [SP, #128]

  (803) 0x44d248 ADD	X12, X8, X11

  (803) 0x44d24c LDR	X17, [X12, #8]

  (803) 0x44d250 LDR	X16, [X28, X16,LSL #3]

  (803) 0x44d254 ADD	X30, X16, X17

  (803) 0x44d258 CMP	X16, X30

  (803) 0x44d25c B.GE	44d220

  (803) 0x44d260 LDR	X15, [SP, #96]

  (803) 0x44d264 LDR	X12, [X15, X22]

  (803) 0x44d268 ADD	X11, X12, X30,LSL #3

  (803) 0x44d26c ADD	X2, X12, X16,LSL #3

  (803) 0x44d270 SUB	X8, X11, X2

  (803) 0x44d274 SUB	X17, X8, #8

  (803) 0x44d278 UBFM	X28, X17, #3, #63

  (803) 0x44d27c ADD	X30, X28, #1

  (803) 0x44d280 ANDS	X15, X30, #4160

  (803) 0x44d284 B.EQ	44d3e8

  (803) 0x44d288 CMP	X15, #1

  (803) 0x44d28c B.EQ	44d2e8

  (803) 0x44d290 CMP	X15, #2

  (803) 0x44d294 B.EQ	44d2c0

  (803) 0x44d298 LDR	X16, [X12, X16,LSL #3]

  (803) 0x44d29c TBNZ	X16, #63, 44d4f8

  (803) 0x44d2a0 LDR	X12, [X19, X16,LSL #3]

  (803) 0x44d2a4 CMP	X12, X10

  (803) 0x44d2a8 B.EQ	44d2bc

  (803) 0x44d2ac LDR	X8, [X4, X22]

  (803) 0x44d2b0 STR	X16, [X8, X1,LSL #3]

  (803) 0x44d2b4 ADD	X1, X1, #1

  (803) 0x44d2b8 STR	X10, [X19, X16,LSL #3]

  (803) 0x44d2bc ADD	X2, X2, #8

  (803) 0x44d2c0 LDR	X16, [X2]

  (803) 0x44d2c4 TBNZ	X16, #63, 44d4d4

  (803) 0x44d2c8 LDR	X12, [X19, X16,LSL #3]

  (803) 0x44d2cc CMP	X12, X10

  (803) 0x44d2d0 B.EQ	44d2e4

  (803) 0x44d2d4 LDR	X8, [X4, X22]

  (803) 0x44d2d8 STR	X16, [X8, X1,LSL #3]

  (803) 0x44d2dc ADD	X1, X1, #1

  (803) 0x44d2e0 STR	X10, [X19, X16,LSL #3]

  (803) 0x44d2e4 ADD	X2, X2, #8

  (803) 0x44d2e8 LDR	X16, [X2]

  (803) 0x44d2ec TBNZ	X16, #63, 44d4b0

  (803) 0x44d2f0 LDR	X12, [X19, X16,LSL #3]

  (803) 0x44d2f4 CMP	X12, X10

  (803) 0x44d2f8 B.EQ	44d30c

  (803) 0x44d2fc LDR	X8, [X4, X22]

  (803) 0x44d300 STR	X16, [X8, X1,LSL #3]

  (803) 0x44d304 ADD	X1, X1, #1

  (803) 0x44d308 STR	X10, [X19, X16,LSL #3]

  (803) 0x44d30c ADD	X2, X2, #8

  (803) 0x44d310 CMP	X11, X2

  (803) 0x44d314 B.NE	44d3e8

  (803) 0x44d318 LDR	X15, [X14]

  (803) 0x44d31c ADD	X0, X0, #1

  (803) 0x44d320 CMP	X0, X15

  (803) 0x44d324 B.LT	44d22c

0x44d328 LDR	X11, [SP, #112]

0x44d32c ADD	X18, X18, #1

0x44d330 CMP	X11, X18

0x44d334 B.GT	44cf00

    (804) 0x44d378 LDR	X12, [X19, X16,LSL #3]

    (804) 0x44d37c CMP	X12, X10

    (804) 0x44d380 B.EQ	44d394

    (804) 0x44d384 LDR	X8, [X4, X22]

    (804) 0x44d388 STR	X16, [X8, X1,LSL #3]

    (804) 0x44d38c ADD	X1, X1, #1

    (804) 0x44d390 STR	X10, [X19, X16,LSL #3]

    (804) 0x44d394 LDR	X16, [X2, #8]

    (804) 0x44d398 TBNZ	X16, #63, 44d440

    (804) 0x44d39c LDR	X12, [X19, X16,LSL #3]

    (804) 0x44d3a0 CMP	X12, X10

    (804) 0x44d3a4 B.EQ	44d3b8

    (804) 0x44d3a8 LDR	X8, [X4, X22]

    (804) 0x44d3ac STR	X16, [X8, X1,LSL #3]

    (804) 0x44d3b0 ADD	X1, X1, #1

    (804) 0x44d3b4 STR	X10, [X19, X16,LSL #3]

    (804) 0x44d3b8 LDR	X16, [X2, #16]

    (804) 0x44d3bc TBNZ	X16, #63, 44d468

    (804) 0x44d3c0 LDR	X12, [X19, X16,LSL #3]

    (804) 0x44d3c4 CMP	X12, X10

    (804) 0x44d3c8 B.EQ	44d3dc

    (804) 0x44d3cc LDR	X8, [X4, X22]

    (804) 0x44d3d0 STR	X16, [X8, X1,LSL #3]

    (804) 0x44d3d4 ADD	X1, X1, #1

    (804) 0x44d3d8 STR	X10, [X19, X16,LSL #3]

    (804) 0x44d3dc ADD	X2, X2, #24

    (804) 0x44d3e0 CMP	X11, X2

    (804) 0x44d3e4 B.EQ	44d318

    (804) 0x44d3e8 LDR	X16, [X2]

    (804) 0x44d3ec TBNZ	X16, #63, 44d48c

    (804) 0x44d3f0 LDR	X12, [X19, X16,LSL #3]

    (804) 0x44d3f4 CMP	X12, X10

    (804) 0x44d3f8 B.EQ	44d40c

    (804) 0x44d3fc LDR	X8, [X4, X22]

    (804) 0x44d400 STR	X16, [X8, X1,LSL #3]

    (804) 0x44d404 ADD	X1, X1, #1

    (804) 0x44d408 STR	X10, [X19, X16,LSL #3]

    (804) 0x44d40c LDR	X16, [X2, #8]

    (804) 0x44d410 ADD	X2, X2, #8

    (804) 0x44d414 TBZ	X16, #63, 44d378

    (804) 0x44d418 ORN	X17, XZR, X16

    (804) 0x44d41c LDR	X28, [X20, X17,LSL #3]

    (804) 0x44d420 CMP	X28, X10

    (804) 0x44d424 B.EQ	44d394

    (804) 0x44d428 LDR	X30, [X5, X22]

    (804) 0x44d42c STR	X17, [X30, X3,LSL #3]

    (804) 0x44d430 ADD	X3, X3, #1

    (804) 0x44d434 STR	X10, [X20, X17,LSL #3]

    (804) 0x44d438 LDR	X16, [X2, #8]

    (804) 0x44d43c TBZ	X16, #63, 44d39c

    (804) 0x44d440 ORN	X17, XZR, X16

    (804) 0x44d444 LDR	X28, [X20, X17,LSL #3]

    (804) 0x44d448 CMP	X28, X10

    (804) 0x44d44c B.EQ	44d3b8

    (804) 0x44d450 LDR	X30, [X5, X22]

    (804) 0x44d454 STR	X17, [X30, X3,LSL #3]

    (804) 0x44d458 ADD	X3, X3, #1

    (804) 0x44d45c STR	X10, [X20, X17,LSL #3]

    (804) 0x44d460 LDR	X16, [X2, #16]

    (804) 0x44d464 TBZ	X16, #63, 44d3c0

    (804) 0x44d468 ORN	X17, XZR, X16

    (804) 0x44d46c LDR	X28, [X20, X17,LSL #3]

    (804) 0x44d470 CMP	X28, X10

    (804) 0x44d474 B.EQ	44d3dc

    (804) 0x44d478 LDR	X30, [X5, X22]

    (804) 0x44d47c STR	X17, [X30, X3,LSL #3]

    (804) 0x44d480 ADD	X3, X3, #1

    (804) 0x44d484 STR	X10, [X20, X17,LSL #3]

    (804) 0x44d488 B	44d3dc

    (804) 0x44d48c ORN	X17, XZR, X16

    (804) 0x44d490 LDR	X28, [X20, X17,LSL #3]

    (804) 0x44d494 CMP	X28, X10

    (804) 0x44d498 B.EQ	44d40c

    (804) 0x44d49c LDR	X30, [X5, X22]

    (804) 0x44d4a0 STR	X17, [X30, X3,LSL #3]

    (804) 0x44d4a4 ADD	X3, X3, #1

    (804) 0x44d4a8 STR	X10, [X20, X17,LSL #3]

    (804) 0x44d4ac B	44d40c

  (803) 0x44d4b0 ORN	X17, XZR, X16

  (803) 0x44d4b4 LDR	X28, [X20, X17,LSL #3]

  (803) 0x44d4b8 CMP	X28, X10

  (803) 0x44d4bc B.EQ	44d30c

  (803) 0x44d4c0 LDR	X30, [X5, X22]

  (803) 0x44d4c4 STR	X17, [X30, X3,LSL #3]

  (803) 0x44d4c8 ADD	X3, X3, #1

  (803) 0x44d4cc STR	X10, [X20, X17,LSL #3]

  (803) 0x44d4d0 B	44d30c

  (803) 0x44d4d4 ORN	X17, XZR, X16

  (803) 0x44d4d8 LDR	X28, [X20, X17,LSL #3]

  (803) 0x44d4dc CMP	X28, X10

  (803) 0x44d4e0 B.EQ	44d2e4

  (803) 0x44d4e4 LDR	X30, [X5, X22]

  (803) 0x44d4e8 STR	X17, [X30, X3,LSL #3]

  (803) 0x44d4ec ADD	X3, X3, #1

  (803) 0x44d4f0 STR	X10, [X20, X17,LSL #3]

  (803) 0x44d4f4 B	44d2e4

  (803) 0x44d4f8 ORN	X17, XZR, X16

  (803) 0x44d4fc LDR	X28, [X20, X17,LSL #3]

  (803) 0x44d500 CMP	X28, X10

  (803) 0x44d504 B.EQ	44d2bc

  (803) 0x44d508 LDR	X30, [X5, X22]

  (803) 0x44d50c STR	X17, [X30, X3,LSL #3]

  (803) 0x44d510 ADD	X3, X3, #1

  (803) 0x44d514 STR	X10, [X20, X17,LSL #3]

  (803) 0x44d518 B	44d2bc

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1072 - 1125

--------------------------------------------------------------------------------

1072:           for (i=thread_start; i < thread_stop; i++)

1073:           {

1074:              i1 = pass_array[i];

1075:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1076:              {

1077:                 j1 = S_diag_j[j];

1078:                 if (assigned[j1] == pass-1)

1079:                 {

1080:                    j_start = P_diag_start[j1];

1081:                    j_end = j_start+P_diag_i[j1+1];

1082:                    for (k=j_start; k < j_end; k++)

1083:                    {

1084:                       k1 = P_diag_pass[pass-1][k];

1085:                       if (P_marker[k1] != -i1-1)

1086:                       {

1087:                           P_diag_pass[pass][cnt_nz++] = k1;

1088:                           P_marker[k1] = -i1-1;

1089:                       }

1090:                    }

1091:                    j_start = P_offd_start[j1];

1092:                    j_end = j_start+P_offd_i[j1+1];

1093:                    for (k=j_start; k < j_end; k++)

1094:                    {

1095:                       k1 = P_offd_pass[pass-1][k];

1096:                       if (P_marker_offd[k1] != -i1-1)

1097:                       {

1098:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1099:                          P_marker_offd[k1] = -i1-1;

1100:                       }

1101:                    }

1102:                 }

1103:              }

1104:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1105:              {

1106:                 j1 = S_offd_j[j];

1107:                 if (assigned_offd[j1] == pass-1)

1108:                 {

1109:                    j_start = Pext_start[j1];

1110:                    j_end = j_start+Pext_i[j1+1];

1111:                    for (k=j_start; k < j_end; k++)

1112:                    {

1113:                       k1 = Pext_pass[pass][k];

1114:                       if (k1 < 0)

1115:                       {

1116:                          if (P_marker[-k1-1] != -i1-1)

1117:                          {

1118:                             P_diag_pass[pass][cnt_nz++] = -k1-1;

1119:                             P_marker[-k1-1] = -i1-1;

1120:                          }

1121:                       }

1122:                       else if (P_marker_offd[k1] != -i1-1)

1123:                       {

1124:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1125:                          P_marker_offd[k1] = -i1-1;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:1072-1075,par_multi_interp.c:1104-1104,par_multi_interp.c:1122-1122
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.75
CQA cycles if no scalar integer	2.75
CQA cycles if FP arith vectorized	2.75
CQA cycles if fully vectorized	0.69
Front-end cycles	2.75
DIV/SQRT cycles	2.50
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.33
P10 cycles	2.33
P11 cycles	2.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	22.00
Nb uops	22.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.36
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:1072-1075,par_multi_interp.c:1104-1104,par_multi_interp.c:1122-1122
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.75
CQA cycles if no scalar integer	2.75
CQA cycles if FP arith vectorized	2.75
CQA cycles if fully vectorized	0.69
Front-end cycles	2.75
DIV/SQRT cycles	2.50
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.33
P10 cycles	2.33
P11 cycles	2.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	22.00
Nb uops	22.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.36
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:1072-1125
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1072-1125.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1072-1075,1104,1122.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 2.75 to 0.69 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 56 bytes.

General properties

nb instructions	22
loop length	88
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	2.33	2.33	2.33	0.00	0.00
cycles	2.50	2.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	2.33	2.33	2.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.75
Overall L1	2.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.75 cycles. At this rate:

21% of peak load performance is reached (20.36 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 44cf00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDR X17, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X10, [X17, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
UBFM X30, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X2, [X7, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORN X0, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X16, X30, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X28, [X7, X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X30, X7, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X28, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GT 44cf38 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xbf8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
B 44d204 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xec4>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X0, [X6, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X14, X6, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORN X10, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X15, [X6, X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X15, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GT 44d22c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xeec>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
B 44d328 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xfe8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X11, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GT 44cf00 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xbc0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:1072-1125
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 2.75 to 0.69 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 56 bytes.

General properties

nb instructions	22
loop length	88
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	2.33	2.33	2.33	0.00	0.00
cycles	2.50	2.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	2.33	2.33	2.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.75
Overall L1	2.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.75 cycles. At this rate:

21% of peak load performance is reached (20.36 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 44cf00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDR X17, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X10, [X17, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
UBFM X30, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X2, [X7, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORN X0, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X16, X30, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X28, [X7, X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X30, X7, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X28, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GT 44cf38 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xbf8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
B 44d204 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xec4>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X0, [X6, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X14, X6, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORN X10, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X15, [X6, X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X15, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GT 44d22c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xeec>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
B 44d328 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xfe8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X11, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GT 44cf00 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xbc0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code