OV - exec - Loop 3729

	Loop Id: 3729	Module: exec	Source: csr_matvec.c:564-567	Coverage: 0.61%

0x50cb00 LDR	X1, [X14, X18,LSL #3]

0x50cb04 LDR	X11, [X13, X18,LSL #3]

0x50cb08 CMP	X1, X11

0x50cb0c B.GE	50cc1c

0x50cb10 SUB	X0, X11, X1

0x50cb14 ANDS	X3, X0, #4160

0x50cb18 B.EQ	50cb94

0x50cb1c CMP	X3, #1

0x50cb20 B.EQ	50cb6c

0x50cb24 CMP	X3, #2

0x50cb28 B.EQ	50cb4c

0x50cb2c LDR	X4, [X26, X1,LSL #3]

0x50cb30 LDR	D2, [X27, X1,LSL #3]

0x50cb34 ADD	X1, X1, #1

0x50cb38 LDR	D1, [X25, X18,LSL #3]

0x50cb3c ADD	X5, X16, X4

0x50cb40 LDR	D0, [X19, X5,LSL #3]

0x50cb44 FMADD	D3, D2, D1, D0

0x50cb48 STR	D3, [X19, X5,LSL #3]

0x50cb4c LDR	X6, [X26, X1,LSL #3]

0x50cb50 LDR	D4, [X27, X1,LSL #3]

0x50cb54 ADD	X1, X1, #1

0x50cb58 LDR	D5, [X25, X18,LSL #3]

0x50cb5c ADD	X7, X16, X6

0x50cb60 LDR	D6, [X19, X7,LSL #3]

0x50cb64 FMADD	D7, D4, D5, D6

0x50cb68 STR	D7, [X19, X7,LSL #3]

0x50cb6c LDR	X10, [X26, X1,LSL #3]

0x50cb70 LDR	D16, [X27, X1,LSL #3]

0x50cb74 ADD	X1, X1, #1

0x50cb78 LDR	D17, [X25, X18,LSL #3]

0x50cb7c ADD	X17, X16, X10

0x50cb80 LDR	D18, [X19, X17,LSL #3]

0x50cb84 FMADD	D19, D16, D17, D18

0x50cb88 STR	D19, [X19, X17,LSL #3]

0x50cb8c CMP	X1, X11

0x50cb90 B.EQ	50cc1c

  (3730) 0x50cb94 LDR	X0, [X26, X1,LSL #3]

  (3730) 0x50cb98 ADD	X6, X1, #1

  (3730) 0x50cb9c ADD	X7, X1, #3

  (3730) 0x50cba0 ADD	X10, X1, #2

  (3730) 0x50cba4 LDR	D19, [X27, X1,LSL #3]

  (3730) 0x50cba8 ADD	X1, X1, #4

  (3730) 0x50cbac LDR	D20, [X25, X18,LSL #3]

  (3730) 0x50cbb0 ADD	X5, X16, X0

  (3730) 0x50cbb4 LDR	X4, [X26, X6,LSL #3]

  (3730) 0x50cbb8 LDR	D21, [X19, X5,LSL #3]

  (3730) 0x50cbbc LDR	X3, [X26, X10,LSL #3]

  (3730) 0x50cbc0 ADD	X9, X16, X4

  (3730) 0x50cbc4 LDR	X17, [X26, X7,LSL #3]

  (3730) 0x50cbc8 FMADD	D22, D19, D20, D21

  (3730) 0x50cbcc ADD	X30, X16, X3

  (3730) 0x50cbd0 ADD	X17, X16, X17

  (3730) 0x50cbd4 STR	D22, [X19, X5,LSL #3]

  (3730) 0x50cbd8 LDR	D23, [X27, X6,LSL #3]

  (3730) 0x50cbdc LDR	D24, [X25, X18,LSL #3]

  (3730) 0x50cbe0 LDR	D25, [X19, X9,LSL #3]

  (3730) 0x50cbe4 FMADD	D26, D23, D24, D25

  (3730) 0x50cbe8 STR	D26, [X19, X9,LSL #3]

  (3730) 0x50cbec LDR	D27, [X27, X10,LSL #3]

  (3730) 0x50cbf0 LDR	D28, [X25, X18,LSL #3]

  (3730) 0x50cbf4 LDR	D29, [X19, X30,LSL #3]

  (3730) 0x50cbf8 FMADD	D30, D27, D28, D29

  (3730) 0x50cbfc STR	D30, [X19, X30,LSL #3]

  (3730) 0x50cc00 LDR	D16, [X27, X7,LSL #3]

  (3730) 0x50cc04 LDR	D17, [X25, X18,LSL #3]

  (3730) 0x50cc08 LDR	D18, [X19, X17,LSL #3]

  (3730) 0x50cc0c FMADD	D19, D16, D17, D18

  (3730) 0x50cc10 STR	D19, [X19, X17,LSL #3]

  (3730) 0x50cc14 CMP	X1, X11

  (3730) 0x50cc18 B.NE	50cb94

0x50cc1c ADD	X18, X18, #1

0x50cc20 CMP	X15, X18

0x50cc24 B.NE	50cb00

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 564 - 567

--------------------------------------------------------------------------------

564:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

565:                {

566:                   j = A_j[jj];

567:                   y_data_expand[offset + j] += A_data[jj] * x_data[i];

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.40
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	P10,
Function	hypre_CSRMatrixMatvecT._omp_fn.3
Source	csr_matvec.c:564-564,csr_matvec.c:567-567
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.83
CQA cycles if no scalar integer	4.17
CQA cycles if FP arith vectorized	5.83
CQA cycles if fully vectorized	1.46
Front-end cycles	5.00
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	3.50
P2 cycles	3.50
P3 cycles	3.50
P4 cycles	3.50
P5 cycles	1.50
P6 cycles	1.50
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	5.83
P10 cycles	5.50
P11 cycles	5.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	40.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	1.03
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	3.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.31
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.40
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	P10,
Function	hypre_CSRMatrixMatvecT._omp_fn.3
Source	csr_matvec.c:564-564,csr_matvec.c:567-567
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.83
CQA cycles if no scalar integer	4.17
CQA cycles if FP arith vectorized	5.83
CQA cycles if fully vectorized	1.46
Front-end cycles	5.00
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	3.50
P2 cycles	3.50
P3 cycles	3.50
P4 cycles	3.50
P5 cycles	1.50
P6 cycles	1.50
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	5.83
P10 cycles	5.50
P11 cycles	5.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	40.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	1.03
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	3.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.31
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_CSRMatrixMatvecT._omp_fn.3
Source file and lines	csr_matvec.c:564-567
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:564-567.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:564,567.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.83 to 4.17 cycles (1.40x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 5.83 to 1.46 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 3 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

3: addition or subtraction (all inside FMA instructions)
3: multiply (all inside FMA instructions)

The binary loop is loading 112 bytes. The binary loop is storing 24 bytes.

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	40
loop length	160
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	3.50	3.50	3.50	3.50	1.50	1.50	1.50	1.50	5.83	5.50	5.67	0.00	0.00
cycles	3.00	3.00	3.50	3.50	3.50	3.50	1.50	1.50	1.50	1.50	5.83	5.50	5.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.00
Overall L1	5.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.83 cycles. At this rate:

20% of peak load performance is reached (19.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (4.11 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 50cb00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR X1, [X14, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X11, [X13, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X1, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 50cc1c <hypre_CSRMatrixMatvecT._omp_fn.3+0x19c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X0, X11, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ANDS X3, X0, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50cb94 <hypre_CSRMatrixMatvecT._omp_fn.3+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50cb6c <hypre_CSRMatrixMatvecT._omp_fn.3+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50cb4c <hypre_CSRMatrixMatvecT._omp_fn.3+0xcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X4, [X26, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D2, [X27, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D1, [X25, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X5, X16, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D0, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D3, D2, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STR D3, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR X6, [X26, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D4, [X27, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D5, [X25, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X7, X16, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D6, [X19, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D7, D4, D5, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STR D7, [X19, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR X10, [X26, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D16, [X27, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D17, [X25, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X17, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D18, [X19, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D19, D16, D17, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STR D19, [X19, X17,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
CMP X1, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50cc1c <hypre_CSRMatrixMatvecT._omp_fn.3+0x19c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X15, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 50cb00 <hypre_CSRMatrixMatvecT._omp_fn.3+0x80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_CSRMatrixMatvecT._omp_fn.3
Source file and lines	csr_matvec.c:564-567
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.83 to 4.17 cycles (1.40x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 5.83 to 1.46 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 3 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

3: addition or subtraction (all inside FMA instructions)
3: multiply (all inside FMA instructions)

The binary loop is loading 112 bytes. The binary loop is storing 24 bytes.

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	40
loop length	160
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	3.50	3.50	3.50	3.50	1.50	1.50	1.50	1.50	5.83	5.50	5.67	0.00	0.00
cycles	3.00	3.00	3.50	3.50	3.50	3.50	1.50	1.50	1.50	1.50	5.83	5.50	5.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.00
Overall L1	5.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.83 cycles. At this rate:

20% of peak load performance is reached (19.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (4.11 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 50cb00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR X1, [X14, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X11, [X13, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X1, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 50cc1c <hypre_CSRMatrixMatvecT._omp_fn.3+0x19c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X0, X11, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ANDS X3, X0, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50cb94 <hypre_CSRMatrixMatvecT._omp_fn.3+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50cb6c <hypre_CSRMatrixMatvecT._omp_fn.3+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50cb4c <hypre_CSRMatrixMatvecT._omp_fn.3+0xcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X4, [X26, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D2, [X27, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D1, [X25, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X5, X16, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D0, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D3, D2, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STR D3, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR X6, [X26, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D4, [X27, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D5, [X25, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X7, X16, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D6, [X19, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D7, D4, D5, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STR D7, [X19, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR X10, [X26, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D16, [X27, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D17, [X25, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X17, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D18, [X19, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D19, D16, D17, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STR D19, [X19, X17,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
CMP X1, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50cc1c <hypre_CSRMatrixMatvecT._omp_fn.3+0x19c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X15, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 50cb00 <hypre_CSRMatrixMatvecT._omp_fn.3+0x80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code