OV - exec - Loop 3714

	Loop Id: 3714	Module: exec	Source: csr_matvec.c:256-263	Coverage: 0.94%

0x50b188 LDR	X1, [X24, X22,LSL #3]

0x50b18c MOVI	D0, #0

0x50b190 LDR	X16, [X26, X22,LSL #3]

0x50b194 CMP	X16, X1

0x50b198 B.LE	50b314

0x50b19c SUB	X2, X16, X1

0x50b1a0 ANDS	X10, X2, #4224

0x50b1a4 B.EQ	50b26c

0x50b1a8 CMP	X10, #1

0x50b1ac B.EQ	50b250

0x50b1b0 CMP	X10, #2

0x50b1b4 B.EQ	50b23c

0x50b1b8 CMP	X10, #3

0x50b1bc B.EQ	50b228

0x50b1c0 CMP	X10, #4

0x50b1c4 B.EQ	50b214

0x50b1c8 CMP	X10, #5

0x50b1cc B.EQ	50b200

0x50b1d0 CMP	X10, #6

0x50b1d4 B.EQ	50b1ec

0x50b1d8 LDR	X8, [X20, X1,LSL #3]

0x50b1dc LDR	D16, [X21, X1,LSL #3]

0x50b1e0 ADD	X1, X1, #1

0x50b1e4 LDR	D17, [X19, X8,LSL #3]

0x50b1e8 FMADD	D0, D16, D17, D0

0x50b1ec LDR	X11, [X20, X1,LSL #3]

0x50b1f0 LDR	D18, [X21, X1,LSL #3]

0x50b1f4 ADD	X1, X1, #1

0x50b1f8 LDR	D3, [X19, X11,LSL #3]

0x50b1fc FMADD	D0, D18, D3, D0

0x50b200 LDR	X17, [X20, X1,LSL #3]

0x50b204 LDR	D19, [X21, X1,LSL #3]

0x50b208 ADD	X1, X1, #1

0x50b20c LDR	D20, [X19, X17,LSL #3]

0x50b210 FMADD	D0, D19, D20, D0

0x50b214 LDR	X0, [X20, X1,LSL #3]

0x50b218 LDR	D21, [X21, X1,LSL #3]

0x50b21c ADD	X1, X1, #1

0x50b220 LDR	D4, [X19, X0,LSL #3]

0x50b224 FMADD	D0, D21, D4, D0

0x50b228 LDR	X12, [X20, X1,LSL #3]

0x50b22c LDR	D22, [X21, X1,LSL #3]

0x50b230 ADD	X1, X1, #1

0x50b234 LDR	D23, [X19, X12,LSL #3]

0x50b238 FMADD	D0, D22, D23, D0

0x50b23c LDR	X7, [X20, X1,LSL #3]

0x50b240 LDR	D2, [X21, X1,LSL #3]

0x50b244 ADD	X1, X1, #1

0x50b248 LDR	D1, [X19, X7,LSL #3]

0x50b24c FMADD	D0, D2, D1, D0

0x50b250 LDR	X6, [X20, X1,LSL #3]

0x50b254 LDR	D24, [X21, X1,LSL #3]

0x50b258 ADD	X1, X1, #1

0x50b25c LDR	D9, [X19, X6,LSL #3]

0x50b260 FMADD	D0, D24, D9, D0

0x50b264 CMP	X16, X1

0x50b268 B.EQ	50b314

  (3715) 0x50b26c LDR	X13, [X20, X1,LSL #3]

  (3715) 0x50b270 ADD	X14, X1, #1

  (3715) 0x50b274 ADD	X18, X1, #2

  (3715) 0x50b278 ADD	X15, X1, #3

  (3715) 0x50b27c ADD	X30, X1, #4

  (3715) 0x50b280 LDR	D25, [X21, X1,LSL #3]

  (3715) 0x50b284 ADD	X5, X1, #5

  (3715) 0x50b288 ADD	X4, X1, #6

  (3715) 0x50b28c ADD	X3, X1, #7

  (3715) 0x50b290 ADD	X1, X1, #8

  (3715) 0x50b294 LDR	X9, [X20, X14,LSL #3]

  (3715) 0x50b298 LDR	D26, [X19, X13,LSL #3]

  (3715) 0x50b29c LDR	D27, [X21, X14,LSL #3]

  (3715) 0x50b2a0 LDR	D28, [X19, X9,LSL #3]

  (3715) 0x50b2a4 LDR	X27, [X20, X18,LSL #3]

  (3715) 0x50b2a8 FMADD	D8, D25, D26, D0

  (3715) 0x50b2ac LDR	D29, [X21, X18,LSL #3]

  (3715) 0x50b2b0 LDR	X2, [X20, X15,LSL #3]

  (3715) 0x50b2b4 FMADD	D30, D27, D28, D8

  (3715) 0x50b2b8 LDR	D31, [X19, X27,LSL #3]

  (3715) 0x50b2bc LDR	D5, [X21, X15,LSL #3]

  (3715) 0x50b2c0 LDR	D6, [X19, X2,LSL #3]

  (3715) 0x50b2c4 LDR	X10, [X20, X30,LSL #3]

  (3715) 0x50b2c8 FMADD	D7, D29, D31, D30

  (3715) 0x50b2cc LDR	D16, [X21, X30,LSL #3]

  (3715) 0x50b2d0 LDR	X8, [X20, X5,LSL #3]

  (3715) 0x50b2d4 FMADD	D17, D5, D6, D7

  (3715) 0x50b2d8 LDR	D18, [X19, X10,LSL #3]

  (3715) 0x50b2dc LDR	D3, [X21, X5,LSL #3]

  (3715) 0x50b2e0 LDR	D19, [X19, X8,LSL #3]

  (3715) 0x50b2e4 LDR	X11, [X20, X4,LSL #3]

  (3715) 0x50b2e8 FMADD	D20, D16, D18, D17

  (3715) 0x50b2ec LDR	D21, [X21, X4,LSL #3]

  (3715) 0x50b2f0 LDR	X17, [X20, X3,LSL #3]

  (3715) 0x50b2f4 FMADD	D4, D3, D19, D20

  (3715) 0x50b2f8 LDR	D22, [X19, X11,LSL #3]

  (3715) 0x50b2fc LDR	D23, [X21, X3,LSL #3]

  (3715) 0x50b300 LDR	D2, [X19, X17,LSL #3]

  (3715) 0x50b304 FMADD	D1, D21, D22, D4

  (3715) 0x50b308 FMADD	D0, D23, D2, D1

  (3715) 0x50b30c CMP	X16, X1

  (3715) 0x50b310 B.NE	50b26c

0x50b314 STR	D0, [X25, X22,LSL #3]

0x50b318 ADD	X22, X22, #1

0x50b31c CMP	X23, X22

0x50b320 B.NE	50b188

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 256 - 263

--------------------------------------------------------------------------------

256:             for (i = iBegin; i < iEnd; i++)

257:             {

258:                tempx = 0.0;

259:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

260:                {

261:                   tempx += A_data[jj] * x_data[A_j[jj]];

262:                }

263:                y_data[i] = tempx;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.58
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P10,
Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source	csr_matvec.c:256-263
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.17
CQA cycles if no scalar integer	5.17
CQA cycles if FP arith vectorized	8.17
CQA cycles if fully vectorized	2.04
Front-end cycles	7.63
DIV/SQRT cycles	5.00
P0 cycles	5.00
P1 cycles	4.75
P2 cycles	4.75
P3 cycles	4.75
P4 cycles	4.75
P5 cycles	2.25
P6 cycles	2.25
P7 cycles	2.25
P8 cycles	2.25
P9 cycles	8.17
P10 cycles	7.83
P11 cycles	8.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	61.00
Nb uops	61.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	1.71
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	7.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.51
Bytes prefetched	0.00
Bytes loaded	184.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.58
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P10,
Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source	csr_matvec.c:256-263
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.17
CQA cycles if no scalar integer	5.17
CQA cycles if FP arith vectorized	8.17
CQA cycles if fully vectorized	2.04
Front-end cycles	7.63
DIV/SQRT cycles	5.00
P0 cycles	5.00
P1 cycles	4.75
P2 cycles	4.75
P3 cycles	4.75
P4 cycles	4.75
P5 cycles	2.25
P6 cycles	2.25
P7 cycles	2.25
P8 cycles	2.25
P9 cycles	8.17
P10 cycles	7.83
P11 cycles	8.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	61.00
Nb uops	61.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	1.71
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	7.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.51
Bytes prefetched	0.00
Bytes loaded	184.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source file and lines	csr_matvec.c:256-263
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:256-263.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=16
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 16 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.17 to 5.17 cycles (1.58x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 8.17 to 2.04 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 7 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 14 FP arithmetical operations:

7: addition or subtraction (all inside FMA instructions)
7: multiply (all inside FMA instructions)

The binary loop is loading 184 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.07 FP operations per loaded or stored byte.

General properties

nb instructions	61
loop length	244
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	4.75	4.75	4.75	4.75	2.25	2.25	2.25	2.25	8.17	7.83	8.00	0.00	0.00
cycles	5.00	5.00	4.75	4.75	4.75	4.75	2.25	2.25	2.25	2.25	8.17	7.83	8.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.63
Overall L1	8.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.17 cycles. At this rate:

23% of peak load performance is reached (22.53 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (0.98 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 50b188

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR X1, [X24, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR X16, [X26, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X16, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 50b314 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x414>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X2, X16, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ANDS X10, X2, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50b26c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x36c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50b250 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x350>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50b23c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x33c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50b228 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X10, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50b214 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x314>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X10, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50b200 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x300>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X10, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50b1ec <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D16, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D17, [X19, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D16, D17, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X11, [X20, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D18, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D3, [X19, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D18, D3, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X17, [X20, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D19, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D20, [X19, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D19, D20, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X0, [X20, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D21, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D4, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D21, D4, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X12, [X20, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D22, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D23, [X19, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D22, D23, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X7, [X20, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D2, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D1, [X19, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D2, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X6, [X20, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D24, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D9, [X19, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D24, D9, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
CMP X16, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50b314 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x414>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR D0, [X25, X22,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X22, X22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X23, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 50b188 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x288>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source file and lines	csr_matvec.c:256-263
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:256-263.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=16
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.17 to 5.17 cycles (1.58x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 8.17 to 2.04 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 7 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 14 FP arithmetical operations:

7: addition or subtraction (all inside FMA instructions)
7: multiply (all inside FMA instructions)

The binary loop is loading 184 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.07 FP operations per loaded or stored byte.

General properties

nb instructions	61
loop length	244
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	4.75	4.75	4.75	4.75	2.25	2.25	2.25	2.25	8.17	7.83	8.00	0.00	0.00
cycles	5.00	5.00	4.75	4.75	4.75	4.75	2.25	2.25	2.25	2.25	8.17	7.83	8.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.63
Overall L1	8.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.17 cycles. At this rate:

23% of peak load performance is reached (22.53 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (0.98 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 50b188

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR X1, [X24, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR X16, [X26, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X16, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 50b314 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x414>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X2, X16, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ANDS X10, X2, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50b26c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x36c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50b250 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x350>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50b23c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x33c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50b228 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X10, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50b214 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x314>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X10, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50b200 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x300>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X10, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50b1ec <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D16, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D17, [X19, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D16, D17, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X11, [X20, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D18, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D3, [X19, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D18, D3, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X17, [X20, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D19, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D20, [X19, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D19, D20, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X0, [X20, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D21, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D4, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D21, D4, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X12, [X20, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D22, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D23, [X19, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D22, D23, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X7, [X20, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D2, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D1, [X19, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D2, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X6, [X20, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D24, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D9, [X19, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D24, D9, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
CMP X16, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50b314 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x414>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR D0, [X25, X22,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X22, X22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X23, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 50b188 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x288>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code