OV - exec - Loop 3707

	Loop Id: 3707	Module: exec	Source: csr_matvec.c:334-341	Coverage: 0.8%

0x50beac LDR	X0, [X24, X22,LSL #3]

0x50beb0 LDR	X17, [X16, X22,LSL #3]

0x50beb4 LDR	D0, [X26, X22,LSL #3]

0x50beb8 CMP	X0, X17

0x50bebc B.GE	50c038

0x50bec0 SUB	X8, X17, X0

0x50bec4 ANDS	X15, X8, #4224

0x50bec8 B.EQ	50bf90

0x50becc CMP	X15, #1

0x50bed0 B.EQ	50bf74

0x50bed4 CMP	X15, #2

0x50bed8 B.EQ	50bf60

0x50bedc CMP	X15, #3

0x50bee0 B.EQ	50bf4c

0x50bee4 CMP	X15, #4

0x50bee8 B.EQ	50bf38

0x50beec CMP	X15, #5

0x50bef0 B.EQ	50bf24

0x50bef4 CMP	X15, #6

0x50bef8 B.EQ	50bf10

0x50befc LDR	X18, [X20, X0,LSL #3]

0x50bf00 LDR	D30, [X21, X0,LSL #3]

0x50bf04 ADD	X0, X0, #1

0x50bf08 LDR	D31, [X19, X18,LSL #3]

0x50bf0c FMADD	D0, D30, D31, D0

0x50bf10 LDR	X30, [X20, X0,LSL #3]

0x50bf14 LDR	D5, [X21, X0,LSL #3]

0x50bf18 ADD	X0, X0, #1

0x50bf1c LDR	D3, [X19, X30,LSL #3]

0x50bf20 FMADD	D0, D5, D3, D0

0x50bf24 LDR	X27, [X20, X0,LSL #3]

0x50bf28 LDR	D6, [X21, X0,LSL #3]

0x50bf2c ADD	X0, X0, #1

0x50bf30 LDR	D7, [X19, X27,LSL #3]

0x50bf34 FMADD	D0, D6, D7, D0

0x50bf38 LDR	X2, [X20, X0,LSL #3]

0x50bf3c LDR	D16, [X21, X0,LSL #3]

0x50bf40 ADD	X0, X0, #1

0x50bf44 LDR	D4, [X19, X2,LSL #3]

0x50bf48 FMADD	D0, D16, D4, D0

0x50bf4c LDR	X10, [X20, X0,LSL #3]

0x50bf50 LDR	D17, [X21, X0,LSL #3]

0x50bf54 ADD	X0, X0, #1

0x50bf58 LDR	D18, [X19, X10,LSL #3]

0x50bf5c FMADD	D0, D17, D18, D0

0x50bf60 LDR	X11, [X20, X0,LSL #3]

0x50bf64 LDR	D2, [X21, X0,LSL #3]

0x50bf68 ADD	X0, X0, #1

0x50bf6c LDR	D1, [X19, X11,LSL #3]

0x50bf70 FMADD	D0, D2, D1, D0

0x50bf74 LDR	X6, [X20, X0,LSL #3]

0x50bf78 LDR	D9, [X21, X0,LSL #3]

0x50bf7c ADD	X0, X0, #1

0x50bf80 LDR	D19, [X19, X6,LSL #3]

0x50bf84 FMADD	D0, D9, D19, D0

0x50bf88 CMP	X0, X17

0x50bf8c B.EQ	50c038

  (3708) 0x50bf90 LDR	X12, [X20, X0,LSL #3]

  (3708) 0x50bf94 ADD	X1, X0, #1

  (3708) 0x50bf98 ADD	X13, X0, #2

  (3708) 0x50bf9c ADD	X7, X0, #3

  (3708) 0x50bfa0 ADD	X14, X0, #4

  (3708) 0x50bfa4 LDR	D20, [X21, X0,LSL #3]

  (3708) 0x50bfa8 ADD	X5, X0, #5

  (3708) 0x50bfac ADD	X4, X0, #6

  (3708) 0x50bfb0 ADD	X3, X0, #7

  (3708) 0x50bfb4 ADD	X0, X0, #8

  (3708) 0x50bfb8 LDR	X9, [X20, X1,LSL #3]

  (3708) 0x50bfbc LDR	D21, [X19, X12,LSL #3]

  (3708) 0x50bfc0 LDR	D22, [X21, X1,LSL #3]

  (3708) 0x50bfc4 LDR	D23, [X19, X9,LSL #3]

  (3708) 0x50bfc8 LDR	X8, [X20, X13,LSL #3]

  (3708) 0x50bfcc FMADD	D24, D20, D21, D0

  (3708) 0x50bfd0 LDR	D25, [X21, X13,LSL #3]

  (3708) 0x50bfd4 LDR	X15, [X20, X7,LSL #3]

  (3708) 0x50bfd8 FMADD	D26, D22, D23, D24

  (3708) 0x50bfdc LDR	D27, [X19, X8,LSL #3]

  (3708) 0x50bfe0 LDR	D28, [X21, X7,LSL #3]

  (3708) 0x50bfe4 LDR	D8, [X19, X15,LSL #3]

  (3708) 0x50bfe8 LDR	X18, [X20, X14,LSL #3]

  (3708) 0x50bfec FMADD	D29, D25, D27, D26

  (3708) 0x50bff0 LDR	D30, [X21, X14,LSL #3]

  (3708) 0x50bff4 LDR	X30, [X20, X5,LSL #3]

  (3708) 0x50bff8 FMADD	D31, D28, D8, D29

  (3708) 0x50bffc LDR	D5, [X19, X18,LSL #3]

  (3708) 0x50c000 LDR	D3, [X21, X5,LSL #3]

  (3708) 0x50c004 LDR	D6, [X19, X30,LSL #3]

  (3708) 0x50c008 LDR	X27, [X20, X4,LSL #3]

  (3708) 0x50c00c FMADD	D7, D30, D5, D31

  (3708) 0x50c010 LDR	D16, [X21, X4,LSL #3]

  (3708) 0x50c014 LDR	X2, [X20, X3,LSL #3]

  (3708) 0x50c018 FMADD	D4, D3, D6, D7

  (3708) 0x50c01c LDR	D17, [X19, X27,LSL #3]

  (3708) 0x50c020 LDR	D18, [X21, X3,LSL #3]

  (3708) 0x50c024 LDR	D2, [X19, X2,LSL #3]

  (3708) 0x50c028 FMADD	D1, D16, D17, D4

  (3708) 0x50c02c FMADD	D0, D18, D2, D1

  (3708) 0x50c030 CMP	X0, X17

  (3708) 0x50c034 B.NE	50bf90

0x50c038 STR	D0, [X25, X22,LSL #3]

0x50c03c ADD	X22, X22, #1

0x50c040 CMP	X23, X22

0x50c044 B.NE	50beac

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 334 - 341

--------------------------------------------------------------------------------

334:             for (i = iBegin; i < iEnd; i++)

335:             {

336:                tempx = b_data[i];

337:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

338:                {

339:                   tempx += A_data[jj] * x_data[A_j[jj]];

340:                }

341:                y_data[i] = tempx;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.55
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P10,
Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source	csr_matvec.c:334-341
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.50
CQA cycles if no scalar integer	5.50
CQA cycles if FP arith vectorized	8.50
CQA cycles if fully vectorized	2.13
Front-end cycles	7.63
DIV/SQRT cycles	5.00
P0 cycles	5.00
P1 cycles	4.75
P2 cycles	4.75
P3 cycles	4.75
P4 cycles	4.75
P5 cycles	2.00
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	8.50
P10 cycles	8.17
P11 cycles	8.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	61.00
Nb uops	61.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	1.65
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	7.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.53
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.55
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P10,
Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source	csr_matvec.c:334-341
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.50
CQA cycles if no scalar integer	5.50
CQA cycles if FP arith vectorized	8.50
CQA cycles if fully vectorized	2.13
Front-end cycles	7.63
DIV/SQRT cycles	5.00
P0 cycles	5.00
P1 cycles	4.75
P2 cycles	4.75
P3 cycles	4.75
P4 cycles	4.75
P5 cycles	2.00
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	8.50
P10 cycles	8.17
P11 cycles	8.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	61.00
Nb uops	61.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	1.65
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	7.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.53
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source file and lines	csr_matvec.c:334-341
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:334-341.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=16
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 16 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.50 to 5.50 cycles (1.55x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 8.50 to 2.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 7 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 14 FP arithmetical operations:

7: addition or subtraction (all inside FMA instructions)
7: multiply (all inside FMA instructions)

The binary loop is loading 192 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.07 FP operations per loaded or stored byte.

General properties

nb instructions	61
loop length	244
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	4.75	4.75	4.75	4.75	2.00	2.00	2.00	2.00	8.50	8.17	8.33	0.00	0.00
cycles	5.00	5.00	4.75	4.75	4.75	4.75	2.00	2.00	2.00	2.00	8.50	8.17	8.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.63
Overall L1	8.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.50 cycles. At this rate:

23% of peak load performance is reached (22.59 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.94 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 50beac

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR X0, [X24, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X17, [X16, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D0, [X26, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
CMP X0, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 50c038 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X8, X17, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ANDS X15, X8, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50bf90 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1090>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50bf74 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1074>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50bf60 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1060>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50bf4c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x104c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50bf38 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1038>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50bf24 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1024>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50bf10 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1010>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D30, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D31, [X19, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D30, D31, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X30, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D5, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D3, [X19, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D5, D3, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X27, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D6, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D7, [X19, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D6, D7, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X2, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D16, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D4, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D16, D4, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X10, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D17, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D18, [X19, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D17, D18, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D2, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D1, [X19, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D2, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X6, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D9, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D19, [X19, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D9, D19, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
CMP X0, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50c038 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR D0, [X25, X22,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X22, X22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X23, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 50beac <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0xfac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source file and lines	csr_matvec.c:334-341
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:334-341.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=16
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.50 to 5.50 cycles (1.55x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 8.50 to 2.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 7 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 14 FP arithmetical operations:

7: addition or subtraction (all inside FMA instructions)
7: multiply (all inside FMA instructions)

The binary loop is loading 192 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.07 FP operations per loaded or stored byte.

General properties

nb instructions	61
loop length	244
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	4.75	4.75	4.75	4.75	2.00	2.00	2.00	2.00	8.50	8.17	8.33	0.00	0.00
cycles	5.00	5.00	4.75	4.75	4.75	4.75	2.00	2.00	2.00	2.00	8.50	8.17	8.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.63
Overall L1	8.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.50 cycles. At this rate:

23% of peak load performance is reached (22.59 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.94 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 50beac

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR X0, [X24, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X17, [X16, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D0, [X26, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
CMP X0, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 50c038 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X8, X17, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ANDS X15, X8, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50bf90 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1090>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50bf74 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1074>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50bf60 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1060>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50bf4c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x104c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50bf38 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1038>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50bf24 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1024>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50bf10 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1010>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D30, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D31, [X19, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D30, D31, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X30, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D5, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D3, [X19, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D5, D3, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X27, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D6, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D7, [X19, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D6, D7, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X2, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D16, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D4, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D16, D4, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X10, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D17, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D18, [X19, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D17, D18, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D2, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D1, [X19, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D2, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X6, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D9, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D19, [X19, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D9, D19, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
CMP X0, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50c038 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR D0, [X25, X22,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X22, X22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X23, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 50beac <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0xfac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code