OV - exec - Loop 3697

	Loop Id: 3697	Module: exec	Source: csr_matvec.c:307-314	Coverage: 1.04%

0x50bd00 LDR	X0, [X24, X22,LSL #3]

0x50bd04 LDR	X17, [X16, X22,LSL #3]

0x50bd08 LDR	D0, [X26, X22,LSL #3]

0x50bd0c CMP	X0, X17

0x50bd10 B.GE	50be8c

0x50bd14 SUB	X13, X17, X0

0x50bd18 ANDS	X14, X13, #4224

0x50bd1c B.EQ	50bde4

0x50bd20 CMP	X14, #1

0x50bd24 B.EQ	50bdc8

0x50bd28 CMP	X14, #2

0x50bd2c B.EQ	50bdb4

0x50bd30 CMP	X14, #3

0x50bd34 B.EQ	50bda0

0x50bd38 CMP	X14, #4

0x50bd3c B.EQ	50bd8c

0x50bd40 CMP	X14, #5

0x50bd44 B.EQ	50bd78

0x50bd48 CMP	X14, #6

0x50bd4c B.EQ	50bd64

0x50bd50 LDR	X5, [X20, X0,LSL #3]

0x50bd54 LDR	D9, [X21, X0,LSL #3]

0x50bd58 ADD	X0, X0, #1

0x50bd5c LDR	D6, [X19, X5,LSL #3]

0x50bd60 FMSUB	D0, D9, D6, D0

0x50bd64 LDR	X15, [X20, X0,LSL #3]

0x50bd68 LDR	D3, [X21, X0,LSL #3]

0x50bd6c ADD	X0, X0, #1

0x50bd70 LDR	D7, [X19, X15,LSL #3]

0x50bd74 FMSUB	D0, D3, D7, D0

0x50bd78 LDR	X18, [X20, X0,LSL #3]

0x50bd7c LDR	D16, [X21, X0,LSL #3]

0x50bd80 ADD	X0, X0, #1

0x50bd84 LDR	D17, [X19, X18,LSL #3]

0x50bd88 FMSUB	D0, D16, D17, D0

0x50bd8c LDR	X30, [X20, X0,LSL #3]

0x50bd90 LDR	D4, [X21, X0,LSL #3]

0x50bd94 ADD	X0, X0, #1

0x50bd98 LDR	D18, [X19, X30,LSL #3]

0x50bd9c FMSUB	D0, D4, D18, D0

0x50bda0 LDR	X8, [X20, X0,LSL #3]

0x50bda4 LDR	D19, [X21, X0,LSL #3]

0x50bda8 ADD	X0, X0, #1

0x50bdac LDR	D2, [X19, X8,LSL #3]

0x50bdb0 FMSUB	D0, D19, D2, D0

0x50bdb4 LDR	X27, [X20, X0,LSL #3]

0x50bdb8 LDR	D20, [X21, X0,LSL #3]

0x50bdbc ADD	X0, X0, #1

0x50bdc0 LDR	D1, [X19, X27,LSL #3]

0x50bdc4 FMSUB	D0, D20, D1, D0

0x50bdc8 LDR	X2, [X20, X0,LSL #3]

0x50bdcc LDR	D21, [X21, X0,LSL #3]

0x50bdd0 ADD	X0, X0, #1

0x50bdd4 LDR	D22, [X19, X2,LSL #3]

0x50bdd8 FMSUB	D0, D21, D22, D0

0x50bddc CMP	X0, X17

0x50bde0 B.EQ	50be8c

  (3698) 0x50bde4 LDR	X10, [X20, X0,LSL #3]

  (3698) 0x50bde8 ADD	X11, X0, #1

  (3698) 0x50bdec ADD	X7, X0, #2

  (3698) 0x50bdf0 ADD	X12, X0, #3

  (3698) 0x50bdf4 ADD	X6, X0, #4

  (3698) 0x50bdf8 LDR	D23, [X21, X0,LSL #3]

  (3698) 0x50bdfc ADD	X13, X0, #5

  (3698) 0x50be00 ADD	X4, X0, #6

  (3698) 0x50be04 ADD	X3, X0, #7

  (3698) 0x50be08 ADD	X0, X0, #8

  (3698) 0x50be0c LDR	X9, [X20, X11,LSL #3]

  (3698) 0x50be10 LDR	D24, [X19, X10,LSL #3]

  (3698) 0x50be14 LDR	D25, [X21, X11,LSL #3]

  (3698) 0x50be18 LDR	D26, [X19, X9,LSL #3]

  (3698) 0x50be1c LDR	X14, [X20, X7,LSL #3]

  (3698) 0x50be20 FMSUB	D27, D23, D24, D0

  (3698) 0x50be24 LDR	D28, [X21, X7,LSL #3]

  (3698) 0x50be28 LDR	X1, [X20, X12,LSL #3]

  (3698) 0x50be2c FMSUB	D8, D25, D26, D27

  (3698) 0x50be30 LDR	D29, [X19, X14,LSL #3]

  (3698) 0x50be34 LDR	D30, [X21, X12,LSL #3]

  (3698) 0x50be38 LDR	D31, [X19, X1,LSL #3]

  (3698) 0x50be3c LDR	X5, [X20, X6,LSL #3]

  (3698) 0x50be40 FMSUB	D5, D28, D29, D8

  (3698) 0x50be44 LDR	D9, [X21, X6,LSL #3]

  (3698) 0x50be48 LDR	X15, [X20, X13,LSL #3]

  (3698) 0x50be4c FMSUB	D6, D30, D31, D5

  (3698) 0x50be50 LDR	D3, [X19, X5,LSL #3]

  (3698) 0x50be54 LDR	D7, [X21, X13,LSL #3]

  (3698) 0x50be58 LDR	D16, [X19, X15,LSL #3]

  (3698) 0x50be5c LDR	X18, [X20, X4,LSL #3]

  (3698) 0x50be60 FMSUB	D17, D9, D3, D6

  (3698) 0x50be64 LDR	D4, [X21, X4,LSL #3]

  (3698) 0x50be68 LDR	X30, [X20, X3,LSL #3]

  (3698) 0x50be6c FMSUB	D18, D7, D16, D17

  (3698) 0x50be70 LDR	D19, [X19, X18,LSL #3]

  (3698) 0x50be74 LDR	D2, [X21, X3,LSL #3]

  (3698) 0x50be78 LDR	D20, [X19, X30,LSL #3]

  (3698) 0x50be7c FMSUB	D1, D4, D19, D18

  (3698) 0x50be80 FMSUB	D0, D2, D20, D1

  (3698) 0x50be84 CMP	X0, X17

  (3698) 0x50be88 B.NE	50bde4

0x50be8c STR	D0, [X25, X22,LSL #3]

0x50be90 ADD	X22, X22, #1

0x50be94 CMP	X23, X22

0x50be98 B.NE	50bd00

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 307 - 314

--------------------------------------------------------------------------------

307:             for (i = iBegin; i < iEnd; i++)

308:             {

309:                tempx = b_data[i];

310:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

311:                {

312:                   tempx -= A_data[jj] * x_data[A_j[jj]];

313:                }

314:                y_data[i] = tempx;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.55
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P10,
Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source	csr_matvec.c:307-314
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.50
CQA cycles if no scalar integer	5.50
CQA cycles if FP arith vectorized	8.50
CQA cycles if fully vectorized	2.13
Front-end cycles	7.63
DIV/SQRT cycles	5.00
P0 cycles	5.00
P1 cycles	4.75
P2 cycles	4.75
P3 cycles	4.75
P4 cycles	4.75
P5 cycles	2.00
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	8.50
P10 cycles	8.17
P11 cycles	8.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	61.00
Nb uops	61.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	1.65
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	7.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.53
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.55
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P10,
Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source	csr_matvec.c:307-314
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.50
CQA cycles if no scalar integer	5.50
CQA cycles if FP arith vectorized	8.50
CQA cycles if fully vectorized	2.13
Front-end cycles	7.63
DIV/SQRT cycles	5.00
P0 cycles	5.00
P1 cycles	4.75
P2 cycles	4.75
P3 cycles	4.75
P4 cycles	4.75
P5 cycles	2.00
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	8.50
P10 cycles	8.17
P11 cycles	8.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	61.00
Nb uops	61.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	1.65
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	7.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.53
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source file and lines	csr_matvec.c:307-314
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:307-314.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=16
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 16 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.50 to 5.50 cycles (1.55x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 8.50 to 2.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 7 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 14 FP arithmetical operations:

7: addition or subtraction (all inside FMA instructions)
7: multiply (all inside FMA instructions)

The binary loop is loading 192 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.07 FP operations per loaded or stored byte.

General properties

nb instructions	61
loop length	244
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	4.75	4.75	4.75	4.75	2.00	2.00	2.00	2.00	8.50	8.17	8.33	0.00	0.00
cycles	5.00	5.00	4.75	4.75	4.75	4.75	2.00	2.00	2.00	2.00	8.50	8.17	8.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.63
Overall L1	8.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.50 cycles. At this rate:

23% of peak load performance is reached (22.59 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.94 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 50bd00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR X0, [X24, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X17, [X16, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D0, [X26, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
CMP X0, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 50be8c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0xf8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X13, X17, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ANDS X14, X13, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50bde4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0xee4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50bdc8 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0xec8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50bdb4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0xeb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50bda0 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0xea0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50bd8c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0xe8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50bd78 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0xe78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50bd64 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0xe64>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X5, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D9, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D6, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D9, D6, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X15, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D3, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D7, [X19, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D3, D7, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X18, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D16, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D17, [X19, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D16, D17, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X30, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D4, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D18, [X19, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D4, D18, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D19, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D2, [X19, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D19, D2, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X27, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D20, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D1, [X19, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D20, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X2, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D21, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D22, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D21, D22, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
CMP X0, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50be8c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0xf8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR D0, [X25, X22,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X22, X22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X23, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 50bd00 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0xe00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source file and lines	csr_matvec.c:307-314
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:307-314.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=16
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.50 to 5.50 cycles (1.55x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 8.50 to 2.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 7 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 14 FP arithmetical operations:

7: addition or subtraction (all inside FMA instructions)
7: multiply (all inside FMA instructions)

The binary loop is loading 192 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.07 FP operations per loaded or stored byte.

General properties

nb instructions	61
loop length	244
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	4.75	4.75	4.75	4.75	2.00	2.00	2.00	2.00	8.50	8.17	8.33	0.00	0.00
cycles	5.00	5.00	4.75	4.75	4.75	4.75	2.00	2.00	2.00	2.00	8.50	8.17	8.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.63
Overall L1	8.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.50 cycles. At this rate:

23% of peak load performance is reached (22.59 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.94 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 50bd00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR X0, [X24, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X17, [X16, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D0, [X26, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
CMP X0, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 50be8c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0xf8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X13, X17, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ANDS X14, X13, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50bde4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0xee4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50bdc8 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0xec8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50bdb4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0xeb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50bda0 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0xea0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50bd8c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0xe8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50bd78 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0xe78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50bd64 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0xe64>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X5, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D9, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D6, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D9, D6, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X15, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D3, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D7, [X19, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D3, D7, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X18, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D16, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D17, [X19, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D16, D17, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X30, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D4, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D18, [X19, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D4, D18, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D19, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D2, [X19, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D19, D2, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X27, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D20, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D1, [X19, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D20, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X2, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D21, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D22, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D21, D22, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
CMP X0, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 50be8c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0xf8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR D0, [X25, X22,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X22, X22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X23, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 50bd00 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0xe00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code