OV - exec - Loop 3581

0x5057e0 LDR	X22, [X28, X14,LSL #3]

0x5057e4 LDR	D2, [X5, X14,LSL #3]

0x5057e8 UBFM	X10, X22, #61, #60

0x5057ec LDR	X2, [X27, X22,LSL #3]

0x5057f0 ADD	X30, X10, #8

0x5057f4 LDR	X7, [X27, X30]

0x5057f8 ADD	X17, X27, X30

0x5057fc CMP	X2, X7

0x505800 B.GE	505844

  (3582) 0x505804 LDR	X1, [X20, X2,LSL #3]

  (3582) 0x505808 LDR	D0, [X26, X2,LSL #3]

  (3582) 0x50580c LDR	X12, [X19, X1,LSL #3]

  (3582) 0x505810 FMUL	D3, D2, D0

  (3582) 0x505814 CMP	X12, X13

  (3582) 0x505818 B.GE	505874

  (3582) 0x50581c STR	X21, [X19, X1,LSL #3]

  (3582) 0x505820 ADD	X2, X2, #1

  (3582) 0x505824 STR	X1, [X0, X21,LSL #3]

  (3582) 0x505828 ADD	X21, X21, #1

  (3582) 0x50582c LDR	X6, [X19, X1,LSL #3]

  (3582) 0x505830 LDR	X7, [X17]

  (3582) 0x505834 STR	D3, [X4, X6,LSL #3]

  (3582) 0x505838 CMP	X7, X2

  (3582) 0x50583c B.GT	505804

0x505840 LDR	X16, [X15, X8,LSL #3]

0x505844 ADD	X14, X14, #1

0x505848 CMP	X14, X16

0x50584c B.LT	5057e0

  (3582) 0x505874 LDR	D1, [X4, X12,LSL #3]

  (3582) 0x505878 ADD	X2, X2, #1

  (3582) 0x50587c FADD	D4, D1, D3

  (3582) 0x505880 STR	D4, [X4, X12,LSL #3]

  (3582) 0x505884 CMP	X7, X2

  (3582) 0x505888 B.GT	505804

0x50588c B	505840

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c: 282 - 298

--------------------------------------------------------------------------------

282:       for (ia = A_i[ic]; ia < A_i[ic+1]; ia++)

283:       {

284: 	 ja = A_j[ia];

285: 	 a_entry = A_data[ia];

286: 	 for (ib = B_i[ja]; ib < B_i[ja+1]; ib++)

287: 	 {

288: 	    jb = B_j[ib];

289: 	    b_entry = B_data[ib];

290: 	    if (B_marker[jb] < row_start)

291: 	    {

292: 		B_marker[jb] = counter;

293: 		C_j[B_marker[jb]] = jb;

294: 		C_data[B_marker[jb]] = a_entry*b_entry;

295: 		counter++;

296: 	    }

297: 	    else

298: 		C_data[B_marker[jb]] += a_entry*b_entry;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.64
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks
Function	hypre_CSRMatrixMultiply._omp_fn.0
Source	csr_matop.c:282-282,csr_matop.c:285-286
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.64
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	1.64
CQA cycles if fully vectorized	0.41
Front-end cycles	1.63
DIV/SQRT cycles	1.17
P0 cycles	1.17
P1 cycles	1.50
P2 cycles	1.50
P3 cycles	1.50
P4 cycles	1.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.56
P10 cycles	1.56
P11 cycles	1.56
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	13.00
Nb uops	13.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.73
Bytes prefetched	0.00
Bytes loaded	37.33
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.50
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	micro-operation queue, P2, P3, P4, P5,
Function	hypre_CSRMatrixMultiply._omp_fn.0
Source	csr_matop.c:282-282,csr_matop.c:285-286
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.50
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	1.50
CQA cycles if fully vectorized	0.38
Front-end cycles	1.50
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	1.50
P2 cycles	1.50
P3 cycles	1.50
P4 cycles	1.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.33
P10 cycles	1.33
P11 cycles	1.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	12.00
Nb uops	12.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.33
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.67
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	P10, P11, P12,
Function	hypre_CSRMatrixMultiply._omp_fn.0
Source	csr_matop.c:282-282,csr_matop.c:285-286
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.67
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	1.67
CQA cycles if fully vectorized	0.42
Front-end cycles	1.63
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	1.50
P2 cycles	1.50
P3 cycles	1.50
P4 cycles	1.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.67
P10 cycles	1.67
P11 cycles	1.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	13.00
Nb uops	13.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.75
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	micro-operation queue,
Function	hypre_CSRMatrixMultiply._omp_fn.0
Source	csr_matop.c:282-282,csr_matop.c:285-286
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.75
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	1.75
CQA cycles if fully vectorized	0.44
Front-end cycles	1.75
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	1.50
P2 cycles	1.50
P3 cycles	1.50
P4 cycles	1.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.67
P10 cycles	1.67
P11 cycles	1.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	14.00
Nb uops	14.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.86
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_CSRMatrixMultiply._omp_fn.0
Source file and lines	csr_matop.c:282-298
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:282-298.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:282,285-286.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.64 to 0.41 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 37 bytes.

General properties

nb instructions	13
loop length	52
nb stack references	0

Front-end

front end

1.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.17	1.17	1.50	1.50	1.50	1.50	0.00	0.00	0.00	0.00	1.56	1.56	1.56	0.00	0.00
cycles	1.17	1.17	1.50	1.50	1.50	1.50	0.00	0.00	0.00	0.00	1.56	1.56	1.56	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.63
Data deps.	1.00
Overall L1	1.64

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.64 cycles. At this rate:

23% of peak load performance is reached (22.73 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Function	hypre_CSRMatrixMultiply._omp_fn.0
Source file and lines	csr_matop.c:282-298
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:282-298.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:282,285-286.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 1.50 to 1.00 cycles (1.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.50 to 0.37 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes.

General properties

nb instructions	12
loop length	48
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	1.50	1.50	1.50	1.50	0.00	0.00	0.00	0.00	1.33	1.33	1.33	0.00	0.00
cycles	1.00	1.00	1.50	1.50	1.50	1.50	0.00	0.00	0.00	0.00	1.33	1.33	1.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.50
Data deps.	1.00
Overall L1	1.50

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.50 cycles. At this rate:

22% of peak load performance is reached (21.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 5057e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDR X22, [X28, X14,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D2, [X5, X14,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
UBFM X10, X22, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X2, [X27, X22,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X30, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X7, [X27, X30]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X17, X27, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X2, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 505844 <hypre_CSRMatrixMultiply._omp_fn.0+0x484>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X14, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LT 5057e0 <hypre_CSRMatrixMultiply._omp_fn.0+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	hypre_CSRMatrixMultiply._omp_fn.0
Source file and lines	csr_matop.c:282-298
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:282-298.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:282,285-286.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 1.67 to 1.00 cycles (1.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.67 to 0.42 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 40 bytes.

General properties

nb instructions	13
loop length	52
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	1.50	1.50	1.50	1.50	0.00	0.00	0.00	0.00	1.67	1.67	1.67	0.00	0.00
cycles	1.00	1.00	1.50	1.50	1.50	1.50	0.00	0.00	0.00	0.00	1.67	1.67	1.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.63
Data deps.	1.00
Overall L1	1.67

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.67 cycles. At this rate:

25% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 5057e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDR X22, [X28, X14,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D2, [X5, X14,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
UBFM X10, X22, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X2, [X27, X22,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X30, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X7, [X27, X30]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X17, X27, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X2, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 505844 <hypre_CSRMatrixMultiply._omp_fn.0+0x484>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X16, [X15, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X14, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LT 5057e0 <hypre_CSRMatrixMultiply._omp_fn.0+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	hypre_CSRMatrixMultiply._omp_fn.0
Source file and lines	csr_matop.c:282-298
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:282-298.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:282,285-286.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 1.75 to 1.00 cycles (1.75x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.75 to 0.44 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 40 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	1.50	1.50	1.50	1.50	0.00	0.00	0.00	0.00	1.67	1.67	1.67	0.00	0.00
cycles	1.50	1.50	1.50	1.50	1.50	1.50	0.00	0.00	0.00	0.00	1.67	1.67	1.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.75
Data deps.	1.00
Overall L1	1.75

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.75 cycles. At this rate:

23% of peak load performance is reached (22.86 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 5057e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDR X22, [X28, X14,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D2, [X5, X14,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
UBFM X10, X22, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X2, [X27, X22,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X30, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X7, [X27, X30]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X17, X27, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X2, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 505844 <hypre_CSRMatrixMultiply._omp_fn.0+0x484>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X16, [X15, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X14, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LT 5057e0 <hypre_CSRMatrixMultiply._omp_fn.0+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
B 505840 <hypre_CSRMatrixMultiply._omp_fn.0+0x480>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code