OV - exec - Loop 3438

0x4f9364 LDR	X18, [X20, X3,LSL #3]    [11]

0x4f9368 ADD	X30, X3, #1

0x4f936c ADD	X16, X3, #2

0x4f9370 ADD	X19, X3, #3

0x4f9374 ADD	X2, X3, #4

0x4f9378 ADD	X7, X3, #5

0x4f937c ADD	X6, X3, #6

0x4f9380 ADD	X5, X3, #7

0x4f9384 ADD	X4, X17, X18

0x4f9388 STR	X4, [X13, X3,LSL #3]    [4]

0x4f938c ADD	X3, X3, #8

0x4f9390 LDR	X1, [X20, X30,LSL #3]    [2]

0x4f9394 ADD	X11, X4, X1

0x4f9398 STR	X11, [X13, X30,LSL #3]    [6]

0x4f939c LDR	X8, [X20, X16,LSL #3]    [5]

0x4f93a0 ADD	X9, X11, X8

0x4f93a4 STR	X9, [X13, X16,LSL #3]    [13]

0x4f93a8 LDR	X10, [X20, X19,LSL #3]    [9]

0x4f93ac ADD	X12, X9, X10

0x4f93b0 STR	X12, [X13, X19,LSL #3]    [15]

0x4f93b4 LDR	X14, [X20, X2,LSL #3]    [12]

0x4f93b8 ADD	X15, X12, X14

0x4f93bc STR	X15, [X13, X2,LSL #3]    [3]

0x4f93c0 LDR	X17, [X20, X7,LSL #3]    [1]

0x4f93c4 ADD	X18, X15, X17

0x4f93c8 STR	X18, [X13, X7,LSL #3]    [10]

0x4f93cc LDR	X30, [X20, X6,LSL #3]    [16]

0x4f93d0 ADD	X19, X18, X30

0x4f93d4 STR	X19, [X13, X6,LSL #3]    [8]

0x4f93d8 LDR	X16, [X20, X5,LSL #3]    [14]

0x4f93dc ADD	X17, X19, X16

0x4f93e0 STR	X17, [X13, X5,LSL #3]    [7]

0x4f93e4 CMP	X21, X3

0x4f93e8 B.GT	4f9364

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 207 - 208

--------------------------------------------------------------------------------

207:    for (i = 0; i < local_num_rows; i++)

208:       offd_i[i+1] = offd_i[i] + offdiag_sizes[i];

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks
Function	hypre_IJMatrixSetDiagOffdSizesParCSR
Source	IJMatrix_parcsr.c:207-208
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	2.00
Front-end cycles	4.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	4.25
P2 cycles	4.25
P3 cycles	4.25
P4 cycles	4.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	5.33
P10 cycles	5.33
P11 cycles	5.33
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	34.00
Nb uops	34.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks
Function	hypre_IJMatrixSetDiagOffdSizesParCSR
Source	IJMatrix_parcsr.c:207-208
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	2.00
Front-end cycles	4.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	4.25
P2 cycles	4.25
P3 cycles	4.25
P4 cycles	4.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	5.33
P10 cycles	5.33
P11 cycles	5.33
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	34.00
Nb uops	34.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_IJMatrixSetDiagOffdSizesParCSR
Source file and lines	IJMatrix_parcsr.c:207-208
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:207-208.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 8.00 to 2.00 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	34
loop length	136
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	4.25	4.25	4.25	4.25	0.00	0.00	0.00	0.00	5.33	5.33	5.33	4.00	4.00
cycles	0.50	0.50	4.25	4.25	4.25	4.25	0.00	0.00	0.00	0.00	5.33	5.33	5.33	4.00	4.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	4.25
Data deps.	8.00
Overall L1	8.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (8.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4f9364

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X18, [X20, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X30, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X16, X3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X19, X3, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X2, X3, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X7, X3, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X6, X3, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X5, X3, #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X17, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X4, [X13, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X1, [X20, X30,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X4, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X13, X30,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X20, X16,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X11, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X9, [X13, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X20, X19,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X12, [X13, X19,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X20, X2,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X15, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X17, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X15, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X18, [X13, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X30, [X20, X6,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X19, X18, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X19, [X13, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X20, X5,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X17, X19, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X17, [X13, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X21, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 4f9364 <hypre_IJMatrixSetDiagOffdSizesParCSR+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_IJMatrixSetDiagOffdSizesParCSR
Source file and lines	IJMatrix_parcsr.c:207-208
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:207-208.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 8.00 to 2.00 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	34
loop length	136
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	4.25	4.25	4.25	4.25	0.00	0.00	0.00	0.00	5.33	5.33	5.33	4.00	4.00
cycles	0.50	0.50	4.25	4.25	4.25	4.25	0.00	0.00	0.00	0.00	5.33	5.33	5.33	4.00	4.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	4.25
Data deps.	8.00
Overall L1	8.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (8.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4f9364

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X18, [X20, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X30, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X16, X3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X19, X3, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X2, X3, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X7, X3, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X6, X3, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X5, X3, #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X17, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X4, [X13, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X1, [X20, X30,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X4, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X13, X30,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X20, X16,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X11, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X9, [X13, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X20, X19,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X12, [X13, X19,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X20, X2,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X15, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X17, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X15, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X18, [X13, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X30, [X20, X6,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X19, X18, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X19, [X13, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X20, X5,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X17, X19, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X17, [X13, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X21, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 4f9364 <hypre_IJMatrixSetDiagOffdSizesParCSR+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code