OV - exec - Loop 3436

  (3437) 0x4f918c LDR	X7, [X19, X16,LSL #3]

  (3437) 0x4f9190 ADD	X15, X15, X7

  (3437) 0x4f9194 STR	X15, [X13, X16,LSL #3]

  (3437) 0x4f9198 ADD	X16, X16, #1

  (3437) 0x4f919c LDR	X8, [X19, X16,LSL #3]

  (3437) 0x4f91a0 ADD	X15, X15, X8

  (3437) 0x4f91a4 STR	X15, [X13, X16,LSL #3]

  (3437) 0x4f91a8 ADD	X16, X16, #1

  (3437) 0x4f91ac LDR	X9, [X19, X16,LSL #3]

  (3437) 0x4f91b0 ADD	X15, X15, X9

  (3437) 0x4f91b4 STR	X15, [X13, X16,LSL #3]

  (3437) 0x4f91b8 ADD	X16, X16, #1

  (3437) 0x4f91bc LDR	X10, [X19, X16,LSL #3]

  (3437) 0x4f91c0 ADD	X15, X15, X10

  (3437) 0x4f91c4 STR	X15, [X13, X16,LSL #3]

  (3437) 0x4f91c8 ADD	X16, X16, #1

  (3437) 0x4f91cc LDR	X12, [X19, X16,LSL #3]

  (3437) 0x4f91d0 ADD	X15, X15, X12

  (3437) 0x4f91d4 STR	X15, [X13, X16,LSL #3]

  (3437) 0x4f91d8 ADD	X16, X16, #1

  (3437) 0x4f91dc LDR	X14, [X19, X16,LSL #3]

  (3437) 0x4f91e0 ADD	X15, X15, X14

  (3437) 0x4f91e4 STR	X15, [X13, X16,LSL #3]

  (3437) 0x4f91e8 ADD	X16, X16, #1

  (3437) 0x4f91ec CMP	X21, X16

  (3437) 0x4f91f0 B.EQ	4f927c

0x4f91f4 LDR	X17, [X19, X16,LSL #3]

0x4f91f8 ADD	X18, X16, #1

0x4f91fc ADD	X4, X16, #2

0x4f9200 ADD	X30, X16, #3

0x4f9204 ADD	X1, X16, #4

0x4f9208 ADD	X7, X16, #5

0x4f920c ADD	X6, X16, #6

0x4f9210 ADD	X5, X16, #7

0x4f9214 ADD	X3, X15, X17

0x4f9218 STR	X3, [X13, X16,LSL #3]

0x4f921c ADD	X16, X16, #8

0x4f9220 LDR	X2, [X19, X18,LSL #3]

0x4f9224 ADD	X8, X3, X2

0x4f9228 STR	X8, [X13, X18,LSL #3]

0x4f922c LDR	X9, [X19, X4,LSL #3]

0x4f9230 ADD	X10, X8, X9

0x4f9234 STR	X10, [X13, X4,LSL #3]

0x4f9238 LDR	X12, [X19, X30,LSL #3]

0x4f923c ADD	X14, X10, X12

0x4f9240 STR	X14, [X13, X30,LSL #3]

0x4f9244 LDR	X15, [X19, X1,LSL #3]

0x4f9248 ADD	X17, X14, X15

0x4f924c STR	X17, [X13, X1,LSL #3]

0x4f9250 LDR	X18, [X19, X7,LSL #3]

0x4f9254 ADD	X30, X17, X18

0x4f9258 STR	X30, [X13, X7,LSL #3]

0x4f925c LDR	X4, [X19, X6,LSL #3]

0x4f9260 ADD	X1, X30, X4

0x4f9264 STR	X1, [X13, X6,LSL #3]

0x4f9268 LDR	X7, [X19, X5,LSL #3]

0x4f926c ADD	X15, X1, X7

0x4f9270 STR	X15, [X13, X5,LSL #3]

0x4f9274 CMP	X21, X16

0x4f9278 B.NE	4f91f4

  (3437) 0x4f927c LDR	X19, [X11]

  (3437) 0x4f9280 STR	X0, [X23]

  (3437) 0x4f9284 LDR	X0, [X24]

  (3437) 0x4f9288 STR	X19, [X23, #32]

  (3437) 0x4f928c CBZ	X0, 4f94c0

  (3437) 0x4f9290 LDR	X6, [X0]

  (3437) 0x4f9294 ORR	X13, XZR, X0

  (3437) 0x4f9298 SUB	X11, X21, #1

  (3437) 0x4f929c MOVZ	X3, #1

  (3437) 0x4f92a0 AND	X16, X11, #4224

  (3437) 0x4f92a4 LDR	X5, [X20]

  (3437) 0x4f92a8 ADD	X17, X6, X5

  (3437) 0x4f92ac STR	X17, [X13, #8]!

  (3437) 0x4f92b0 CMP	X21, X3

  (3437) 0x4f92b4 B.LE	4f93ec

  (3437) 0x4f92b8 CBZ	X16, 4f9364

  (3437) 0x4f92bc CMP	X16, #1

  (3437) 0x4f92c0 B.EQ	4f934c

  (3437) 0x4f92c4 CMP	X16, #2

  (3437) 0x4f92c8 B.EQ	4f933c

  (3437) 0x4f92cc CMP	X16, #3

  (3437) 0x4f92d0 B.EQ	4f932c

  (3437) 0x4f92d4 CMP	X16, #4

  (3437) 0x4f92d8 B.EQ	4f931c

  (3437) 0x4f92dc CMP	X16, #5

  (3437) 0x4f92e0 B.EQ	4f930c

  (3437) 0x4f92e4 CMP	X16, #6

  (3437) 0x4f92e8 B.EQ	4f92fc

  (3437) 0x4f92ec LDR	X2, [X20, #8]

  (3437) 0x4f92f0 MOVZ	X3, #2

  (3437) 0x4f92f4 ADD	X17, X17, X2

  (3437) 0x4f92f8 STR	X17, [X13, #8]

  (3437) 0x4f92fc LDR	X8, [X20, X3,LSL #3]

  (3437) 0x4f9300 ADD	X17, X17, X8

  (3437) 0x4f9304 STR	X17, [X13, X3,LSL #3]

  (3437) 0x4f9308 ADD	X3, X3, #1

  (3437) 0x4f930c LDR	X9, [X20, X3,LSL #3]

  (3437) 0x4f9310 ADD	X17, X17, X9

  (3437) 0x4f9314 STR	X17, [X13, X3,LSL #3]

  (3437) 0x4f9318 ADD	X3, X3, #1

  (3437) 0x4f931c LDR	X10, [X20, X3,LSL #3]

  (3437) 0x4f9320 ADD	X17, X17, X10

  (3437) 0x4f9324 STR	X17, [X13, X3,LSL #3]

  (3437) 0x4f9328 ADD	X3, X3, #1

  (3437) 0x4f932c LDR	X12, [X20, X3,LSL #3]

  (3437) 0x4f9330 ADD	X17, X17, X12

  (3437) 0x4f9334 STR	X17, [X13, X3,LSL #3]

  (3437) 0x4f9338 ADD	X3, X3, #1

  (3437) 0x4f933c LDR	X14, [X20, X3,LSL #3]

  (3437) 0x4f9340 ADD	X17, X17, X14

  (3437) 0x4f9344 STR	X17, [X13, X3,LSL #3]

  (3437) 0x4f9348 ADD	X3, X3, #1

  (3437) 0x4f934c LDR	X15, [X20, X3,LSL #3]

  (3437) 0x4f9350 ADD	X17, X17, X15

  (3437) 0x4f9354 STR	X17, [X13, X3,LSL #3]

  (3437) 0x4f9358 ADD	X3, X3, #1

  (3437) 0x4f935c CMP	X21, X3

  (3437) 0x4f9360 B.LE	4f93ec

    (3438) 0x4f9364 LDR	X18, [X20, X3,LSL #3]

    (3438) 0x4f9368 ADD	X30, X3, #1

    (3438) 0x4f936c ADD	X16, X3, #2

    (3438) 0x4f9370 ADD	X19, X3, #3

    (3438) 0x4f9374 ADD	X2, X3, #4

    (3438) 0x4f9378 ADD	X7, X3, #5

    (3438) 0x4f937c ADD	X6, X3, #6

    (3438) 0x4f9380 ADD	X5, X3, #7

    (3438) 0x4f9384 ADD	X4, X17, X18

    (3438) 0x4f9388 STR	X4, [X13, X3,LSL #3]

    (3438) 0x4f938c ADD	X3, X3, #8

    (3438) 0x4f9390 LDR	X1, [X20, X30,LSL #3]

    (3438) 0x4f9394 ADD	X11, X4, X1

    (3438) 0x4f9398 STR	X11, [X13, X30,LSL #3]

    (3438) 0x4f939c LDR	X8, [X20, X16,LSL #3]

    (3438) 0x4f93a0 ADD	X9, X11, X8

    (3438) 0x4f93a4 STR	X9, [X13, X16,LSL #3]

    (3438) 0x4f93a8 LDR	X10, [X20, X19,LSL #3]

    (3438) 0x4f93ac ADD	X12, X9, X10

    (3438) 0x4f93b0 STR	X12, [X13, X19,LSL #3]

    (3438) 0x4f93b4 LDR	X14, [X20, X2,LSL #3]

    (3438) 0x4f93b8 ADD	X15, X12, X14

    (3438) 0x4f93bc STR	X15, [X13, X2,LSL #3]

    (3438) 0x4f93c0 LDR	X17, [X20, X7,LSL #3]

    (3438) 0x4f93c4 ADD	X18, X15, X17

    (3438) 0x4f93c8 STR	X18, [X13, X7,LSL #3]

    (3438) 0x4f93cc LDR	X30, [X20, X6,LSL #3]

    (3438) 0x4f93d0 ADD	X19, X18, X30

    (3438) 0x4f93d4 STR	X19, [X13, X6,LSL #3]

    (3438) 0x4f93d8 LDR	X16, [X20, X5,LSL #3]

    (3438) 0x4f93dc ADD	X17, X19, X16

    (3438) 0x4f93e0 STR	X17, [X13, X5,LSL #3]

    (3438) 0x4f93e4 CMP	X21, X3

    (3438) 0x4f93e8 B.GT	4f9364

  (3437) 0x4f93ec LDR	X20, [X0, X21,LSL #3]

  (3437) 0x4f93f0 LDR	X13, [SP, #64]

  (3437) 0x4f93f4 STR	X0, [X24]

  (3437) 0x4f93f8 STR	X20, [X24, #32]

  (3437) 0x4f93fc CBZ	X13, 4f9494

  (3437) 0x4f9400 ADRP	X3,

  (3437) 0x4f9404 ADRP	X0,

  (3437) 0x4f9408 STR	XZR, [X13, #16]

  (3437) 0x4f940c LDR	X21, [X3, #3848]

  (3437) 0x4f9410 LDR	X22, [X0, #4048]

  (3437) 0x4f9414 LDR	X3, [SP, #72]

  (3437) 0x4f9418 LDR	X2, [X21]

  (3437) 0x4f941c SUBS	X3, X3, X2

  (3437) 0x4f9420 MOVZ	X2, #0

  (3437) 0x4f9424 LDR	X0, [X22]

  (3437) 0x4f9428 B.NE	4f94d0

  (3437) 0x4f942c LDP	X19, X20, [SP, #16]

  (3437) 0x4f9430 LDP	X21, X22, [SP, #32]

  (3437) 0x4f9434 LDP	X23, X24, [SP, #48]

  (3437) 0x4f9438 LDP	X29, X30, [SP], #80

  (3437) 0x4f943c RET

  (3437) 0x4f9440 LDR	X6, [X19]

  (3437) 0x4f9444 MOVZ	X16, #1

  (3437) 0x4f9448 ADD	X15, X15, X6

  (3437) 0x4f944c STR	X15, [X13]

  (3437) 0x4f9450 B	4f918c

  (3437) 0x4f9494 ORR	X1, XZR, X21

  (3437) 0x4f9498 MOVZ	X3, #0

  (3437) 0x4f949c LDR	X2, [X23, #24]

  (3437) 0x4f94a0 ADD	X0, SP, #64

  (3437) 0x4f94a4 BL	504720

  (3437) 0x4f94a8 LDR	X13, [SP, #64]

  (3437) 0x4f94ac STR	X13, [X22, #40]

  (3437) 0x4f94b0 B	4f9400

  (3437) 0x4f94c0 MOVZ	X1, #8

  (3437) 0x4f94c4 ADD	X0, X21, #1

  (3437) 0x4f94c8 BL	51674c

  (3437) 0x4f94cc B	4f9290

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 199 - 221

--------------------------------------------------------------------------------

199:    for (i = 0; i < local_num_rows; i++)

200:       diag_i[i+1] = diag_i[i] + diag_sizes[i];

201:    hypre_CSRMatrixI(diag) = diag_i;

202:    hypre_CSRMatrixNumNonzeros(diag) = diag_i[local_num_rows];

203:    offd =  hypre_ParCSRMatrixOffd(par_matrix);

204:    offd_i =  hypre_CSRMatrixI(offd);

205:    if (!offd_i)

206:       offd_i = hypre_CTAlloc(HYPRE_Int, local_num_rows+1);

207:    for (i = 0; i < local_num_rows; i++)

208:       offd_i[i+1] = offd_i[i] + offdiag_sizes[i];

209:    hypre_CSRMatrixI(offd) = offd_i;

210:    hypre_CSRMatrixNumNonzeros(offd) = offd_i[local_num_rows];

211:    if (!aux_matrix)

212:    {

213:       hypre_AuxParCSRMatrixCreate(&aux_matrix, local_num_rows,

214:                                   hypre_CSRMatrixNumCols(diag), NULL);

215:       hypre_IJMatrixTranslator(matrix) = aux_matrix;

216:    }

217:    hypre_AuxParCSRMatrixNeedAux(aux_matrix) = 0;

218:

219:    return hypre_error_flag;

220:

221: }

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	P10, P11, P12,
Function	hypre_IJMatrixSetDiagOffdSizesParCSR
Source	IJMatrix_parcsr.c:199-200
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.33
CQA cycles if no scalar integer	5.33
CQA cycles if FP arith vectorized	5.33
CQA cycles if fully vectorized	1.33
Front-end cycles	4.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	4.25
P2 cycles	4.25
P3 cycles	4.25
P4 cycles	4.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	5.33
P10 cycles	5.33
P11 cycles	5.33
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	34.00
Nb uops	34.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	P10, P11, P12,
Function	hypre_IJMatrixSetDiagOffdSizesParCSR
Source	IJMatrix_parcsr.c:199-200
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.33
CQA cycles if no scalar integer	5.33
CQA cycles if FP arith vectorized	5.33
CQA cycles if fully vectorized	1.33
Front-end cycles	4.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	4.25
P2 cycles	4.25
P3 cycles	4.25
P4 cycles	4.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	5.33
P10 cycles	5.33
P11 cycles	5.33
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	34.00
Nb uops	34.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_IJMatrixSetDiagOffdSizesParCSR
Source file and lines	IJMatrix_parcsr.c:199-221
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:199-221.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:199-200.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 5.33 to 1.33 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	34
loop length	136
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	4.25	4.25	4.25	4.25	0.00	0.00	0.00	0.00	5.33	5.33	5.33	4.00	4.00
cycles	0.50	0.50	4.25	4.25	4.25	4.25	0.00	0.00	0.00	0.00	5.33	5.33	5.33	4.00	4.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.25
Overall L1	5.33

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.33 cycles. At this rate:

12% of peak load performance is reached (12.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
25% of peak store performance is reached (12.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4f91f4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X17, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X16, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X30, X16, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X16, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X7, X16, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X6, X16, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X5, X16, #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X3, X15, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X3, [X13, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X16, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X2, [X19, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X3, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X13, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X13, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X19, X30,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X14, [X13, X30,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [X19, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X17, X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X17, [X13, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X19, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X30, X17, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X30, [X13, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X19, X6,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X30, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X1, [X13, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X7, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X1, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X15, [X13, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X21, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 4f91f4 <hypre_IJMatrixSetDiagOffdSizesParCSR+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_IJMatrixSetDiagOffdSizesParCSR
Source file and lines	IJMatrix_parcsr.c:199-221
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:199-221.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:199-200.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 5.33 to 1.33 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	34
loop length	136
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	4.25	4.25	4.25	4.25	0.00	0.00	0.00	0.00	5.33	5.33	5.33	4.00	4.00
cycles	0.50	0.50	4.25	4.25	4.25	4.25	0.00	0.00	0.00	0.00	5.33	5.33	5.33	4.00	4.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.25
Overall L1	5.33

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.33 cycles. At this rate:

12% of peak load performance is reached (12.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
25% of peak store performance is reached (12.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4f91f4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X17, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X16, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X30, X16, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X16, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X7, X16, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X6, X16, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X5, X16, #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X3, X15, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X3, [X13, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X16, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X2, [X19, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X3, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X13, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X13, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X19, X30,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X14, [X13, X30,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [X19, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X17, X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X17, [X13, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X19, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X30, X17, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X30, [X13, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X19, X6,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X30, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X1, [X13, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X7, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X1, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X15, [X13, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X21, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 4f91f4 <hypre_IJMatrixSetDiagOffdSizesParCSR+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code