OV - exec - Loop 3406

	Loop Id: 3406	Module: exec	Source: IJMatrix_parcsr.c:3383-3454 [...]	Coverage: 0.03%

0x4f6760 LDR	X1, [X27, X21,LSL #3]

0x4f6764 CMP	X8, X1

0x4f6768 CCMP	X9, X1, #0, #10

0x4f676c B.LE	4f696c

0x4f6770 LDR	X0, [X18, X6]

0x4f6774 CMP	X3, X0

0x4f6778 B.LE	4f68f4

0x4f677c SUB	X30, X3, X0

0x4f6780 ANDS	X4, X30, #4224

0x4f6784 B.EQ	4f684c

0x4f6788 CMP	X4, #1

0x4f678c B.EQ	4f6830

0x4f6790 CMP	X4, #2

0x4f6794 B.EQ	4f681c

0x4f6798 CMP	X4, #3

0x4f679c B.EQ	4f6808

0x4f67a0 CMP	X4, #4

0x4f67a4 B.EQ	4f67f4

0x4f67a8 CMP	X4, #5

0x4f67ac B.EQ	4f67e0

0x4f67b0 CMP	X4, #6

0x4f67b4 B.EQ	4f67cc

0x4f67b8 LDR	X11, [X23, X0,LSL #3]

0x4f67bc UBFM	X2, X0, #61, #60

0x4f67c0 CMP	X1, X11

0x4f67c4 B.EQ	4f6e08

0x4f67c8 ADD	X0, X0, #1

0x4f67cc LDR	X12, [X23, X0,LSL #3]

0x4f67d0 UBFM	X2, X0, #61, #60

0x4f67d4 CMP	X1, X12

0x4f67d8 B.EQ	4f6e08

0x4f67dc ADD	X0, X0, #1

0x4f67e0 LDR	X13, [X23, X0,LSL #3]

0x4f67e4 UBFM	X2, X0, #61, #60

0x4f67e8 CMP	X1, X13

0x4f67ec B.EQ	4f6e08

0x4f67f0 ADD	X0, X0, #1

0x4f67f4 LDR	X14, [X23, X0,LSL #3]

0x4f67f8 UBFM	X2, X0, #61, #60

0x4f67fc CMP	X1, X14

0x4f6800 B.EQ	4f6e08

0x4f6804 ADD	X0, X0, #1

0x4f6808 LDR	X15, [X23, X0,LSL #3]

0x4f680c UBFM	X2, X0, #61, #60

0x4f6810 CMP	X1, X15

0x4f6814 B.EQ	4f6e08

0x4f6818 ADD	X0, X0, #1

0x4f681c LDR	X25, [X23, X0,LSL #3]

0x4f6820 UBFM	X2, X0, #61, #60

0x4f6824 CMP	X1, X25

0x4f6828 B.EQ	4f6e08

0x4f682c ADD	X0, X0, #1

0x4f6830 LDR	X30, [X23, X0,LSL #3]

0x4f6834 UBFM	X2, X0, #61, #60

0x4f6838 CMP	X1, X30

0x4f683c B.EQ	4f6e08

0x4f6840 ADD	X0, X0, #1

0x4f6844 CMP	X3, X0

0x4f6848 B.EQ	4f68f4

  (3407) 0x4f684c LDR	X30, [X23, X0,LSL #3]

  (3407) 0x4f6850 ADD	X4, X0, #1

  (3407) 0x4f6854 ADD	X12, X0, #3

  (3407) 0x4f6858 ADD	X11, X0, #2

  (3407) 0x4f685c ADD	X13, X0, #4

  (3407) 0x4f6860 ADD	X14, X0, #5

  (3407) 0x4f6864 ADD	X15, X0, #6

  (3407) 0x4f6868 ADD	X25, X0, #7

  (3407) 0x4f686c UBFM	X2, X0, #61, #60

  (3407) 0x4f6870 ADD	X0, X0, #8

  (3407) 0x4f6874 CMP	X1, X30

  (3407) 0x4f6878 B.EQ	4f6e08

  (3407) 0x4f687c LDR	X30, [X23, X4,LSL #3]

  (3407) 0x4f6880 UBFM	X2, X4, #61, #60

  (3407) 0x4f6884 CMP	X1, X30

  (3407) 0x4f6888 B.EQ	4f6e08

  (3407) 0x4f688c LDR	X4, [X23, X11,LSL #3]

  (3407) 0x4f6890 UBFM	X2, X11, #61, #60

  (3407) 0x4f6894 CMP	X1, X4

  (3407) 0x4f6898 B.EQ	4f6e08

  (3407) 0x4f689c LDR	X11, [X23, X12,LSL #3]

  (3407) 0x4f68a0 UBFM	X2, X12, #61, #60

  (3407) 0x4f68a4 CMP	X1, X11

  (3407) 0x4f68a8 B.EQ	4f6e08

  (3407) 0x4f68ac LDR	X12, [X23, X13,LSL #3]

  (3407) 0x4f68b0 UBFM	X2, X13, #61, #60

  (3407) 0x4f68b4 CMP	X1, X12

  (3407) 0x4f68b8 B.EQ	4f6e08

  (3407) 0x4f68bc LDR	X13, [X23, X14,LSL #3]

  (3407) 0x4f68c0 UBFM	X2, X14, #61, #60

  (3407) 0x4f68c4 CMP	X1, X13

  (3407) 0x4f68c8 B.EQ	4f6e08

  (3407) 0x4f68cc LDR	X14, [X23, X15,LSL #3]

  (3407) 0x4f68d0 UBFM	X2, X15, #61, #60

  (3407) 0x4f68d4 CMP	X1, X14

  (3407) 0x4f68d8 B.EQ	4f6e08

  (3407) 0x4f68dc LDR	X15, [X23, X25,LSL #3]

  (3407) 0x4f68e0 UBFM	X2, X25, #61, #60

  (3407) 0x4f68e4 CMP	X1, X15

  (3407) 0x4f68e8 B.EQ	4f6e08

  (3407) 0x4f68ec CMP	X3, X0

  (3407) 0x4f68f0 B.NE	4f684c

0x4f68f4 CMP	X20, X28

0x4f68f8 B.LE	4f7318

0x4f68fc LDR	D2, [X5, X21,LSL #3]

0x4f6900 UBFM	X2, X28, #61, #60

0x4f6904 STR	X1, [X23, X28,LSL #3]

0x4f6908 ADD	X28, X28, #1

0x4f690c STR	D2, [X19, X2]

0x4f6910 ADD	X21, X21, #1

0x4f6914 CMP	X21, X17

0x4f6918 B.NE	4f6760

0x4f6e08 LDR	D3, [X5, X21,LSL #3]

0x4f6e0c STR	D3, [X19, X2]

0x4f6e10 B	4f6910

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 3383 - 3454

--------------------------------------------------------------------------------

3383:   	          for (i=0; i < n; i++)

3384: 	          {

3385: 	             if (cols[indx] < col_0 || cols[indx] > col_n)

3386:                      /* insert into offd */

3387: 	             {

3388: 	                for (j=offd_i[row_local]; j < offd_indx; j++)

3389: 	                {

3390: 		           if (offd_j[j] == cols[indx])

3391: 		           {

3392:                               offd_data[j] = values[indx];

3393: 		              not_found = 0;

3394: 		              break;

3395: 		           }

3396: 	                }

3397: 	                if (not_found)

3398: 	                {

3399: 	                   if (cnt_offd < offd_space)

3400: 	                   {

3401: 	                      offd_j[cnt_offd] = cols[indx];

3402: 	                      offd_data[cnt_offd++] = values[indx];

[...]

3454: 	             indx++;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	7.50
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P0, P1,
Function	hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1
Source	IJMatrix_parcsr.c:3383-3385,IJMatrix_parcsr.c:3388-3392,IJMatrix_parcsr.c:3397-3402,IJMatrix_parcsr.c:3454-3454
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.00
CQA cycles if no scalar integer	1.33
CQA cycles if FP arith vectorized	10.00
CQA cycles if fully vectorized	2.50
Front-end cycles	9.00
DIV/SQRT cycles	10.00
P0 cycles	10.00
P1 cycles	9.50
P2 cycles	9.50
P3 cycles	9.50
P4 cycles	9.50
P5 cycles	1.00
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	4.83
P10 cycles	4.50
P11 cycles	4.67
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	72.00
Nb uops	72.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.20
Bytes prefetched	0.00
Bytes loaded	88.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	7.50
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P0, P1,
Function	hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1
Source	IJMatrix_parcsr.c:3383-3385,IJMatrix_parcsr.c:3388-3392,IJMatrix_parcsr.c:3397-3402,IJMatrix_parcsr.c:3454-3454
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.00
CQA cycles if no scalar integer	1.33
CQA cycles if FP arith vectorized	10.00
CQA cycles if fully vectorized	2.50
Front-end cycles	9.00
DIV/SQRT cycles	10.00
P0 cycles	10.00
P1 cycles	9.50
P2 cycles	9.50
P3 cycles	9.50
P4 cycles	9.50
P5 cycles	1.00
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	4.83
P10 cycles	4.50
P11 cycles	4.67
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	72.00
Nb uops	72.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.20
Bytes prefetched	0.00
Bytes loaded	88.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1
Source file and lines	IJMatrix_parcsr.c:3383-3454
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3383-3402,3454.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3383-3385,3388-3392,3397-3402,3454.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.00 to 1.33 cycles (7.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 10.00 to 2.50 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 88 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	72
loop length	288
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	10.00	10.00	9.50	9.50	9.50	9.50	1.00	1.00	0.00	0.00	4.83	4.50	4.67	0.50	0.50
cycles	10.00	10.00	9.50	9.50	9.50	9.50	1.00	1.00	0.00	0.00	4.83	4.50	4.67	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.00
Overall L1	10.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.00 cycles. At this rate:

9% of peak load performance is reached (8.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4f6760

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X1, [X27, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
CCMP X9, X1, #0, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.LE 4f696c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x6a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X18, X6]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 4f68f4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x62c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X30, X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ANDS X4, X30, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f684c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x584>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f6830 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x568>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f681c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x554>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X4, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f6808 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x540>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X4, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f67f4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x52c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X4, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f67e0 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x518>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X4, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f67cc <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X2, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X1, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f6e08 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X12, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X2, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X1, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f6e08 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X13, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X2, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X1, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f6e08 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X14, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X2, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X1, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f6e08 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X15, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X2, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X1, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f6e08 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X25, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X2, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f6e08 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X30, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X2, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X1, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f6e08 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f68f4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x62c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 4f7318 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1050>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D2, [X5, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
UBFM X2, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X1, [X23, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X28, X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR D2, [X19, X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X21, X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X21, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 4f6760 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x498>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D3, [X5, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D3, [X19, X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
B 4f6910 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x648>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1
Source file and lines	IJMatrix_parcsr.c:3383-3454
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.00 to 1.33 cycles (7.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 88 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	72
loop length	288
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	10.00	10.00	9.50	9.50	9.50	9.50	1.00	1.00	0.00	0.00	4.83	4.50	4.67	0.50	0.50
cycles	10.00	10.00	9.50	9.50	9.50	9.50	1.00	1.00	0.00	0.00	4.83	4.50	4.67	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.00
Overall L1	10.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.00 cycles. At this rate:

9% of peak load performance is reached (8.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4f6760

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X1, [X27, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
CCMP X9, X1, #0, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.LE 4f696c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x6a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X18, X6]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 4f68f4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x62c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X30, X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ANDS X4, X30, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f684c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x584>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f6830 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x568>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f681c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x554>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X4, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f6808 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x540>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X4, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f67f4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x52c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X4, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f67e0 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x518>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X4, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f67cc <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X2, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X1, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f6e08 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X12, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X2, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X1, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f6e08 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X13, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X2, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X1, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f6e08 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X14, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X2, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X1, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f6e08 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X15, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X2, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X1, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f6e08 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X25, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X2, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f6e08 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X30, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X2, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X1, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f6e08 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f68f4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x62c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 4f7318 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1050>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D2, [X5, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
UBFM X2, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X1, [X23, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X28, X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR D2, [X19, X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X21, X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X21, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 4f6760 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x498>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D3, [X5, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D3, [X19, X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
B 4f6910 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x648>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code