OV - exec - Loop 3396

	Loop Id: 3396	Module: exec	Source: IJMatrix_parcsr.c:3291-3500 [...]	Coverage: 0.01%

0x4f66ac LDR	X11, [SP, #112]

0x4f66b0 LDR	X12, [SP, #120]

0x4f66b4 LDR	X14, [SP, #104]

0x4f66b8 LDR	X25, [X11, X26,LSL #3]

0x4f66bc LDR	X13, [X12]

0x4f66c0 LDR	X2, [X14, X26,LSL #3]

0x4f66c4 CMP	X25, X13

0x4f66c8 B.LT	4f6b14

0x4f66cc LDR	X16, [SP, #144]

0x4f66d0 LDR	X17, [X16]

0x4f66d4 CMP	X25, X17

0x4f66d8 B.GE	4f6b14

0x4f66dc SUB	X14, X25, X13

0x4f66e0 LDR	X18, [SP, #192]

0x4f66e4 UBFM	X6, X14, #61, #60

0x4f66e8 CBNZ	X18, 4f6e20

0x4f6940 LDR	X7, [SP, #96]

0x4f6944 ADD	X26, X26, #1

0x4f6948 CMP	X7, X26

0x4f694c B.NE	4f66ac

0x4f6b14 LDR	X18, [SP, #128]

0x4f6b18 ADD	X21, X21, X2

0x4f6b1c CBZ	X18, 4f6940

0x4f6b20 LDR	X15, [SP, #152]

0x4f6b24 CMP	X15, #0

0x4f6b28 B.LE	4f6940

0x4f6b2c ADD	X14, X27, X2,LSL #3

0x4f6b30 MOVZ	X11, #0

0x4f6b34 LDR	X6, [SP, #160]

0x4f6b38 LDP	X7, X10, [SP, #176]

0x4f6b3c B	4f6b4c

  (3397) 0x4f6b40 ADD	X6, X6, #16

  (3397) 0x4f6b44 CMP	X7, X6

  (3397) 0x4f6b48 B.EQ	4f6940

  (3397) 0x4f6b4c LDP	X30, X4, [X6]

  (3397) 0x4f6b50 ORR	X28, XZR, X11

  (3397) 0x4f6b54 ADD	X11, X11, X4

  (3397) 0x4f6b58 CMP	X25, X30

  (3397) 0x4f6b5c B.NE	4f6b40

  (3397) 0x4f6b60 CMP	X2, #0

  (3397) 0x4f6b64 B.LE	4f6b40

  (3397) 0x4f6b68 CMP	X4, #0

  (3397) 0x4f6b6c B.LE	4f6b40

  (3397) 0x4f6b70 ADD	X12, X10, X28,LSL #3

  (3397) 0x4f6b74 ORR	X3, XZR, X27

  (3397) 0x4f6b78 ADD	X4, X10, X11,LSL #3

  (3397) 0x4f6b7c HINT	#0

    (3399) 0x4f6b80 SUB	X1, X4, X12

    (3399) 0x4f6b84 ORR	X0, XZR, X12

    (3399) 0x4f6b88 SUB	X13, X1, #8

    (3399) 0x4f6b8c UBFM	X16, X13, #3, #63

    (3399) 0x4f6b90 ADD	X17, X16, #1

    (3399) 0x4f6b94 ANDS	X18, X17, #4224

    (3399) 0x4f6b98 B.EQ	4f6c70

    (3399) 0x4f6b9c CMP	X18, #1

    (3399) 0x4f6ba0 B.EQ	4f6c44

    (3399) 0x4f6ba4 CMP	X18, #2

    (3399) 0x4f6ba8 B.EQ	4f6c30

    (3399) 0x4f6bac CMP	X18, #3

    (3399) 0x4f6bb0 B.EQ	4f6c1c

    (3399) 0x4f6bb4 CMP	X18, #4

    (3399) 0x4f6bb8 B.EQ	4f6c08

    (3399) 0x4f6bbc CMP	X18, #5

    (3399) 0x4f6bc0 B.EQ	4f6bf4

    (3399) 0x4f6bc4 CMP	X18, #6

    (3399) 0x4f6bc8 B.EQ	4f6be0

    (3399) 0x4f6bcc LDR	X15, [X3]

    (3399) 0x4f6bd0 LDR	X28, [X12]

    (3399) 0x4f6bd4 CMP	X28, X15

    (3399) 0x4f6bd8 B.EQ	4f6df4

    (3399) 0x4f6bdc ADD	X0, X12, #8

    (3399) 0x4f6be0 LDR	X13, [X0]

    (3399) 0x4f6be4 LDR	X1, [X3]

    (3399) 0x4f6be8 CMP	X13, X1

    (3399) 0x4f6bec B.EQ	4f6de0

    (3399) 0x4f6bf0 ADD	X0, X0, #8

    (3399) 0x4f6bf4 LDR	X18, [X0]

    (3399) 0x4f6bf8 LDR	X15, [X3]

    (3399) 0x4f6bfc CMP	X18, X15

    (3399) 0x4f6c00 B.EQ	4f6dcc

    (3399) 0x4f6c04 ADD	X0, X0, #8

    (3399) 0x4f6c08 LDR	X13, [X0]

    (3399) 0x4f6c0c LDR	X1, [X3]

    (3399) 0x4f6c10 CMP	X13, X1

    (3399) 0x4f6c14 B.EQ	4f6db8

    (3399) 0x4f6c18 ADD	X0, X0, #8

    (3399) 0x4f6c1c LDR	X18, [X0]

    (3399) 0x4f6c20 LDR	X15, [X3]

    (3399) 0x4f6c24 CMP	X18, X15

    (3399) 0x4f6c28 B.EQ	4f6da4

    (3399) 0x4f6c2c ADD	X0, X0, #8

    (3399) 0x4f6c30 LDR	X13, [X0]

    (3399) 0x4f6c34 LDR	X1, [X3]

    (3399) 0x4f6c38 CMP	X13, X1

    (3399) 0x4f6c3c B.EQ	4f6d90

    (3399) 0x4f6c40 ADD	X0, X0, #8

    (3399) 0x4f6c44 LDR	X18, [X0]

    (3399) 0x4f6c48 LDR	X15, [X3]

    (3399) 0x4f6c4c CMP	X18, X15

    (3399) 0x4f6c50 B.NE	4f6c64

    (3399) 0x4f6c54 STR	X22, [X0]

    (3399) 0x4f6c58 LDR	X28, [X20, X19]

    (3399) 0x4f6c5c ADD	X30, X28, #1

    (3399) 0x4f6c60 STR	X30, [X20, X19]

    (3399) 0x4f6c64 ADD	X0, X0, #8

    (3399) 0x4f6c68 CMP	X4, X0

    (3399) 0x4f6c6c B.EQ	4f6d80

      (3398) 0x4f6c70 LDR	X13, [X0]

      (3398) 0x4f6c74 LDR	X1, [X3]

      (3398) 0x4f6c78 CMP	X13, X1

      (3398) 0x4f6c7c B.NE	4f6c90

      (3398) 0x4f6c80 STR	X22, [X0]

      (3398) 0x4f6c84 LDR	X16, [X20, X19]

      (3398) 0x4f6c88 ADD	X17, X16, #1

      (3398) 0x4f6c8c STR	X17, [X20, X19]

      (3398) 0x4f6c90 LDR	X28, [X3]

      (3398) 0x4f6c94 ADD	X18, X0, #8

      (3398) 0x4f6c98 LDR	X15, [X0, #8]

      (3398) 0x4f6c9c CMP	X15, X28

      (3398) 0x4f6ca0 B.NE	4f6cb4

      (3398) 0x4f6ca4 STR	X22, [X0, #8]

      (3398) 0x4f6ca8 LDR	X0, [X20, X19]

      (3398) 0x4f6cac ADD	X30, X0, #1

      (3398) 0x4f6cb0 STR	X30, [X20, X19]

      (3398) 0x4f6cb4 LDR	X1, [X3]

      (3398) 0x4f6cb8 LDR	X13, [X18, #8]

      (3398) 0x4f6cbc CMP	X13, X1

      (3398) 0x4f6cc0 B.NE	4f6cd4

      (3398) 0x4f6cc4 STR	X22, [X18, #8]

      (3398) 0x4f6cc8 LDR	X16, [X20, X19]

      (3398) 0x4f6ccc ADD	X17, X16, #1

      (3398) 0x4f6cd0 STR	X17, [X20, X19]

      (3398) 0x4f6cd4 LDR	X28, [X3]

      (3398) 0x4f6cd8 LDR	X15, [X18, #16]

      (3398) 0x4f6cdc CMP	X15, X28

      (3398) 0x4f6ce0 B.NE	4f6cf4

      (3398) 0x4f6ce4 STR	X22, [X18, #16]

      (3398) 0x4f6ce8 LDR	X0, [X20, X19]

      (3398) 0x4f6cec ADD	X30, X0, #1

      (3398) 0x4f6cf0 STR	X30, [X20, X19]

      (3398) 0x4f6cf4 LDR	X1, [X3]

      (3398) 0x4f6cf8 LDR	X13, [X18, #24]

      (3398) 0x4f6cfc CMP	X13, X1

      (3398) 0x4f6d00 B.NE	4f6d14

      (3398) 0x4f6d04 STR	X22, [X18, #24]

      (3398) 0x4f6d08 LDR	X16, [X20, X19]

      (3398) 0x4f6d0c ADD	X17, X16, #1

      (3398) 0x4f6d10 STR	X17, [X20, X19]

      (3398) 0x4f6d14 LDR	X28, [X3]

      (3398) 0x4f6d18 LDR	X15, [X18, #32]

      (3398) 0x4f6d1c CMP	X15, X28

      (3398) 0x4f6d20 B.NE	4f6d34

      (3398) 0x4f6d24 STR	X22, [X18, #32]

      (3398) 0x4f6d28 LDR	X0, [X20, X19]

      (3398) 0x4f6d2c ADD	X30, X0, #1

      (3398) 0x4f6d30 STR	X30, [X20, X19]

      (3398) 0x4f6d34 LDR	X1, [X3]

      (3398) 0x4f6d38 LDR	X13, [X18, #40]

      (3398) 0x4f6d3c CMP	X13, X1

      (3398) 0x4f6d40 B.NE	4f6d54

      (3398) 0x4f6d44 STR	X22, [X18, #40]

      (3398) 0x4f6d48 LDR	X16, [X20, X19]

      (3398) 0x4f6d4c ADD	X17, X16, #1

      (3398) 0x4f6d50 STR	X17, [X20, X19]

      (3398) 0x4f6d54 LDR	X28, [X3]

      (3398) 0x4f6d58 LDR	X15, [X18, #48]

      (3398) 0x4f6d5c CMP	X15, X28

      (3398) 0x4f6d60 B.NE	4f6d74

      (3398) 0x4f6d64 STR	X22, [X18, #48]

      (3398) 0x4f6d68 LDR	X0, [X20, X19]

      (3398) 0x4f6d6c ADD	X30, X0, #1

      (3398) 0x4f6d70 STR	X30, [X20, X19]

      (3398) 0x4f6d74 ADD	X0, X18, #56

      (3398) 0x4f6d78 CMP	X4, X0

      (3398) 0x4f6d7c B.NE	4f6c70

    (3399) 0x4f6d80 ADD	X3, X3, #8

    (3399) 0x4f6d84 CMP	X14, X3

    (3399) 0x4f6d88 B.NE	4f6b80

  (3397) 0x4f6d8c B	4f6b40

    (3399) 0x4f6d90 STR	X22, [X0]

    (3399) 0x4f6d94 LDR	X16, [X20, X19]

    (3399) 0x4f6d98 ADD	X17, X16, #1

    (3399) 0x4f6d9c STR	X17, [X20, X19]

    (3399) 0x4f6da0 B	4f6c40

    (3399) 0x4f6da4 STR	X22, [X0]

    (3399) 0x4f6da8 LDR	X28, [X20, X19]

    (3399) 0x4f6dac ADD	X30, X28, #1

    (3399) 0x4f6db0 STR	X30, [X20, X19]

    (3399) 0x4f6db4 B	4f6c2c

    (3399) 0x4f6db8 STR	X22, [X0]

    (3399) 0x4f6dbc LDR	X16, [X20, X19]

    (3399) 0x4f6dc0 ADD	X17, X16, #1

    (3399) 0x4f6dc4 STR	X17, [X20, X19]

    (3399) 0x4f6dc8 B	4f6c18

    (3399) 0x4f6dcc STR	X22, [X0]

    (3399) 0x4f6dd0 LDR	X28, [X20, X19]

    (3399) 0x4f6dd4 ADD	X30, X28, #1

    (3399) 0x4f6dd8 STR	X30, [X20, X19]

    (3399) 0x4f6ddc B	4f6c04

    (3399) 0x4f6de0 STR	X22, [X0]

    (3399) 0x4f6de4 LDR	X16, [X20, X19]

    (3399) 0x4f6de8 ADD	X17, X16, #1

    (3399) 0x4f6dec STR	X17, [X20, X19]

    (3399) 0x4f6df0 B	4f6bf0

    (3399) 0x4f6df4 STR	X22, [X12]

    (3399) 0x4f6df8 LDR	X30, [X20, X19]

    (3399) 0x4f6dfc ADD	X0, X30, #1

    (3399) 0x4f6e00 STR	X0, [X20, X19]

    (3399) 0x4f6e04 B	4f6bdc

0x4f6e20 LDR	X1, [SP, #200]

0x4f6e24 LDR	X0, [SP, #240]

0x4f6e28 LDR	X11, [SP, #248]

0x4f6e2c LDR	X28, [X1, X14,LSL #3]

0x4f6e30 LDR	X30, [X0, X14,LSL #3]

0x4f6e34 LDR	X12, [X11, X14,LSL #3]

0x4f6e38 LDR	X4, [SP, #256]

0x4f6e3c SUB	X17, X30, X28

0x4f6e40 STP	X12, X30, [SP, #208]

0x4f6e44 LDR	X25, [X4, X14,LSL #3]

0x4f6e48 CMP	X2, X17

0x4f6e4c B.GT	4f72b8

0x4f6e50 CMP	X2, #0

0x4f6e54 B.LE	4f6940

0x4f6e58 MOVZ	X7, #0

0x4f6e5c ADD	X3, X21, X2

0x4f6e60 STR	X20, [SP, #264]

0x4f6e64 ORR	X11, XZR, X28

0x4f6e68 ORR	X20, XZR, X3

0x4f6e6c MOVZ	X13, #0

0x4f6e70 LDR	X30, [SP, #208]

0x4f6e74 STR	X3, [SP, #168]

0x4f6e78 LDR	X3, [SP, #216]

0x4f6e7c STR	X14, [SP, #208]

  (3400) 0x4f6e80 MOVZ	X0, #0

  (3400) 0x4f6e84 LDR	X1, [X27, X21,LSL #3]

  (3400) 0x4f6e88 CMP	X28, #0

  (3400) 0x4f6e8c B.LE	4f7004

  (3400) 0x4f6e90 ANDS	X6, X28, #4224

  (3400) 0x4f6e94 B.EQ	4f6f5c

  (3400) 0x4f6e98 CMP	X6, #1

  (3400) 0x4f6e9c B.EQ	4f6f40

  (3400) 0x4f6ea0 CMP	X6, #2

  (3400) 0x4f6ea4 B.EQ	4f6f2c

  (3400) 0x4f6ea8 CMP	X6, #3

  (3400) 0x4f6eac B.EQ	4f6f18

  (3400) 0x4f6eb0 CMP	X6, #4

  (3400) 0x4f6eb4 B.EQ	4f6f04

  (3400) 0x4f6eb8 CMP	X6, #5

  (3400) 0x4f6ebc B.EQ	4f6ef0

  (3400) 0x4f6ec0 CMP	X6, #6

  (3400) 0x4f6ec4 B.EQ	4f6edc

  (3400) 0x4f6ec8 LDR	X16, [X25]

  (3400) 0x4f6ecc MOVZ	X2, #0

  (3400) 0x4f6ed0 CMP	X16, X1

  (3400) 0x4f6ed4 B.EQ	4f7268

  (3400) 0x4f6ed8 MOVZ	X0, #1

  (3400) 0x4f6edc LDR	X18, [X25, X0,LSL #3]

  (3400) 0x4f6ee0 UBFM	X2, X0, #61, #60

  (3400) 0x4f6ee4 CMP	X18, X1

  (3400) 0x4f6ee8 B.EQ	4f7268

  (3400) 0x4f6eec ADD	X0, X0, #1

  (3400) 0x4f6ef0 LDR	X10, [X25, X0,LSL #3]

  (3400) 0x4f6ef4 UBFM	X2, X0, #61, #60

  (3400) 0x4f6ef8 CMP	X10, X1

  (3400) 0x4f6efc B.EQ	4f7268

  (3400) 0x4f6f00 ADD	X0, X0, #1

  (3400) 0x4f6f04 LDR	X17, [X25, X0,LSL #3]

  (3400) 0x4f6f08 UBFM	X2, X0, #61, #60

  (3400) 0x4f6f0c CMP	X17, X1

  (3400) 0x4f6f10 B.EQ	4f7268

  (3400) 0x4f6f14 ADD	X0, X0, #1

  (3400) 0x4f6f18 LDR	X4, [X25, X0,LSL #3]

  (3400) 0x4f6f1c UBFM	X2, X0, #61, #60

  (3400) 0x4f6f20 CMP	X4, X1

  (3400) 0x4f6f24 B.EQ	4f7268

  (3400) 0x4f6f28 ADD	X0, X0, #1

  (3400) 0x4f6f2c LDR	X12, [X25, X0,LSL #3]

  (3400) 0x4f6f30 UBFM	X2, X0, #61, #60

  (3400) 0x4f6f34 CMP	X12, X1

  (3400) 0x4f6f38 B.EQ	4f7268

  (3400) 0x4f6f3c ADD	X0, X0, #1

  (3400) 0x4f6f40 LDR	X14, [X25, X0,LSL #3]

  (3400) 0x4f6f44 UBFM	X2, X0, #61, #60

  (3400) 0x4f6f48 CMP	X14, X1

  (3400) 0x4f6f4c B.EQ	4f7268

  (3400) 0x4f6f50 ADD	X0, X0, #1

  (3400) 0x4f6f54 CMP	X28, X0

  (3400) 0x4f6f58 B.EQ	4f7004

    (3402) 0x4f6f5c LDR	X18, [X25, X0,LSL #3]

    (3402) 0x4f6f60 ADD	X4, X0, #1

    (3402) 0x4f6f64 ADD	X10, X0, #3

    (3402) 0x4f6f68 ADD	X6, X0, #2

    (3402) 0x4f6f6c ADD	X12, X0, #4

    (3402) 0x4f6f70 ADD	X15, X0, #5

    (3402) 0x4f6f74 ADD	X16, X0, #6

    (3402) 0x4f6f78 ADD	X17, X0, #7

    (3402) 0x4f6f7c UBFM	X2, X0, #61, #60

    (3402) 0x4f6f80 ADD	X0, X0, #8

    (3402) 0x4f6f84 CMP	X18, X1

    (3402) 0x4f6f88 B.EQ	4f7268

    (3402) 0x4f6f8c LDR	X14, [X25, X4,LSL #3]

    (3402) 0x4f6f90 UBFM	X2, X4, #61, #60

    (3402) 0x4f6f94 CMP	X14, X1

    (3402) 0x4f6f98 B.EQ	4f7268

    (3402) 0x4f6f9c LDR	X4, [X25, X6,LSL #3]

    (3402) 0x4f6fa0 UBFM	X2, X6, #61, #60

    (3402) 0x4f6fa4 CMP	X4, X1

    (3402) 0x4f6fa8 B.EQ	4f7268

    (3402) 0x4f6fac LDR	X18, [X25, X10,LSL #3]

    (3402) 0x4f6fb0 UBFM	X2, X10, #61, #60

    (3402) 0x4f6fb4 CMP	X18, X1

    (3402) 0x4f6fb8 B.EQ	4f7268

    (3402) 0x4f6fbc LDR	X10, [X25, X12,LSL #3]

    (3402) 0x4f6fc0 UBFM	X2, X12, #61, #60

    (3402) 0x4f6fc4 CMP	X10, X1

    (3402) 0x4f6fc8 B.EQ	4f7268

    (3402) 0x4f6fcc LDR	X6, [X25, X15,LSL #3]

    (3402) 0x4f6fd0 UBFM	X2, X15, #61, #60

    (3402) 0x4f6fd4 CMP	X6, X1

    (3402) 0x4f6fd8 B.EQ	4f7268

    (3402) 0x4f6fdc LDR	X12, [X25, X16,LSL #3]

    (3402) 0x4f6fe0 UBFM	X2, X16, #61, #60

    (3402) 0x4f6fe4 CMP	X12, X1

    (3402) 0x4f6fe8 B.EQ	4f7268

    (3402) 0x4f6fec LDR	X15, [X25, X17,LSL #3]

    (3402) 0x4f6ff0 UBFM	X2, X17, #61, #60

    (3402) 0x4f6ff4 CMP	X15, X1

    (3402) 0x4f6ff8 B.EQ	4f7268

    (3402) 0x4f6ffc CMP	X28, X0

    (3402) 0x4f7000 B.NE	4f6f5c

  (3400) 0x4f7004 LDR	D4, [X5, X21,LSL #3]

  (3400) 0x4f7008 CMP	X3, X11

  (3400) 0x4f700c B.LE	4f7274

  (3400) 0x4f7010 UBFM	X17, X11, #61, #60

  (3400) 0x4f7014 STR	X1, [X25, X11,LSL #3]

  (3400) 0x4f7018 ADD	X11, X11, #1

  (3400) 0x4f701c STR	D4, [X30, X17]

  (3400) 0x4f7020 ADD	X21, X21, #1

  (3400) 0x4f7024 CMP	X21, X20

  (3400) 0x4f7028 B.NE	4f6e80

0x4f702c LDP	X0, X14, [SP, #200]

0x4f7030 ADD	X21, X11, X13

0x4f7034 LDR	X20, [SP, #264]

0x4f7038 STR	X21, [X0, X14,LSL #3]

0x4f703c CBNZ	X13, 4f704c

0x4f7040 CBNZ	X7, 4f723c

0x4f7044 LDR	X21, [SP, #168]

0x4f7048 B	4f6940

0x4f704c LDR	X28, [SP, #256]

0x4f7050 UBFM	X25, X21, #61, #60

0x4f7054 ORR	X1, XZR, X25

0x4f7058 STP	X14, X7, [SP, #208]

0x4f705c STP	X11, X13, [SP, #264]

0x4f7060 LDR	X0, [X28, X14,LSL #3]

0x4f7064 STR	X8, [SP, #280]

0x4f7068 STP	X9, X5, [SP, #304]

0x4f706c BL	51678c

0x4f7070 ORR	X1, XZR, X25

0x4f7074 LDR	X8, [SP, #208]

0x4f7078 ORR	X7, XZR, X0

0x4f707c LDR	X25, [SP, #248]

0x4f7080 LDR	X0, [X25, X8,LSL #3]

0x4f7084 STR	X7, [X28, X8,LSL #3]

0x4f7088 BL	51678c

0x4f708c LDP	X6, X7, [SP, #208]

0x4f7090 ORR	X18, XZR, X0

0x4f7094 MOVZ	X0, #0

0x4f7098 LDP	X4, X13, [SP, #264]

0x4f709c LDP	X9, X5, [SP, #304]

0x4f70a0 UBFM	X15, X4, #61, #60

0x4f70a4 ANDS	X11, X13, #4224

0x4f70a8 ADD	X1, X18, X15

0x4f70ac LDR	X12, [SP, #240]

0x4f70b0 LDR	X10, [X28, X6,LSL #3]

0x4f70b4 STR	X18, [X25, X6,LSL #3]

0x4f70b8 LDR	X8, [SP, #280]

0x4f70bc STR	X21, [X12, X6,LSL #3]

0x4f70c0 ADD	X2, X10, X15

0x4f70c4 B.EQ	4f7478

0x4f70c8 CMP	X11, #1

0x4f70cc B.EQ	4f7170

0x4f70d0 CMP	X11, #2

0x4f70d4 B.EQ	4f7158

0x4f70d8 CMP	X11, #3

0x4f70dc B.EQ	4f7140

0x4f70e0 CMP	X11, #4

0x4f70e4 B.EQ	4f7128

0x4f70e8 CMP	X11, #5

0x4f70ec B.EQ	4f7110

0x4f70f0 CMP	X11, #6

0x4f70f4 B.NE	4f738c

0x4f70f8 LDR	X30, [SP, #136]

0x4f70fc LDR	X3, [X7, X0,LSL #3]

0x4f7100 LDR	D7, [X30, X0,LSL #3]

0x4f7104 STR	X3, [X2, X0,LSL #3]

0x4f7108 STR	D7, [X1, X0,LSL #3]

0x4f710c ADD	X0, X0, #1

0x4f7110 LDR	X21, [SP, #136]

0x4f7114 LDR	X14, [X7, X0,LSL #3]

0x4f7118 LDR	D16, [X21, X0,LSL #3]

0x4f711c STR	X14, [X2, X0,LSL #3]

0x4f7120 STR	D16, [X1, X0,LSL #3]

0x4f7124 ADD	X0, X0, #1

0x4f7128 LDR	X25, [SP, #136]

0x4f712c LDR	X28, [X7, X0,LSL #3]

0x4f7130 LDR	D17, [X25, X0,LSL #3]

0x4f7134 STR	X28, [X2, X0,LSL #3]

0x4f7138 STR	D17, [X1, X0,LSL #3]

0x4f713c ADD	X0, X0, #1

0x4f7140 LDR	X6, [SP, #136]

0x4f7144 LDR	X18, [X7, X0,LSL #3]

0x4f7148 LDR	D18, [X6, X0,LSL #3]

0x4f714c STR	X18, [X2, X0,LSL #3]

0x4f7150 STR	D18, [X1, X0,LSL #3]

0x4f7154 ADD	X0, X0, #1

0x4f7158 LDR	X4, [SP, #136]

0x4f715c LDR	X12, [X7, X0,LSL #3]

0x4f7160 LDR	D19, [X4, X0,LSL #3]

0x4f7164 STR	X12, [X2, X0,LSL #3]

0x4f7168 STR	D19, [X1, X0,LSL #3]

0x4f716c ADD	X0, X0, #1

0x4f7170 LDR	X3, [SP, #136]

0x4f7174 LDR	X10, [X7, X0,LSL #3]

0x4f7178 LDR	D20, [X3, X0,LSL #3]

0x4f717c ORR	X16, XZR, X3

0x4f7180 STR	X10, [X2, X0,LSL #3]

0x4f7184 STR	D20, [X1, X0,LSL #3]

0x4f7188 ADD	X0, X0, #1

0x4f718c CMP	X13, X0

0x4f7190 B.EQ	4f723c

  (3401) 0x4f7194 LDR	X17, [X7, X0,LSL #3]

  (3401) 0x4f7198 ADD	X30, X0, #1

  (3401) 0x4f719c ADD	X15, X0, #2

  (3401) 0x4f71a0 ADD	X14, X0, #3

  (3401) 0x4f71a4 ADD	X11, X0, #4

  (3401) 0x4f71a8 LDR	D21, [X16, X0,LSL #3]

  (3401) 0x4f71ac ADD	X18, X0, #5

  (3401) 0x4f71b0 ADD	X6, X0, #6

  (3401) 0x4f71b4 ADD	X4, X0, #7

  (3401) 0x4f71b8 STR	X17, [X2, X0,LSL #3]

  (3401) 0x4f71bc LDR	X21, [X7, X30,LSL #3]

  (3401) 0x4f71c0 STR	D21, [X1, X0,LSL #3]

  (3401) 0x4f71c4 ADD	X0, X0, #8

  (3401) 0x4f71c8 LDR	D22, [X16, X30,LSL #3]

  (3401) 0x4f71cc STR	X21, [X2, X30,LSL #3]

  (3401) 0x4f71d0 LDR	X28, [X7, X15,LSL #3]

  (3401) 0x4f71d4 STR	D22, [X1, X30,LSL #3]

  (3401) 0x4f71d8 LDR	D23, [X16, X15,LSL #3]

  (3401) 0x4f71dc STR	X28, [X2, X15,LSL #3]

  (3401) 0x4f71e0 LDR	X25, [X7, X14,LSL #3]

  (3401) 0x4f71e4 STR	D23, [X1, X15,LSL #3]

  (3401) 0x4f71e8 LDR	D24, [X16, X14,LSL #3]

  (3401) 0x4f71ec STR	X25, [X2, X14,LSL #3]

  (3401) 0x4f71f0 LDR	X12, [X7, X11,LSL #3]

  (3401) 0x4f71f4 STR	D24, [X1, X14,LSL #3]

  (3401) 0x4f71f8 LDR	D25, [X16, X11,LSL #3]

  (3401) 0x4f71fc STR	X12, [X2, X11,LSL #3]

  (3401) 0x4f7200 LDR	X10, [X7, X18,LSL #3]

  (3401) 0x4f7204 STR	D25, [X1, X11,LSL #3]

  (3401) 0x4f7208 LDR	D26, [X16, X18,LSL #3]

  (3401) 0x4f720c STR	X10, [X2, X18,LSL #3]

  (3401) 0x4f7210 LDR	X3, [X7, X6,LSL #3]

  (3401) 0x4f7214 STR	D26, [X1, X18,LSL #3]

  (3401) 0x4f7218 LDR	D27, [X16, X6,LSL #3]

  (3401) 0x4f721c STR	X3, [X2, X6,LSL #3]

  (3401) 0x4f7220 LDR	X17, [X7, X4,LSL #3]

  (3401) 0x4f7224 STR	D27, [X1, X6,LSL #3]

  (3401) 0x4f7228 LDR	D28, [X16, X4,LSL #3]

  (3401) 0x4f722c STR	X17, [X2, X4,LSL #3]

  (3401) 0x4f7230 STR	D28, [X1, X4,LSL #3]

  (3401) 0x4f7234 CMP	X13, X0

  (3401) 0x4f7238 B.NE	4f7194

0x4f723c ORR	X0, XZR, X7

0x4f7240 STP	X8, X9, [SP, #208]

0x4f7244 STR	X5, [SP, #264]

0x4f7248 LDR	X21, [SP, #168]

0x4f724c BL	516820

0x4f7250 LDR	X0, [SP, #136]

0x4f7254 STR	XZR, [SP, #136]

0x4f7258 BL	516820

0x4f725c LDP	X8, X9, [SP, #208]

0x4f7260 LDR	X5, [SP, #264]

0x4f7264 B	4f6940

  (3400) 0x4f7268 LDR	D5, [X5, X21,LSL #3]

  (3400) 0x4f726c STR	D5, [X30, X2]

  (3400) 0x4f7270 B	4f7020

  (3400) 0x4f7274 STR	X1, [X7, X13,LSL #3]

  (3400) 0x4f7278 UBFM	X16, X13, #61, #60

  (3400) 0x4f727c ADD	X13, X13, #1

  (3400) 0x4f7280 LDR	X1, [SP, #136]

  (3400) 0x4f7284 STR	D4, [X1, X16]

  (3400) 0x4f7288 B	4f7020

0x4f72b8 SUB	X13, X2, X17

0x4f72bc MOVZ	X1, #8

0x4f72c0 STP	X2, X14, [SP, #264]

0x4f72c4 ORR	X0, XZR, X13

0x4f72c8 STR	X13, [SP, #136]

0x4f72cc STR	X8, [SP, #280]

0x4f72d0 STP	X9, X5, [SP, #304]

0x4f72d4 BL	51674c

0x4f72d8 ORR	X9, XZR, X0

0x4f72dc MOVZ	X1, #8

0x4f72e0 LDR	X0, [SP, #136]

0x4f72e4 STR	X9, [SP, #168]

0x4f72e8 BL	51674c

0x4f72ec LDP	X2, X14, [SP, #264]

0x4f72f0 STR	X0, [SP, #136]

0x4f72f4 LDR	X7, [SP, #168]

0x4f72f8 CMP	X2, #0

0x4f72fc LDP	X9, X5, [SP, #304]

0x4f7300 LDR	X8, [SP, #280]

0x4f7304 B.GT	4f6e5c

0x4f7308 STR	X21, [SP, #168]

0x4f730c LDR	X15, [SP, #200]

0x4f7310 STR	X28, [X15, X14,LSL #3]

0x4f7314 B	4f7040

0x4f738c LDR	X17, [SP, #136]

0x4f7390 MOVZ	X0, #1

0x4f7394 LDR	X16, [X7]

0x4f7398 LDR	D6, [X17]

0x4f739c STR	X16, [X10, X15]

0x4f73a0 STR	D6, [X18, X15]

0x4f73a4 B	4f70f8

0x4f7478 LDR	X16, [SP, #136]

0x4f747c B	4f7194

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 3291 - 3500

--------------------------------------------------------------------------------

3291:          for (ii=ns; ii < ne; ii++)

3292:          {

3293:             row = rows[ii];

3294:             n = ncols[ii];

3295:             /* processor owns the row */

3296:             if (row >= row_partitioning[pstart] && row < row_partitioning[pstart+1])

3297:             {

3298:                row_local = row - row_partitioning[pstart];

3299:                /* compute local row number */

3300:                if (need_aux)

3301:                {

3302:                   local_j = aux_j[row_local];

3303:                   local_data = aux_data[row_local];

3304:    	          space = row_space[row_local];

3305:    	          old_size = row_length[row_local];

3306:    	          size = space - old_size;

3307:    	          if (size < n)

3308:       	          {

3309:       	             size = n - size;

3310:       	             tmp_j = hypre_CTAlloc(HYPRE_Int,size);

3311:       	             tmp_data = hypre_CTAlloc(HYPRE_Complex,size);

3312:       	          }

3313:       	          tmp_indx = 0;

3314:       	          not_found = 1;

3315:       	          size = old_size;

3316:                   for (i=0; i < n; i++)

3317:       	          {

3318:       	             for (j=0; j < old_size; j++)

3319:       	             {

3320:       	                if (local_j[j] == cols[indx])

3321:       	                {

3322:                            local_data[j] = values[indx];

3323:       		           not_found = 0;

3324:       		           break;

3325:       	                }

3326:       	             }

3327:       	             if (not_found)

3328:       	             {

3329:       	                if (size < space)

3330:       	                {

3331:       	                   local_j[size] = cols[indx];

3332:       	                   local_data[size++] = values[indx];

3333:       	                }

3334:       	                else

3335:       	                {

3336:       	                   tmp_j[tmp_indx] = cols[indx];

3337:       	                   tmp_data[tmp_indx++] = values[indx];

3338:       	                }

3339:       	             }

3340:       	             not_found = 1;

3341:         	     indx++;

3342:       	          }

3343:

3344:                   row_length[row_local] = size+tmp_indx;

3345:

3346:                   if (tmp_indx)

3347:                   {

3348:    	             aux_j[row_local] = hypre_TReAlloc(aux_j[row_local],HYPRE_Int,

3349:                                                     size+tmp_indx);

3350:    	             aux_data[row_local] = hypre_TReAlloc(aux_data[row_local],

3351:                                                        HYPRE_Complex,size+tmp_indx);

3352:                      row_space[row_local] = size+tmp_indx;

3353:                      local_j = aux_j[row_local];

[...]

3359:    	          for (i=0; i < tmp_indx; i++)

3360:    	          {

3361:    	             local_j[cnt] = tmp_j[i];

3362:    	             local_data[cnt++] = tmp_data[i];

3363: 	          }

3364:

3365: 	          if (tmp_j)

3366: 	          {

3367: 	             hypre_TFree(tmp_j);

3368: 	             hypre_TFree(tmp_data);

[...]

3376: 	          offd_indx = hypre_AuxParCSRMatrixIndxOffd(aux_matrix)[row_local];

[...]

3446:                                  hypre_printf("Error in row %d ! Too many elements !\n",

[...]

3466:                indx +=  n;

3467:    	       if (aux_matrix)

3468:                {

3469:                   col_indx = 0;

3470:                   for (i=0; i < off_proc_i_indx; i=i+2)

3471:                   {

3472: 	             row_len = off_proc_i[i+1];

3473: 	             if (off_proc_i[i] == row)

3474: 		     {

3475: 		        for (j=0; j < n; j++)

3476: 		        {

3477: 			   cnt1 = col_indx;

3478: 			   for (k=0; k < row_len; k++)

3479: 			   {

3480: 			      if (off_proc_j[cnt1] == cols[j])

3481: 			      {

3482:                                  off_proc_j[cnt1++] = -1;

3483:                		         /*cancel_indx++;*/

3484: 	                         offproc_cnt[my_thread_num]++;

[...]

3500: 		        col_indx += row_len;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	6.52
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.00
Bottlenecks	P10,
Function	hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1
Source	IJMatrix_parcsr.c:3291-3313,IJMatrix_parcsr.c:3316-3316,IJMatrix_parcsr.c:3344-3353,IJMatrix_parcsr.c:3359-3362,IJMatrix_parcsr.c:3365-3368,IJMatrix_parcsr.c:3376-3376,IJMatrix_parcsr.c:3446-3446,IJMatrix_parcsr.c:3466-3470
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	35.83
CQA cycles if no scalar integer	5.50
CQA cycles if FP arith vectorized	35.83
CQA cycles if fully vectorized	8.96
Front-end cycles	23.63
DIV/SQRT cycles	15.50
P0 cycles	15.50
P1 cycles	14.25
P2 cycles	14.25
P3 cycles	14.25
P4 cycles	14.25
P5 cycles	3.50
P6 cycles	3.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	35.83
P10 cycles	35.50
P11 cycles	35.67
P12 cycles	15.00
P13 cycles	15.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	189.00
Nb uops	189.00
Nb loads	NA
Nb stores	37.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	27.24
Bytes prefetched	0.00
Bytes loaded	624.00
Bytes stored	352.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	6.52
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.00
Bottlenecks	P10,
Function	hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1
Source	IJMatrix_parcsr.c:3291-3313,IJMatrix_parcsr.c:3316-3316,IJMatrix_parcsr.c:3344-3353,IJMatrix_parcsr.c:3359-3362,IJMatrix_parcsr.c:3365-3368,IJMatrix_parcsr.c:3376-3376,IJMatrix_parcsr.c:3446-3446,IJMatrix_parcsr.c:3466-3470
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	35.83
CQA cycles if no scalar integer	5.50
CQA cycles if FP arith vectorized	35.83
CQA cycles if fully vectorized	8.96
Front-end cycles	23.63
DIV/SQRT cycles	15.50
P0 cycles	15.50
P1 cycles	14.25
P2 cycles	14.25
P3 cycles	14.25
P4 cycles	14.25
P5 cycles	3.50
P6 cycles	3.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	35.83
P10 cycles	35.50
P11 cycles	35.67
P12 cycles	15.00
P13 cycles	15.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	189.00
Nb uops	189.00
Nb loads	NA
Nb stores	37.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	27.24
Bytes prefetched	0.00
Bytes loaded	624.00
Bytes stored	352.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1
Source file and lines	IJMatrix_parcsr.c:3291-3500
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3291-3353,3359-3368,3376,3446,3466-3484,3500.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3291-3313,3316,3344-3353,3359-3362,3365-3368,3376,3446,3466-3470.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 35.83 to 5.50 cycles (6.52x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 35.83 to 8.96 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 35.83 to 3.00 cycles (11.94x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 624 bytes. The binary loop is storing 352 bytes.

General properties

nb instructions	189
loop length	756
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

23.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	15.50	15.50	14.25	14.25	14.25	14.25	3.50	3.50	0.00	0.00	35.83	35.50	35.67	15.00	15.00
cycles	15.50	15.50	14.25	14.25	14.25	14.25	3.50	3.50	0.00	0.00	35.83	35.50	35.67	15.00	15.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.63
Overall L1	35.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 35.83 cycles. At this rate:

18% of peak load performance is reached (17.41 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (9.82 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4f6940

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X11, [SP, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [SP, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X11, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X14, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X25, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LT 4f6b14 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x84c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X16, [SP, #144]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X25, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 4f6b14 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x84c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X14, X25, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X18, [SP, #192]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X6, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CBNZ X18, 4f6e20 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb58>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X7, [SP, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X26, X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X7, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 4f66ac <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x3e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [SP, #128]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X21, X21, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CBZ X18, 4f6940 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x678>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [SP, #152]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 4f6940 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x678>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X14, X27, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X6, [SP, #160]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X7, X10, [SP, #176]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 4f6b4c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x884>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [SP, #240]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [SP, #248]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X1, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X0, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X11, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [SP, #256]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X17, X30, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STP X12, X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X25, [X4, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GT 4f72b8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xff0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 4f6940 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x678>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X3, X21, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X20, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X11, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X3, [SP, #168]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [SP, #216]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X14, [SP, #208]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X0, X14, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X21, X11, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X20, [SP, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X21, [X0, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBNZ X13, 4f704c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xd84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBNZ X7, 4f723c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xf74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X21, [SP, #168]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4f6940 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x678>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X28, [SP, #256]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X25, X21, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STP X14, X7, [SP, #208]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X11, X13, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X28, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #280]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X9, X5, [SP, #304]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 51678c <hypre_ReAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X1, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X8, [SP, #208]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X7, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X25, [SP, #248]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X25, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X7, [X28, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 51678c <hypre_ReAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X6, X7, [SP, #208]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X18, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP X4, X13, [SP, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X9, X5, [SP, #304]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
UBFM X15, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ANDS X11, X13, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
ADD X1, X18, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X12, [SP, #240]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X28, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X18, [X25, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #280]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X21, [X12, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X2, X10, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.EQ 4f7478 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x11b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f7170 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xea8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f7158 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xe90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X11, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f7140 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xe78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X11, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f7128 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xe60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X11, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f7110 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xe48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X11, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 4f738c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x10c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X30, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D7, [X30, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR X3, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D7, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X21, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D16, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR X14, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D16, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X25, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D17, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR X28, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D17, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D18, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR X18, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D18, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X4, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D19, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR X12, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D19, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X3, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D20, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ORR X16, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X10, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D20, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f723c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xf74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STP X8, X9, [SP, #208]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X5, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [SP, #168]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 516820 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 516820 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [SP, #208]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X5, [SP, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4f6940 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x678>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X13, X2, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STP X2, X14, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X0, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X13, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP, #280]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X9, X5, [SP, #304]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 51674c <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X9, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X0, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X9, [SP, #168]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 51674c <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X2, X14, [SP, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X0, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X7, [SP, #168]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
LDP X9, X5, [SP, #304]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X8, [SP, #280]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.GT 4f6e5c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X21, [SP, #168]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X28, [X15, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4f7040 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xd78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X17, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X16, [X7]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D6, [X17]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR X16, [X10, X15]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D6, [X18, X15]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
B 4f70f8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xe30>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X16, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4f7194 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xecc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1
Source file and lines	IJMatrix_parcsr.c:3291-3500
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 35.83 to 5.50 cycles (6.52x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 35.83 to 3.00 cycles (11.94x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 624 bytes. The binary loop is storing 352 bytes.

General properties

nb instructions	189
loop length	756
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

23.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	15.50	15.50	14.25	14.25	14.25	14.25	3.50	3.50	0.00	0.00	35.83	35.50	35.67	15.00	15.00
cycles	15.50	15.50	14.25	14.25	14.25	14.25	3.50	3.50	0.00	0.00	35.83	35.50	35.67	15.00	15.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.63
Overall L1	35.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 35.83 cycles. At this rate:

18% of peak load performance is reached (17.41 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (9.82 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4f6940

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X11, [SP, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [SP, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X11, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X14, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X25, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LT 4f6b14 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x84c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X16, [SP, #144]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X25, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 4f6b14 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x84c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X14, X25, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X18, [SP, #192]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X6, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CBNZ X18, 4f6e20 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb58>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X7, [SP, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X26, X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X7, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 4f66ac <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x3e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [SP, #128]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X21, X21, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CBZ X18, 4f6940 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x678>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [SP, #152]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 4f6940 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x678>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X14, X27, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X6, [SP, #160]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X7, X10, [SP, #176]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 4f6b4c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x884>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [SP, #240]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [SP, #248]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X1, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X0, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X11, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [SP, #256]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X17, X30, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STP X12, X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X25, [X4, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GT 4f72b8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xff0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 4f6940 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x678>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X3, X21, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X20, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X11, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X3, [SP, #168]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [SP, #216]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X14, [SP, #208]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X0, X14, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X21, X11, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X20, [SP, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X21, [X0, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBNZ X13, 4f704c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xd84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBNZ X7, 4f723c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xf74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X21, [SP, #168]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4f6940 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x678>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X28, [SP, #256]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X25, X21, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STP X14, X7, [SP, #208]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X11, X13, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X28, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #280]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X9, X5, [SP, #304]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 51678c <hypre_ReAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X1, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X8, [SP, #208]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X7, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X25, [SP, #248]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X25, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X7, [X28, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 51678c <hypre_ReAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X6, X7, [SP, #208]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X18, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP X4, X13, [SP, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X9, X5, [SP, #304]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
UBFM X15, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ANDS X11, X13, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
ADD X1, X18, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X12, [SP, #240]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X28, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X18, [X25, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #280]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X21, [X12, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X2, X10, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.EQ 4f7478 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x11b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f7170 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xea8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f7158 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xe90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X11, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f7140 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xe78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X11, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f7128 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xe60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X11, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f7110 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xe48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X11, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 4f738c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x10c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X30, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D7, [X30, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR X3, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D7, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X21, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D16, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR X14, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D16, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X25, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D17, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR X28, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D17, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D18, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR X18, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D18, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X4, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D19, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR X12, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D19, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X3, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D20, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ORR X16, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X10, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D20, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4f723c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xf74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STP X8, X9, [SP, #208]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X5, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [SP, #168]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 516820 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 516820 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [SP, #208]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X5, [SP, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4f6940 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x678>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X13, X2, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STP X2, X14, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X0, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X13, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP, #280]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X9, X5, [SP, #304]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 51674c <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X9, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X0, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X9, [SP, #168]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 51674c <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X2, X14, [SP, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X0, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X7, [SP, #168]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
LDP X9, X5, [SP, #304]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X8, [SP, #280]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.GT 4f6e5c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X21, [SP, #168]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X28, [X15, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4f7040 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xd78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X17, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X16, [X7]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D6, [X17]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR X16, [X10, X15]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR D6, [X18, X15]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
B 4f70f8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xe30>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X16, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4f7194 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xecc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code