OV - exec - Loop 3374

    (3376) 0x4f4d40 LDR	X0, [X10, X30,LSL #3]

    (3376) 0x4f4d44 LDR	X12, [X5, X30,LSL #3]

    (3376) 0x4f4d48 UBFM	X4, X0, #61, #60

    (3376) 0x4f4d4c ADD	X8, X7, X4

    (3376) 0x4f4d50 ADD	X13, X3, X4

    (3376) 0x4f4d54 CMP	X0, X12

    (3376) 0x4f4d58 B.GE	4f4d84

  (3375) 0x4f4d5c HINT	#0

  (3375) 0x4f4d60 LDR	X14, [X3, X0,LSL #3]

  (3375) 0x4f4d64 SUB	X15, X14, X6

  (3375) 0x4f4d68 STR	X15, [X3, X0,LSL #3]

  (3375) 0x4f4d6c CMP	X30, X15

  (3375) 0x4f4d70 B.EQ	4f4da0

  (3375) 0x4f4d74 LDR	X16, [X5, X30,LSL #3]

  (3375) 0x4f4d78 ADD	X0, X0, #1

  (3375) 0x4f4d7c CMP	X16, X0

  (3375) 0x4f4d80 B.GT	4f4d60

    (3376) 0x4f4d84 ADD	X30, X30, #1

    (3376) 0x4f4d88 CMP	X11, X30

    (3376) 0x4f4d8c B.NE	4f4d40

0x4f4da0 LDR	D1, [X7, X0,LSL #3]

0x4f4da4 LDR	D0, [X8]

0x4f4da8 LDR	X17, [X13]

0x4f4dac STR	D1, [X8]

0x4f4db0 STR	D0, [X7, X0,LSL #3]

0x4f4db4 STR	X17, [X3, X0,LSL #3]

0x4f4db8 ADD	X0, X0, #1

0x4f4dbc STR	X30, [X13]

0x4f4dc0 LDR	X18, [X5, X30,LSL #3]

0x4f4dc4 CMP	X18, X0

0x4f4dc8 B.GT	4f4d60

0x4f4dcc ADD	X30, X30, #1

0x4f4dd0 CMP	X11, X30

0x4f4dd4 B.NE	4f4d40

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 2802 - 2812

--------------------------------------------------------------------------------

2802:    	    j0 = diag_i[i];

2803:    	    for (j=j0; j < diag_i[i+1]; j++)

2804:    	    {

2805:    	       diag_j[j] -= col_0;

2806:    	       if (diag_j[j] == i)

2807:    	       {

2808:    	          temp = diag_data[j0];

2809:    	          diag_data[j0] = diag_data[j];

2810:    	          diag_data[j] = temp;

2811:    	          diag_j[j] = diag_j[j0];

2812:    	          diag_j[j0] = i;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	2.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.52
Bottlenecks	P10, P11, P12,
Function	hypre_IJMatrixAssembleParCSR._omp_fn.1
Source	IJMatrix_parcsr.c:2803-2803,IJMatrix_parcsr.c:2808-2812
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.67
CQA cycles if no scalar integer	1.33
CQA cycles if FP arith vectorized	2.67
CQA cycles if fully vectorized	0.67
Front-end cycles	1.75
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.67
P10 cycles	2.67
P11 cycles	2.67
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	14.00
Nb uops	14.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	2.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.52
Bottlenecks	P10, P11, P12,
Function	hypre_IJMatrixAssembleParCSR._omp_fn.1
Source	IJMatrix_parcsr.c:2803-2803,IJMatrix_parcsr.c:2808-2812
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.67
CQA cycles if no scalar integer	1.33
CQA cycles if FP arith vectorized	2.67
CQA cycles if fully vectorized	0.67
Front-end cycles	1.75
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.67
P10 cycles	2.67
P11 cycles	2.67
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	14.00
Nb uops	14.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_IJMatrixAssembleParCSR._omp_fn.1
Source file and lines	IJMatrix_parcsr.c:2802-2812
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:2802-2812.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:2803,2808-2812.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.67 to 1.33 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 2.67 to 0.67 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes. The binary loop is storing 32 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	1.00	1.00	1.00	1.00	1.00	1.00	0.00	0.00	2.67	2.67	2.67	1.00	1.00
cycles	1.00	1.00	1.00	1.00	1.00	1.00	1.00	1.00	0.00	0.00	2.67	2.67	2.67	1.00	1.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.75
Overall L1	2.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.67 cycles. At this rate:

12% of peak load performance is reached (12.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
24% of peak store performance is reached (12.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4f4da0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR D1, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D0, [X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X17, [X13]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR D1, [X8]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
STR D0, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
STR X17, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X30, [X13]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X5, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X18, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GT 4f4d60 <hypre_IJMatrixAssembleParCSR._omp_fn.1+0x7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X30, X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X11, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 4f4d40 <hypre_IJMatrixAssembleParCSR._omp_fn.1+0x5c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_IJMatrixAssembleParCSR._omp_fn.1
Source file and lines	IJMatrix_parcsr.c:2802-2812
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:2802-2812.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:2803,2808-2812.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.67 to 1.33 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 2.67 to 0.67 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes. The binary loop is storing 32 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	1.00	1.00	1.00	1.00	1.00	1.00	0.00	0.00	2.67	2.67	2.67	1.00	1.00
cycles	1.00	1.00	1.00	1.00	1.00	1.00	1.00	1.00	0.00	0.00	2.67	2.67	2.67	1.00	1.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.75
Overall L1	2.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.67 cycles. At this rate:

12% of peak load performance is reached (12.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
24% of peak store performance is reached (12.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4f4da0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR D1, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D0, [X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X17, [X13]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR D1, [X8]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
STR D0, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
STR X17, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X30, [X13]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X5, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X18, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GT 4f4d60 <hypre_IJMatrixAssembleParCSR._omp_fn.1+0x7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X30, X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X11, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 4f4d40 <hypre_IJMatrixAssembleParCSR._omp_fn.1+0x5c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code