OV - exec - Loop 317

	Loop Id: 317	Module: exec	Source: par_coarse_parms.c:94-96	Coverage: 0.01%

0x42aa98 LDR	X17, [X10]    [1]

0x42aa9c CMP	X17, #1

0x42aaa0 B.NE	42aaac

0x42aaa4 ADD	X0, X0, #1

0x42aaa8 ORR	W1, WZR, W17

0x42aaac LDR	X18, [X10, #8]    [1]

0x42aab0 ADD	X30, X10, #8

0x42aab4 CMP	X18, #1

0x42aab8 B.NE	42aac4

0x42aabc ADD	X0, X0, #1

0x42aac0 ORR	W1, WZR, W18

0x42aac4 LDR	X7, [X30, #8]    [2]

0x42aac8 CMP	X7, #1

0x42aacc B.NE	42aad8

0x42aad0 ADD	X0, X0, #1

0x42aad4 ORR	W1, WZR, W7

0x42aad8 LDR	X8, [X30, #16]    [2]

0x42aadc CMP	X8, #1

0x42aae0 B.NE	42aaec

0x42aae4 ADD	X0, X0, #1

0x42aae8 ORR	W1, WZR, W8

0x42aaec LDR	X2, [X30, #24]    [2]

0x42aaf0 CMP	X2, #1

0x42aaf4 B.NE	42ab00

0x42aaf8 ADD	X0, X0, #1

0x42aafc ORR	W1, WZR, W2

0x42ab00 LDR	X3, [X30, #32]    [2]

0x42ab04 CMP	X3, #1

0x42ab08 B.NE	42ab14

0x42ab0c ADD	X0, X0, #1

0x42ab10 ORR	W1, WZR, W3

0x42ab14 LDR	X5, [X30, #40]    [2]

0x42ab18 CMP	X5, #1

0x42ab1c B.NE	42ab28

0x42ab20 ADD	X0, X0, #1

0x42ab24 ORR	W1, WZR, W5

0x42ab28 LDR	X6, [X30, #48]    [2]

0x42ab2c CMP	X6, #1

0x42ab30 B.NE	42ab3c

0x42ab34 ADD	X0, X0, #1

0x42ab38 ORR	W1, WZR, W6

0x42ab3c ADD	X10, X30, #56

0x42ab40 CMP	X4, X10

0x42ab44 B.NE	42aa98

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarse_parms.c: 94 - 96

--------------------------------------------------------------------------------

94:    for (i=0; i < local_num_variables; i++)

95:    {

96:       if (CF_marker[i] == 1) local_coarse_size++;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.02
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.23
Bottlenecks	P2, P3, P4, P5,
Function	hypre_BoomerAMGCoarseParms
Source	par_coarse_parms.c:94-96
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.75
CQA cycles if no scalar integer	6.75
CQA cycles if FP arith vectorized	6.75
CQA cycles if fully vectorized	1.34
Front-end cycles	5.50
DIV/SQRT cycles	4.50
P0 cycles	4.50
P1 cycles	6.75
P2 cycles	6.75
P3 cycles	6.75
P4 cycles	6.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.67
P10 cycles	2.67
P11 cycles	2.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	44.00
Nb uops	44.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.48
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	20.83
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.02
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.23
Bottlenecks	P2, P3, P4, P5,
Function	hypre_BoomerAMGCoarseParms
Source	par_coarse_parms.c:94-96
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.75
CQA cycles if no scalar integer	6.75
CQA cycles if FP arith vectorized	6.75
CQA cycles if fully vectorized	1.34
Front-end cycles	5.50
DIV/SQRT cycles	4.50
P0 cycles	4.50
P1 cycles	6.75
P2 cycles	6.75
P3 cycles	6.75
P4 cycles	6.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.67
P10 cycles	2.67
P11 cycles	2.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	44.00
Nb uops	44.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.48
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	20.83
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGCoarseParms
Source file and lines	par_coarse_parms.c:94-96
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarse_parms.c:94-96.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 256 paths individually, rerun with max-paths=256
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 256 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 20% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 6.75 to 1.34 cycles (5.02x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes.

General properties

nb instructions	44
loop length	176
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	6.75	6.75	6.75	6.75	0.00	0.00	0.00	0.00	2.67	2.67	2.67	0.00	0.00
cycles	4.50	4.50	6.75	6.75	6.75	6.75	0.00	0.00	0.00	0.00	2.67	2.67	2.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.50
Overall L1	6.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.75 cycles. At this rate:

9% of peak load performance is reached (9.48 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 42aa98

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDR X17, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.NE 42aaac <hypre_BoomerAMGCoarseParms+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W1, WZR, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X18, [X10, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X30, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.NE 42aac4 <hypre_BoomerAMGCoarseParms+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W1, WZR, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X7, [X30, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.NE 42aad8 <hypre_BoomerAMGCoarseParms+0x178>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W1, WZR, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X8, [X30, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.NE 42aaec <hypre_BoomerAMGCoarseParms+0x18c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W1, WZR, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X2, [X30, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.NE 42ab00 <hypre_BoomerAMGCoarseParms+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W1, WZR, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X3, [X30, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.NE 42ab14 <hypre_BoomerAMGCoarseParms+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W1, WZR, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X5, [X30, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.NE 42ab28 <hypre_BoomerAMGCoarseParms+0x1c8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W1, WZR, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X6, [X30, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.NE 42ab3c <hypre_BoomerAMGCoarseParms+0x1dc>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W1, WZR, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X10, X30, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X4, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.NE 42aa98 <hypre_BoomerAMGCoarseParms+0x138>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	hypre_BoomerAMGCoarseParms
Source file and lines	par_coarse_parms.c:94-96
Module	exec

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 256 paths individually, rerun with max-paths=256
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes.

General properties

nb instructions	44
loop length	176
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	6.75	6.75	6.75	6.75	0.00	0.00	0.00	0.00	2.67	2.67	2.67	0.00	0.00
cycles	4.50	4.50	6.75	6.75	6.75	6.75	0.00	0.00	0.00	0.00	2.67	2.67	2.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.50
Overall L1	6.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.75 cycles. At this rate:

9% of peak load performance is reached (9.48 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 42aa98

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDR X17, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.NE 42aaac <hypre_BoomerAMGCoarseParms+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W1, WZR, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X18, [X10, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X30, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.NE 42aac4 <hypre_BoomerAMGCoarseParms+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W1, WZR, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X7, [X30, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.NE 42aad8 <hypre_BoomerAMGCoarseParms+0x178>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W1, WZR, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X8, [X30, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.NE 42aaec <hypre_BoomerAMGCoarseParms+0x18c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W1, WZR, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X2, [X30, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.NE 42ab00 <hypre_BoomerAMGCoarseParms+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W1, WZR, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X3, [X30, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.NE 42ab14 <hypre_BoomerAMGCoarseParms+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W1, WZR, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X5, [X30, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.NE 42ab28 <hypre_BoomerAMGCoarseParms+0x1c8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W1, WZR, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X6, [X30, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.NE 42ab3c <hypre_BoomerAMGCoarseParms+0x1dc>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W1, WZR, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X10, X30, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X4, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.NE 42aa98 <hypre_BoomerAMGCoarseParms+0x138>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code