OV - exec - Loop 2970

0x4db18c LDR	X9, [SP, #152]

0x4db190 ORR	X1, XZR, X20

0x4db194 ORR	X3, XZR, X25

0x4db198 CBNZ	X9, 4db274

0x4db19c LDP	X15, X30, [X16]

0x4db1a0 CMP	X15, X30

0x4db1a4 B.GE	4db224

0x4db1a8 LDP	X18, X9, [SP, #160]

0x4db1ac LDP	X28, X30, [SP, #176]

  (2975) 0x4db1b0 LDR	X17, [X28, X15,LSL #3]

  (2975) 0x4db1b4 LDR	D17, [X30, X15,LSL #3]

  (2975) 0x4db1b8 UBFM	X8, X17, #61, #60

  (2975) 0x4db1bc LDR	X2, [X27, X17,LSL #3]

  (2975) 0x4db1c0 ADD	X7, X8, #8

  (2975) 0x4db1c4 LDR	X6, [X27, X7]

  (2975) 0x4db1c8 ADD	X8, X27, X7

  (2975) 0x4db1cc CMP	X2, X6

  (2975) 0x4db1d0 B.GE	4db210

  (2975) 0x4db1d4 HINT	#0

  (2975) 0x4db1d8 HINT	#0

  (2975) 0x4db1dc HINT	#0

    (2978) 0x4db1e0 LDR	X4, [X21, X2,LSL #3]

    (2978) 0x4db1e4 LDR	D18, [X22, X2,LSL #3]

    (2978) 0x4db1e8 LDR	X5, [X0, X4,LSL #3]

    (2978) 0x4db1ec FMUL	D19, D17, D18

    (2978) 0x4db1f0 CMP	X5, X20

    (2978) 0x4db1f4 B.LT	4db35c

    (2978) 0x4db1f8 LDR	D20, [X19, X5,LSL #3]

    (2978) 0x4db1fc ADD	X2, X2, #1

    (2978) 0x4db200 FADD	D21, D20, D19

    (2978) 0x4db204 STR	D21, [X19, X5,LSL #3]

    (2978) 0x4db208 CMP	X6, X2

    (2978) 0x4db20c B.GT	4db1e0

  (2975) 0x4db210 CBNZ	X18, 4db380

  (2975) 0x4db214 LDR	X17, [X16, #8]

  (2975) 0x4db218 ADD	X15, X15, #1

  (2975) 0x4db21c CMP	X17, X15

  (2975) 0x4db220 B.GT	4db1b0

0x4db224 LDP	X20, X25, [SP, #120]

0x4db228 ADD	X16, X16, #8

0x4db22c LDR	X28, [SP, #136]

0x4db230 ADD	X18, X20, #1

0x4db234 ADD	X9, X25, #8

0x4db238 STP	X18, X9, [SP, #120]

0x4db23c CMP	X28, X18

0x4db240 B.EQ	4db474

0x4db244 LDR	X28, [SP, #144]

0x4db248 ORR	X25, XZR, X3

0x4db24c ORR	X20, XZR, X1

0x4db250 CBZ	X28, 4db18c

0x4db274 LDR	X30, [SP, #128]

0x4db278 LDP	X17, X6, [X30]

0x4db27c CMP	X17, X6

0x4db280 B.GE	4db19c

0x4db284 STP	X14, X21, [SP, #208]

0x4db288 STR	X27, [SP, #224]

0x4db28c LDP	X15, X18, [SP, #232]

0x4db290 LDP	X21, X27, [SP, #248]

0x4db294 LDP	X28, X8, [SP, #264]

0x4db298 STP	X12, X13, [SP, #192]

0x4db29c LDR	X9, [SP, #280]

  (2971) 0x4db2a0 LDR	X14, [X21, X17,LSL #3]

  (2971) 0x4db2a4 LDR	D1, [X27, X17,LSL #3]

  (2971) 0x4db2a8 UBFM	X12, X14, #61, #60

  (2971) 0x4db2ac LDR	X2, [X15, X14,LSL #3]

  (2971) 0x4db2b0 ADD	X12, X12, #8

  (2971) 0x4db2b4 LDR	X7, [X15, X12]

  (2971) 0x4db2b8 ADD	X13, X15, X12

  (2971) 0x4db2bc CMP	X2, X7

  (2971) 0x4db2c0 B.GE	4db2f8

    (2973) 0x4db2c4 LDR	X5, [X28, X2,LSL #3]

    (2973) 0x4db2c8 LDR	D0, [X8, X2,LSL #3]

    (2973) 0x4db2cc ADD	X6, X26, X5

    (2973) 0x4db2d0 LDR	X4, [X0, X6,LSL #3]

    (2973) 0x4db2d4 FMUL	D3, D1, D0

    (2973) 0x4db2d8 CMP	X4, X25

    (2973) 0x4db2dc B.LT	4db450

    (2973) 0x4db2e0 LDR	D2, [X23, X4,LSL #3]

    (2973) 0x4db2e4 ADD	X2, X2, #1

    (2973) 0x4db2e8 FADD	D4, D2, D3

    (2973) 0x4db2ec STR	D4, [X23, X4,LSL #3]

    (2973) 0x4db2f0 CMP	X7, X2

    (2973) 0x4db2f4 B.GT	4db2c4

  (2971) 0x4db2f8 LDR	X5, [X18, X14,LSL #3]

  (2971) 0x4db2fc ADD	X14, X18, X12

  (2971) 0x4db300 LDR	X6, [X18, X12]

  (2971) 0x4db304 CMP	X5, X6

  (2971) 0x4db308 B.GE	4db33c

    (2972) 0x4db30c LDR	X12, [X9, X5,LSL #3]

    (2972) 0x4db310 LDR	D5, [X10, X5,LSL #3]

    (2972) 0x4db314 LDR	X13, [X0, X12,LSL #3]

    (2972) 0x4db318 FMUL	D6, D1, D5

    (2972) 0x4db31c CMP	X13, X20

    (2972) 0x4db320 B.LT	4db41c

    (2972) 0x4db324 LDR	D7, [X19, X13,LSL #3]

    (2972) 0x4db328 ADD	X5, X5, #1

    (2972) 0x4db32c FADD	D16, D7, D6

    (2972) 0x4db330 STR	D16, [X19, X13,LSL #3]

    (2972) 0x4db334 CMP	X6, X5

    (2972) 0x4db338 B.GT	4db30c

  (2971) 0x4db33c LDR	X4, [X30, #8]

  (2971) 0x4db340 ADD	X17, X17, #1

  (2971) 0x4db344 CMP	X4, X17

  (2971) 0x4db348 B.GT	4db2a0

0x4db34c LDP	X12, X13, [SP, #192]

0x4db350 LDP	X14, X21, [SP, #208]

0x4db354 LDR	X27, [SP, #224]

0x4db358 B	4db19c

    (2978) 0x4db35c STR	X1, [X0, X4,LSL #3]

    (2978) 0x4db360 ADD	X2, X2, #1

    (2978) 0x4db364 STR	D19, [X19, X1,LSL #3]

    (2978) 0x4db368 STR	X4, [X24, X1,LSL #3]

    (2978) 0x4db36c ADD	X1, X1, #1

    (2978) 0x4db370 LDR	X6, [X8]

    (2978) 0x4db374 CMP	X2, X6

    (2978) 0x4db378 B.LT	4db1e0

  (2975) 0x4db37c CBZ	X18, 4db214

  (2975) 0x4db380 LDR	X2, [X9, X17,LSL #3]

  (2975) 0x4db384 ADD	X17, X9, X7

  (2975) 0x4db388 LDR	X7, [X9, X7]

  (2975) 0x4db38c CMP	X2, X7

  (2975) 0x4db390 B.GE	4db214

  (2975) 0x4db394 HINT	#0

  (2975) 0x4db398 HINT	#0

  (2975) 0x4db39c HINT	#0

    (2976) 0x4db3a0 LDR	X8, [X13, X2,LSL #3]

    (2976) 0x4db3a4 LDR	D22, [X14, X2,LSL #3]

    (2976) 0x4db3a8 LDR	X5, [X12, X8,LSL #3]

    (2976) 0x4db3ac FMUL	D23, D17, D22

    (2976) 0x4db3b0 ADD	X6, X26, X5

    (2976) 0x4db3b4 LDR	X4, [X0, X6,LSL #3]

    (2976) 0x4db3b8 CMP	X4, X25

    (2976) 0x4db3bc B.LT	4db3f8

    (2977) 0x4db3c0 LDR	D24, [X23, X4,LSL #3]

    (2977) 0x4db3c4 ADD	X2, X2, #1

    (2977) 0x4db3c8 FADD	D25, D24, D23

    (2977) 0x4db3cc STR	D25, [X23, X4,LSL #3]

    (2977) 0x4db3d0 CMP	X7, X2

    (2977) 0x4db3d4 B.LE	4db214

    (2977) 0x4db3d8 LDR	X8, [X13, X2,LSL #3]

    (2977) 0x4db3dc LDR	D22, [X14, X2,LSL #3]

    (2977) 0x4db3e0 LDR	X5, [X12, X8,LSL #3]

    (2977) 0x4db3e4 FMUL	D23, D17, D22

    (2977) 0x4db3e8 ADD	X6, X26, X5

    (2977) 0x4db3ec LDR	X4, [X0, X6,LSL #3]

    (2977) 0x4db3f0 CMP	X4, X25

    (2977) 0x4db3f4 B.GE	4db3c0

    (2976) 0x4db3f8 STR	X3, [X0, X6,LSL #3]

    (2976) 0x4db3fc ADD	X2, X2, #1

    (2976) 0x4db400 STR	D23, [X23, X3,LSL #3]

    (2976) 0x4db404 STR	X5, [X11, X3,LSL #3]

    (2976) 0x4db408 ADD	X3, X3, #1

    (2976) 0x4db40c LDR	X7, [X17]

    (2976) 0x4db410 CMP	X2, X7

    (2976) 0x4db414 B.LT	4db3a0

  (2975) 0x4db418 B	4db214

    (2972) 0x4db41c STR	X1, [X0, X12,LSL #3]

    (2972) 0x4db420 ADD	X5, X5, #1

    (2972) 0x4db424 STR	D6, [X19, X1,LSL #3]

    (2972) 0x4db428 STR	X12, [X24, X1,LSL #3]

    (2972) 0x4db42c ADD	X1, X1, #1

    (2972) 0x4db430 LDR	X6, [X14]

    (2972) 0x4db434 CMP	X5, X6

    (2972) 0x4db438 B.LT	4db30c

  (2971) 0x4db43c LDR	X4, [X30, #8]

  (2971) 0x4db440 ADD	X17, X17, #1

  (2971) 0x4db444 CMP	X4, X17

  (2971) 0x4db448 B.GT	4db2a0

0x4db44c B	4db34c

    (2973) 0x4db450 STR	X3, [X0, X6,LSL #3]

    (2973) 0x4db454 ADD	X2, X2, #1

    (2973) 0x4db458 STR	D3, [X23, X3,LSL #3]

    (2973) 0x4db45c STR	X5, [X11, X3,LSL #3]

    (2973) 0x4db460 ADD	X3, X3, #1

    (2973) 0x4db464 LDR	X7, [X13]

    (2973) 0x4db468 CMP	X2, X7

    (2973) 0x4db46c B.LT	4db2c4

  (2971) 0x4db470 B	4db2f8

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 865 - 989

--------------------------------------------------------------------------------

865:     for (i1 = ns; i1 < ne; i1++)

[...]

874:       if ( allsquare )

[...]

886:       if (num_cols_offd_A)

887:       {

888:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

889:          {

890:             i2 = A_offd_j[jj2];

891:             a_entry = A_offd_data[jj2];

[...]

897:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

898:             {

899:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

907:                if (B_marker[i3] < jj_row_begin_offd)

908:                {

909:                   B_marker[i3] = jj_count_offd;

910:                   C_offd_data[jj_count_offd] = a_entry*B_ext_offd_data[jj3];

911:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

912:                   jj_count_offd++;

913:                }

914:                else

915:                   C_offd_data[B_marker[i3]] += a_entry*B_ext_offd_data[jj3];

916:             }

917:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

918:             {

919:                i3 = B_ext_diag_j[jj3];

920:                if (B_marker[i3] < jj_row_begin_diag)

921:                {

922:                   B_marker[i3] = jj_count_diag;

923:                   C_diag_data[jj_count_diag] = a_entry*B_ext_diag_data[jj3];

924:                   C_diag_j[jj_count_diag] = i3;

925:                   jj_count_diag++;

926:                }

927:                else

928:                   C_diag_data[B_marker[i3]] += a_entry*B_ext_diag_data[jj3];

[...]

937:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

938:       {

939:          i2 = A_diag_j[jj2];

940:          a_entry = A_diag_data[jj2];

[...]

946:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

947:          {

948:             i3 = B_diag_j[jj3];

[...]

956:             if (B_marker[i3] < jj_row_begin_diag)

957:             {

958:                B_marker[i3] = jj_count_diag;

959:                C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3];

960:                C_diag_j[jj_count_diag] = i3;

961:                jj_count_diag++;

962:             }

963:             else

964:             {

965:                C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3];

966:             }

967:          }

968:          if (num_cols_offd_B)

969:          {

970:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

971:             {

972:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

980:                if (B_marker[i3] < jj_row_begin_offd)

981:                {

982:                   B_marker[i3] = jj_count_offd;

983:                   C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3];

984:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

985:                   jj_count_offd++;

986:                }

987:                else

988:                {

989:                   C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3];

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.44
Bottlenecks	P10, P11, P12,
Function	hypre_ParMatmul._omp_fn.3
Source	par_csr_matop.c:865-865,par_csr_matop.c:874-874,par_csr_matop.c:886-888,par_csr_matop.c:937-937
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.67
CQA cycles if no scalar integer	6.67
CQA cycles if FP arith vectorized	6.67
CQA cycles if fully vectorized	1.67
Front-end cycles	4.63
DIV/SQRT cycles	3.50
P0 cycles	3.50
P1 cycles	2.50
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	6.67
P10 cycles	6.67
P11 cycles	6.67
P12 cycles	2.00
P13 cycles	2.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	37.00
Nb uops	37.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	39.60
Bytes prefetched	0.00
Bytes loaded	208.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.44
Bottlenecks	P10, P11, P12,
Function	hypre_ParMatmul._omp_fn.3
Source	par_csr_matop.c:865-865,par_csr_matop.c:874-874,par_csr_matop.c:886-888,par_csr_matop.c:937-937
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.67
CQA cycles if no scalar integer	6.67
CQA cycles if FP arith vectorized	6.67
CQA cycles if fully vectorized	1.67
Front-end cycles	4.63
DIV/SQRT cycles	3.50
P0 cycles	3.50
P1 cycles	2.50
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	6.67
P10 cycles	6.67
P11 cycles	6.67
P12 cycles	2.00
P13 cycles	2.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	37.00
Nb uops	37.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	39.60
Bytes prefetched	0.00
Bytes loaded	208.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParMatmul._omp_fn.3
Source file and lines	par_csr_matop.c:865-989
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:865,874,886-891,897-899,907-928,937-940,946-948,956-972,980-989.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:865,874,886-888,937.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.67 to 1.67 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 208 bytes. The binary loop is storing 56 bytes.

General properties

nb instructions	37
loop length	148
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	6.67	6.67	6.67	2.00	2.00
cycles	3.50	3.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	6.67	6.67	6.67	2.00	2.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.63
Overall L1	6.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.67 cycles. At this rate:

32% of peak load performance is reached (31.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (8.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4db19c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X9, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X1, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X3, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CBNZ X9, 4db274 <hypre_ParMatmul._omp_fn.3+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X15, X30, [X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X15, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4db224 <hypre_ParMatmul._omp_fn.3+0x214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X18, X9, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X30, [SP, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X20, X25, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X16, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X28, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X9, X25, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X18, X9, [SP, #120]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X28, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4db474 <hypre_ParMatmul._omp_fn.3+0x464>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X28, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X25, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X20, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CBZ X28, 4db18c <hypre_ParMatmul._omp_fn.3+0x17c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X30, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X17, X6, [X30]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X17, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4db19c <hypre_ParMatmul._omp_fn.3+0x18c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STP X14, X21, [SP, #208]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X27, [SP, #224]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X15, X18, [SP, #232]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X27, [SP, #248]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X8, [SP, #264]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X12, X13, [SP, #192]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [SP, #280]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X12, X13, [SP, #192]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X14, X21, [SP, #208]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X27, [SP, #224]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4db19c <hypre_ParMatmul._omp_fn.3+0x18c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
B 4db34c <hypre_ParMatmul._omp_fn.3+0x33c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_ParMatmul._omp_fn.3
Source file and lines	par_csr_matop.c:865-989
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:865,874,886-891,897-899,907-928,937-940,946-948,956-972,980-989.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:865,874,886-888,937.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.67 to 1.67 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 208 bytes. The binary loop is storing 56 bytes.

General properties

nb instructions	37
loop length	148
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	6.67	6.67	6.67	2.00	2.00
cycles	3.50	3.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	6.67	6.67	6.67	2.00	2.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.63
Overall L1	6.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.67 cycles. At this rate:

32% of peak load performance is reached (31.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (8.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4db19c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X9, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X1, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X3, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CBNZ X9, 4db274 <hypre_ParMatmul._omp_fn.3+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X15, X30, [X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X15, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4db224 <hypre_ParMatmul._omp_fn.3+0x214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X18, X9, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X30, [SP, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X20, X25, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X16, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X28, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X9, X25, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X18, X9, [SP, #120]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X28, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4db474 <hypre_ParMatmul._omp_fn.3+0x464>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X28, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X25, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X20, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CBZ X28, 4db18c <hypre_ParMatmul._omp_fn.3+0x17c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X30, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X17, X6, [X30]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X17, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4db19c <hypre_ParMatmul._omp_fn.3+0x18c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STP X14, X21, [SP, #208]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X27, [SP, #224]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X15, X18, [SP, #232]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X27, [SP, #248]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X8, [SP, #264]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X12, X13, [SP, #192]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [SP, #280]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X12, X13, [SP, #192]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X14, X21, [SP, #208]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X27, [SP, #224]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4db19c <hypre_ParMatmul._omp_fn.3+0x18c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
B 4db34c <hypre_ParMatmul._omp_fn.3+0x33c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code