OV - exec - Loop 2959

0x4da64c LDR	X4, [SP, #144]

0x4da650 ORR	X3, XZR, X20

0x4da654 ORR	X12, XZR, X15

0x4da658 CBNZ	X4, 4da71c

0x4da65c LDR	X18, [X28, X17,LSL #3]

0x4da660 ORR	X4, XZR, X25

0x4da664 LDR	X30, [X28, X16]

0x4da668 CMP	X18, X30

0x4da66c B.GE	4da6d8

  (2964) 0x4da670 LDR	X30, [X6, X18,LSL #3]

  (2964) 0x4da674 UBFM	X25, X30, #61, #60

  (2964) 0x4da678 LDR	X0, [X23, X30,LSL #3]

  (2964) 0x4da67c ADD	X13, X25, #8

  (2964) 0x4da680 LDR	X10, [X23, X13]

  (2964) 0x4da684 ADD	X25, X23, X13

  (2964) 0x4da688 CMP	X0, X10

  (2964) 0x4da68c B.GE	4da6c0

  (2964) 0x4da690 STR	X2, [SP, #104]

  (2964) 0x4da694 HINT	#0

  (2964) 0x4da698 HINT	#0

  (2964) 0x4da69c HINT	#0

    (2967) 0x4da6a0 LDR	X1, [X21, X0,LSL #3]

    (2967) 0x4da6a4 LDR	X2, [X19, X1,LSL #3]

    (2967) 0x4da6a8 CMP	X2, X20

    (2967) 0x4da6ac B.LT	4da7d4

    (2967) 0x4da6b0 ADD	X0, X0, #1

    (2967) 0x4da6b4 CMP	X0, X10

    (2967) 0x4da6b8 B.LT	4da6a0

  (2964) 0x4da6bc LDR	X2, [SP, #104]

  (2964) 0x4da6c0 CBNZ	X5, 4da7f4

  (2964) 0x4da6c4 LDR	X30, [X28, X16]

  (2964) 0x4da6c8 ADD	X18, X18, #1

  (2964) 0x4da6cc CMP	X30, X18

  (2964) 0x4da6d0 B.GT	4da670

0x4da6d4 ORR	X25, XZR, X4

0x4da6d8 LDR	X4, [SP, #160]

0x4da6dc ADD	X16, X16, #8

0x4da6e0 STR	X20, [X4, X17,LSL #3]

0x4da6e4 LDR	X20, [SP, #112]

0x4da6e8 STR	X15, [X2, X17,LSL #3]

0x4da6ec ADD	X17, X17, #1

0x4da6f0 CMP	X20, X17

0x4da6f4 B.EQ	4da8a8

0x4da6f8 ORR	X20, XZR, X3

0x4da6fc LDR	X3, [SP, #136]

0x4da700 ORR	X15, XZR, X12

0x4da704 CBZ	X3, 4da64c

0x4da71c LDR	X18, [X11, X17,LSL #3]

0x4da720 LDR	X10, [X11, X16]

0x4da724 CMP	X18, X10

0x4da728 B.GE	4da65c

0x4da72c ORR	X4, XZR, X5

  (2960) 0x4da730 LDR	X30, [X14, X18,LSL #3]

  (2960) 0x4da734 UBFM	X5, X30, #61, #60

  (2960) 0x4da738 LDR	X1, [X7, X30,LSL #3]

  (2960) 0x4da73c ADD	X10, X5, #8

  (2960) 0x4da740 LDR	X5, [X7, X10]

  (2960) 0x4da744 ADD	X13, X7, X10

  (2960) 0x4da748 CMP	X1, X5

  (2960) 0x4da74c B.GE	4da784

  (2960) 0x4da750 STR	X2, [SP, #104]

  (2960) 0x4da754 HINT	#0

  (2960) 0x4da758 HINT	#0

  (2960) 0x4da75c HINT	#0

    (2962) 0x4da760 LDR	X0, [X25, X1,LSL #3]

    (2962) 0x4da764 ADD	X0, X22, X0

    (2962) 0x4da768 LDR	X2, [X19, X0,LSL #3]

    (2962) 0x4da76c CMP	X2, X15

    (2962) 0x4da770 B.LT	4da88c

    (2962) 0x4da774 ADD	X1, X1, #1

    (2962) 0x4da778 CMP	X1, X5

    (2962) 0x4da77c B.LT	4da760

  (2960) 0x4da780 LDR	X2, [SP, #104]

  (2960) 0x4da784 LDR	X0, [X8, X30,LSL #3]

  (2960) 0x4da788 ADD	X30, X8, X10

  (2960) 0x4da78c LDR	X1, [X8, X10]

  (2960) 0x4da790 CMP	X0, X1

  (2960) 0x4da794 B.GE	4da7bc

  (2960) 0x4da798 HINT	#0

  (2960) 0x4da79c HINT	#0

    (2961) 0x4da7a0 LDR	X13, [X26, X0,LSL #3]

    (2961) 0x4da7a4 LDR	X10, [X19, X13,LSL #3]

    (2961) 0x4da7a8 CMP	X10, X20

    (2961) 0x4da7ac B.LT	4da860

    (2961) 0x4da7b0 ADD	X0, X0, #1

    (2961) 0x4da7b4 CMP	X0, X1

    (2961) 0x4da7b8 B.LT	4da7a0

  (2960) 0x4da7bc LDR	X5, [X11, X16]

  (2960) 0x4da7c0 ADD	X18, X18, #1

  (2960) 0x4da7c4 CMP	X5, X18

  (2960) 0x4da7c8 B.GT	4da730

0x4da7cc ORR	X5, XZR, X4

0x4da7d0 B	4da65c

    (2967) 0x4da7d4 STR	X3, [X19, X1,LSL #3]

    (2967) 0x4da7d8 ADD	X0, X0, #1

    (2967) 0x4da7dc ADD	X3, X3, #1

    (2967) 0x4da7e0 LDR	X10, [X25]

    (2967) 0x4da7e4 CMP	X10, X0

    (2967) 0x4da7e8 B.GT	4da6a0

  (2964) 0x4da7ec LDR	X2, [SP, #104]

  (2964) 0x4da7f0 B	4da6c0

  (2964) 0x4da7f4 LDR	X1, [X9, X30,LSL #3]

  (2964) 0x4da7f8 ADD	X30, X9, X13

  (2964) 0x4da7fc LDR	X13, [X9, X13]

  (2964) 0x4da800 CMP	X1, X13

  (2964) 0x4da804 B.GE	4da6c4

    (2965) 0x4da808 LDR	X25, [X27, X1,LSL #3]

    (2965) 0x4da80c LDR	X0, [X24, X25,LSL #3]

    (2965) 0x4da810 ADD	X10, X22, X0

    (2965) 0x4da814 LDR	X25, [X19, X10,LSL #3]

    (2965) 0x4da818 CMP	X25, X15

    (2965) 0x4da81c B.LT	4da844

    (2966) 0x4da820 ADD	X1, X1, #1

    (2966) 0x4da824 CMP	X1, X13

    (2966) 0x4da828 B.GE	4da6c4

    (2966) 0x4da82c LDR	X25, [X27, X1,LSL #3]

    (2966) 0x4da830 LDR	X0, [X24, X25,LSL #3]

    (2966) 0x4da834 ADD	X10, X22, X0

    (2966) 0x4da838 LDR	X25, [X19, X10,LSL #3]

    (2966) 0x4da83c CMP	X25, X15

    (2966) 0x4da840 B.GE	4da820

    (2965) 0x4da844 STR	X12, [X19, X10,LSL #3]

    (2965) 0x4da848 ADD	X1, X1, #1

    (2965) 0x4da84c ADD	X12, X12, #1

    (2965) 0x4da850 LDR	X13, [X30]

    (2965) 0x4da854 CMP	X13, X1

    (2965) 0x4da858 B.GT	4da808

  (2964) 0x4da85c B	4da6c4

    (2961) 0x4da860 STR	X3, [X19, X13,LSL #3]

    (2961) 0x4da864 ADD	X0, X0, #1

    (2961) 0x4da868 ADD	X3, X3, #1

    (2961) 0x4da86c LDR	X1, [X30]

    (2961) 0x4da870 CMP	X1, X0

    (2961) 0x4da874 B.GT	4da7a0

  (2960) 0x4da878 LDR	X5, [X11, X16]

  (2960) 0x4da87c ADD	X18, X18, #1

  (2960) 0x4da880 CMP	X5, X18

  (2960) 0x4da884 B.GT	4da730

0x4da888 B	4da7cc

    (2962) 0x4da88c STR	X12, [X19, X0,LSL #3]

    (2962) 0x4da890 ADD	X1, X1, #1

    (2962) 0x4da894 ADD	X12, X12, #1

    (2962) 0x4da898 LDR	X5, [X13]

    (2962) 0x4da89c CMP	X5, X1

    (2962) 0x4da8a0 B.GT	4da760

  (2960) 0x4da8a4 B	4da780

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 127 - 242

--------------------------------------------------------------------------------

127:     for (i1 = ns; i1 < ne; i1++)

[...]

135:       if ( allsquare ) {

[...]

144:       if (num_cols_offd_A)

145:       {

146:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

[...]

154:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

155:             {

156:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

164:                if (B_marker[i3] < jj_row_begin_offd)

165:                {

166:                   B_marker[i3] = jj_count_offd;

167:                   jj_count_offd++;

168:                }

169:             }

170:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

171:             {

172:                i3 = B_ext_diag_j[jj3];

173:

174:                if (B_marker[i3] < jj_row_begin_diag)

175:                {

176:                   B_marker[i3] = jj_count_diag;

177:                   jj_count_diag++;

[...]

187:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

[...]

195:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

[...]

205:             if (B_marker[i3] < jj_row_begin_diag)

206:             {

207:                B_marker[i3] = jj_count_diag;

208:                jj_count_diag++;

[...]

216:          if (num_cols_offd_B)

217:          {

218:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

219:             {

220:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

228:                if (B_marker[i3] < jj_row_begin_offd)

229:                {

230:                   B_marker[i3] = jj_count_offd;

231:                   jj_count_offd++;

[...]

241:       (*C_diag_i)[i1] = jj_row_begin_diag;

242:       (*C_offd_i)[i1] = jj_row_begin_offd;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	micro-operation queue,
Function	hypre_ParMatmul_RowSizes._omp_fn.0
Source	par_csr_matop.c:127-127,par_csr_matop.c:135-135,par_csr_matop.c:144-146,par_csr_matop.c:187-187,par_csr_matop.c:241-242
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.75
CQA cycles if no scalar integer	3.75
CQA cycles if FP arith vectorized	3.75
CQA cycles if fully vectorized	0.94
Front-end cycles	3.75
DIV/SQRT cycles	3.50
P0 cycles	3.50
P1 cycles	3.25
P2 cycles	3.25
P3 cycles	3.25
P4 cycles	3.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	3.33
P10 cycles	3.33
P11 cycles	3.33
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	30.00
Nb uops	30.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.33
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	micro-operation queue,
Function	hypre_ParMatmul_RowSizes._omp_fn.0
Source	par_csr_matop.c:127-127,par_csr_matop.c:135-135,par_csr_matop.c:144-146,par_csr_matop.c:187-187,par_csr_matop.c:241-242
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.75
CQA cycles if no scalar integer	3.75
CQA cycles if FP arith vectorized	3.75
CQA cycles if fully vectorized	0.94
Front-end cycles	3.75
DIV/SQRT cycles	3.50
P0 cycles	3.50
P1 cycles	3.25
P2 cycles	3.25
P3 cycles	3.25
P4 cycles	3.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	3.33
P10 cycles	3.33
P11 cycles	3.33
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	30.00
Nb uops	30.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.33
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParMatmul_RowSizes._omp_fn.0
Source file and lines	par_csr_matop.c:127-242
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:127,135,144-146,154-156,164-177,187,195,205-208,216-220,228-231,241-242.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:127,135,144-146,187,241-242.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.75 to 0.94 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	3.25	3.25	3.25	3.25	0.00	0.00	0.00	0.00	3.33	3.33	3.33	1.00	1.00
cycles	3.50	3.50	3.25	3.25	3.25	3.25	0.00	0.00	0.00	0.00	3.33	3.33	3.33	1.00	1.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.75
Overall L1	3.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.75 cycles. At this rate:

17% of peak load performance is reached (17.07 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (4.27 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4da65c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X4, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X3, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X12, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CBNZ X4, 4da71c <hypre_ParMatmul_RowSizes._omp_fn.0+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X28, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X4, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X30, [X28, X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X18, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4da6d8 <hypre_ParMatmul_RowSizes._omp_fn.0+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X25, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X4, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X20, [X4, X17,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X20, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X15, [X2, X17,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X17, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X20, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4da8a8 <hypre_ParMatmul_RowSizes._omp_fn.0+0x388>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X3, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X15, XZR, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CBZ X3, 4da64c <hypre_ParMatmul_RowSizes._omp_fn.0+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X11, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X11, X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X18, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4da65c <hypre_ParMatmul_RowSizes._omp_fn.0+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X4, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X5, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 4da65c <hypre_ParMatmul_RowSizes._omp_fn.0+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
B 4da7cc <hypre_ParMatmul_RowSizes._omp_fn.0+0x2ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_ParMatmul_RowSizes._omp_fn.0
Source file and lines	par_csr_matop.c:127-242
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:127,135,144-146,154-156,164-177,187,195,205-208,216-220,228-231,241-242.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:127,135,144-146,187,241-242.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.75 to 0.94 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	3.25	3.25	3.25	3.25	0.00	0.00	0.00	0.00	3.33	3.33	3.33	1.00	1.00
cycles	3.50	3.50	3.25	3.25	3.25	3.25	0.00	0.00	0.00	0.00	3.33	3.33	3.33	1.00	1.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.75
Overall L1	3.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.75 cycles. At this rate:

17% of peak load performance is reached (17.07 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (4.27 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4da65c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X4, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X3, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X12, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CBNZ X4, 4da71c <hypre_ParMatmul_RowSizes._omp_fn.0+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X28, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X4, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X30, [X28, X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X18, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4da6d8 <hypre_ParMatmul_RowSizes._omp_fn.0+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X25, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X4, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X20, [X4, X17,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X20, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X15, [X2, X17,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X17, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X20, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4da8a8 <hypre_ParMatmul_RowSizes._omp_fn.0+0x388>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X3, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X15, XZR, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CBZ X3, 4da64c <hypre_ParMatmul_RowSizes._omp_fn.0+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X11, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X11, X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X18, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4da65c <hypre_ParMatmul_RowSizes._omp_fn.0+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X4, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X5, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 4da65c <hypre_ParMatmul_RowSizes._omp_fn.0+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
B 4da7cc <hypre_ParMatmul_RowSizes._omp_fn.0+0x2ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code