OV - exec - Loop 2956

	Loop Id: 2956	Module: exec	Source: par_csr_matop.c:263-266	Coverage: 0.01%

0x4dadf0 LDR	X16, [X19, X10,LSL #3]    [8]

0x4dadf4 ADD	X2, X10, #1

0x4dadf8 ADD	X23, X10, #2

0x4dadfc ADD	X17, X10, #3

0x4dae00 ADD	X21, X10, #4

0x4dae04 ADD	X27, X10, #5

0x4dae08 ADD	X26, X10, #6

0x4dae0c ADD	X4, X10, #7

0x4dae10 ADD	X24, X16, X0

0x4dae14 STR	X24, [X19, X10,LSL #3]    [8]

0x4dae18 LDR	X22, [X13, X10,LSL #3]    [9]

0x4dae1c ADD	X8, X22, X5

0x4dae20 STR	X8, [X13, X10,LSL #3]    [9]

0x4dae24 ADD	X10, X10, #8

0x4dae28 LDR	X7, [X19, X2,LSL #3]    [10]

0x4dae2c ADD	X9, X7, X0

0x4dae30 STR	X9, [X19, X2,LSL #3]    [10]

0x4dae34 LDR	X6, [X13, X2,LSL #3]    [4]

0x4dae38 ADD	X11, X6, X5

0x4dae3c STR	X11, [X13, X2,LSL #3]    [4]

0x4dae40 LDR	X14, [X19, X23,LSL #3]    [2]

0x4dae44 ADD	X1, X14, X0

0x4dae48 STR	X1, [X19, X23,LSL #3]    [2]

0x4dae4c LDR	X20, [X13, X23,LSL #3]    [16]

0x4dae50 ADD	X28, X20, X5

0x4dae54 STR	X28, [X13, X23,LSL #3]    [16]

0x4dae58 LDR	X15, [X19, X17,LSL #3]    [5]

0x4dae5c ADD	X25, X15, X0

0x4dae60 STR	X25, [X19, X17,LSL #3]    [5]

0x4dae64 LDR	X12, [X13, X17,LSL #3]    [12]

0x4dae68 ADD	X30, X12, X5

0x4dae6c STR	X30, [X13, X17,LSL #3]    [12]

0x4dae70 LDR	X3, [X19, X21,LSL #3]    [1]

0x4dae74 ADD	X18, X3, X0

0x4dae78 STR	X18, [X19, X21,LSL #3]    [1]

0x4dae7c LDR	X16, [X13, X21,LSL #3]    [14]

0x4dae80 ADD	X2, X16, X5

0x4dae84 STR	X2, [X13, X21,LSL #3]    [14]

0x4dae88 LDR	X17, [X19, X27,LSL #3]    [3]

0x4dae8c ADD	X23, X17, X0

0x4dae90 STR	X23, [X19, X27,LSL #3]    [3]

0x4dae94 LDR	X21, [X13, X27,LSL #3]    [17]

0x4dae98 ADD	X24, X21, X5

0x4dae9c STR	X24, [X13, X27,LSL #3]    [17]

0x4daea0 LDR	X27, [X19, X26,LSL #3]    [15]

0x4daea4 ADD	X22, X27, X0

0x4daea8 STR	X22, [X19, X26,LSL #3]    [15]

0x4daeac LDR	X8, [X13, X26,LSL #3]    [13]

0x4daeb0 ADD	X7, X8, X5

0x4daeb4 STR	X7, [X13, X26,LSL #3]    [13]

0x4daeb8 LDR	X26, [X19, X4,LSL #3]    [11]

0x4daebc ADD	X9, X26, X0

0x4daec0 STR	X9, [X19, X4,LSL #3]    [11]

0x4daec4 LDR	X6, [X13, X4,LSL #3]    [6]

0x4daec8 ADD	X11, X6, X5

0x4daecc STR	X11, [X13, X4,LSL #3]    [6]

0x4daed0 LDR	X4, [SP, #112]    [7]

0x4daed4 CMP	X4, X10

0x4daed8 B.NE	4dadf0

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 263 - 266

--------------------------------------------------------------------------------

263:        for (i1 = ns; i1 < ne; i1++)

264:        {

265:           (*C_diag_i)[i1] += jj_count_diag;

266:           (*C_offd_i)[i1] += jj_count_offd;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38
Bottlenecks	P10, P11, P12,
Function	hypre_ParMatmul_RowSizes._omp_fn.0
Source	par_csr_matop.c:263-266
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.00
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	11.00
CQA cycles if fully vectorized	2.75
Front-end cycles	7.38
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	6.25
P2 cycles	6.25
P3 cycles	6.25
P4 cycles	6.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	11.00
P10 cycles	11.00
P11 cycles	11.00
P12 cycles	8.00
P13 cycles	8.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	59.00
Nb uops	59.00
Nb loads	NA
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	136.00
Bytes stored	128.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38
Bottlenecks	P10, P11, P12,
Function	hypre_ParMatmul_RowSizes._omp_fn.0
Source	par_csr_matop.c:263-266
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.00
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	11.00
CQA cycles if fully vectorized	2.75
Front-end cycles	7.38
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	6.25
P2 cycles	6.25
P3 cycles	6.25
P4 cycles	6.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	11.00
P10 cycles	11.00
P11 cycles	11.00
P12 cycles	8.00
P13 cycles	8.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	59.00
Nb uops	59.00
Nb loads	NA
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	136.00
Bytes stored	128.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParMatmul_RowSizes._omp_fn.0
Source file and lines	par_csr_matop.c:263-266
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:263-266.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 11.00 to 2.75 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 136 bytes. The binary loop is storing 128 bytes.

General properties

nb instructions	59
loop length	236
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	6.25	6.25	6.25	6.25	0.00	0.00	0.00	0.00	11.00	11.00	11.00	8.00	8.00
cycles	0.50	0.50	6.25	6.25	6.25	6.25	0.00	0.00	0.00	0.00	11.00	11.00	11.00	8.00	8.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.38
Data deps.	1.00
Overall L1	11.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.00 cycles. At this rate:

12% of peak load performance is reached (12.36 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
24% of peak store performance is reached (11.64 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4dadf0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X16, [X19, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X23, X10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X17, X10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X21, X10, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X27, X10, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X26, X10, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X10, #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X24, X16, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X24, [X19, X10,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X22, [X13, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X22, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X13, X10,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X7, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X7, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X9, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X6, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X6, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X19, X23,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X14, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X1, [X19, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X20, [X13, X23,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X28, X20, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X28, [X13, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [X19, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X25, X15, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X25, [X19, X17,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X13, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X30, X12, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X30, [X13, X17,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X19, X21,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X18, [X19, X21,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X13, X21,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X16, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X2, [X13, X21,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X17, [X19, X27,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X23, X17, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X23, [X19, X27,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X13, X27,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X24, X21, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X24, [X13, X27,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X27, [X19, X26,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X22, X27, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X22, [X19, X26,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X13, X26,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X7, X8, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X7, [X13, X26,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X26, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X26, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X9, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X6, [X13, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X6, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X13, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X4, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 4dadf0 <hypre_ParMatmul_RowSizes._omp_fn.0+0x8d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_ParMatmul_RowSizes._omp_fn.0
Source file and lines	par_csr_matop.c:263-266
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:263-266.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 136 bytes. The binary loop is storing 128 bytes.

General properties

nb instructions	59
loop length	236
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	6.25	6.25	6.25	6.25	0.00	0.00	0.00	0.00	11.00	11.00	11.00	8.00	8.00
cycles	0.50	0.50	6.25	6.25	6.25	6.25	0.00	0.00	0.00	0.00	11.00	11.00	11.00	8.00	8.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.38
Data deps.	1.00
Overall L1	11.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.00 cycles. At this rate:

12% of peak load performance is reached (12.36 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
24% of peak store performance is reached (11.64 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4dadf0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X16, [X19, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X23, X10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X17, X10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X21, X10, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X27, X10, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X26, X10, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X10, #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X24, X16, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X24, [X19, X10,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X22, [X13, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X22, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X13, X10,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X7, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X7, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X9, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X6, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X6, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X19, X23,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X14, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X1, [X19, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X20, [X13, X23,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X28, X20, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X28, [X13, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [X19, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X25, X15, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X25, [X19, X17,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X13, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X30, X12, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X30, [X13, X17,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X19, X21,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X18, [X19, X21,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X13, X21,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X16, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X2, [X13, X21,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X17, [X19, X27,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X23, X17, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X23, [X19, X27,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X13, X27,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X24, X21, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X24, [X13, X27,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X27, [X19, X26,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X22, X27, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X22, [X19, X26,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X13, X26,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X7, X8, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X7, [X13, X26,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X26, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X26, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X9, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X6, [X13, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X6, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X13, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X4, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 4dadf0 <hypre_ParMatmul_RowSizes._omp_fn.0+0x8d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code