OV - exec - Loop 292

	Loop Id: 292	Module: exec	Source: par_coarsen.c:2232-2243	Coverage: 0.02%

0x428ef8 STR	X1, [X20, X0,LSL #3]    [21]

0x428efc ADD	X1, X1, #1

0x428f00 ADD	X0, X0, #1

0x428f04 STR	XZR, [X23, X1,LSL #3]    [35]

0x428f08 LDR	X8, [X14, X1,LSL #3]    [8]

0x428f0c LDR	X3, [X4, X1,LSL #3]    [18]

0x428f10 CMP	X8, X3

0x428f14 B.EQ	428fb4

0x428f18 ADD	X11, X1, #1

0x428f1c STR	X1, [X20, X0,LSL #3]    [36]

0x428f20 ADD	X0, X0, #1

0x428f24 STR	XZR, [X23, X11,LSL #3]    [11]

0x428f28 LDR	X9, [X14, X11,LSL #3]    [33]

0x428f2c LDR	X22, [X4, X11,LSL #3]    [12]

0x428f30 CMP	X9, X22

0x428f34 B.EQ	428fe4

0x428f38 ADD	X19, X1, #2

0x428f3c STR	X11, [X20, X0,LSL #3]    [19]

0x428f40 ADD	X0, X0, #1

0x428f44 STR	XZR, [X23, X19,LSL #3]    [22]

0x428f48 LDR	X16, [X14, X19,LSL #3]    [3]

0x428f4c LDR	X5, [X4, X19,LSL #3]    [24]

0x428f50 CMP	X16, X5

0x428f54 B.EQ	429014

0x428f58 STR	X19, [X20, X0,LSL #3]    [20]

0x428f5c ADD	X0, X0, #1

0x428f60 LDR	X18, [SP, #152]    [13]

0x428f64 ADD	X1, X1, #3

0x428f68 CMP	X18, X1

0x428f6c B.EQ	42864c

0x428f70 STR	XZR, [X23, X1,LSL #3]    [4]

0x428f74 LDR	X6, [X14, X1,LSL #3]    [15]

0x428f78 LDR	X15, [X4, X1,LSL #3]    [10]

0x428f7c CMP	X6, X15

0x428f80 B.NE	428ef8

0x428f84 LDR	X18, [X17, X1,LSL #3]    [5]

0x428f88 LDR	X30, [X27, X1,LSL #3]    [28]

0x428f8c CMP	X18, X30

0x428f90 B.NE	428ef8

0x428f94 STR	X12, [X23, X1,LSL #3]    [4]

0x428f98 STR	XZR, [X26, X1,LSL #3]    [2]

0x428f9c ADD	X1, X1, #1

0x428fa0 STR	XZR, [X23, X1,LSL #3]    [35]

0x428fa4 LDR	X8, [X14, X1,LSL #3]    [8]

0x428fa8 LDR	X3, [X4, X1,LSL #3]    [18]

0x428fac CMP	X8, X3

0x428fb0 B.NE	428f18

0x428fb4 LDR	X10, [X17, X1,LSL #3]    [32]

0x428fb8 LDR	X2, [X27, X1,LSL #3]    [14]

0x428fbc CMP	X10, X2

0x428fc0 B.NE	428f18

0x428fc4 ADD	X11, X1, #1

0x428fc8 STR	X12, [X23, X1,LSL #3]    [30]

0x428fcc STR	XZR, [X26, X1,LSL #3]    [27]

0x428fd0 STR	XZR, [X23, X11,LSL #3]    [37]

0x428fd4 LDR	X9, [X14, X11,LSL #3]    [17]

0x428fd8 LDR	X22, [X4, X11,LSL #3]    [1]

0x428fdc CMP	X9, X22

0x428fe0 B.NE	428f38

0x428fe4 LDR	X13, [X17, X11,LSL #3]    [26]

0x428fe8 LDR	X7, [X27, X11,LSL #3]    [16]

0x428fec CMP	X13, X7

0x428ff0 B.NE	428f38

0x428ff4 ADD	X19, X1, #2

0x428ff8 STR	X12, [X23, X11,LSL #3]    [38]

0x428ffc STR	XZR, [X26, X11,LSL #3]    [23]

0x429000 STR	XZR, [X23, X19,LSL #3]    [7]

0x429004 LDR	X16, [X14, X19,LSL #3]    [29]

0x429008 LDR	X5, [X4, X19,LSL #3]    [9]

0x42900c CMP	X16, X5

0x429010 B.NE	428f58

0x429014 LDR	X6, [X17, X19,LSL #3]    [34]

0x429018 LDR	X15, [X27, X19,LSL #3]    [25]

0x42901c CMP	X6, X15

0x429020 B.NE	428f58

0x429024 STR	X12, [X23, X19,LSL #3]    [6]

0x429028 STR	XZR, [X26, X19,LSL #3]    [31]

0x42902c B	428f60

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2232 - 2243

--------------------------------------------------------------------------------

2232:       for (i=0; i < num_variables; i++)

2233:       {

2234:          CF_marker[i] = 0;

2235:          if ( (S_diag_i[i+1]-S_diag_i[i]) == 0

2236:                 && (S_offd_i[i+1]-S_offd_i[i]) == 0)

2237:          {

2238:             CF_marker[i] = SF_PT; /* an isolated fine grid */

2239:             if (CF_init == 3 || CF_init == 4) CF_marker[i] = C_PT;

2240:             measure_array[i] = 0;

2241:          }

2242:          else

2243:             graph_array[cnt++] = i;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.01
Bottlenecks	P10,
Function	hypre_BoomerAMGCoarsenPMIS
Source	par_coarsen.c:2232-2243
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.17
CQA cycles if no scalar integer	14.17
CQA cycles if FP arith vectorized	14.17
CQA cycles if fully vectorized	3.54
Front-end cycles	9.75
DIV/SQRT cycles	6.50
P0 cycles	6.50
P1 cycles	5.75
P2 cycles	5.75
P3 cycles	5.75
P4 cycles	5.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	14.17
P10 cycles	13.83
P11 cycles	14.00
P12 cycles	9.50
P13 cycles	9.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	78.00
Nb uops	78.00
Nb loads	NA
Nb stores	19.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.72
Bytes prefetched	0.00
Bytes loaded	184.00
Bytes stored	152.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.01
Bottlenecks	P10,
Function	hypre_BoomerAMGCoarsenPMIS
Source	par_coarsen.c:2232-2243
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.17
CQA cycles if no scalar integer	14.17
CQA cycles if FP arith vectorized	14.17
CQA cycles if fully vectorized	3.54
Front-end cycles	9.75
DIV/SQRT cycles	6.50
P0 cycles	6.50
P1 cycles	5.75
P2 cycles	5.75
P3 cycles	5.75
P4 cycles	5.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	14.17
P10 cycles	13.83
P11 cycles	14.00
P12 cycles	9.50
P13 cycles	9.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	78.00
Nb uops	78.00
Nb loads	NA
Nb stores	19.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.72
Bytes prefetched	0.00
Bytes loaded	184.00
Bytes stored	152.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGCoarsenPMIS
Source file and lines	par_coarsen.c:2232-2243
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2232-2243.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 81 paths individually, rerun with max-paths=81
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 81 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 14.17 to 3.54 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 184 bytes. The binary loop is storing 152 bytes.

General properties

nb instructions	78
loop length	312
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.50	6.50	5.75	5.75	5.75	5.75	0.00	0.00	0.00	0.00	14.17	13.83	14.00	9.50	9.50
cycles	6.50	6.50	5.75	5.75	5.75	5.75	0.00	0.00	0.00	0.00	14.17	13.83	14.00	9.50	9.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.75
Overall L1	14.17

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.17 cycles. At this rate:

13% of peak load performance is reached (12.99 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (10.73 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 428f70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STR X1, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X14, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X4, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 428fb4 <hypre_BoomerAMGCoarsenPMIS+0xf10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X11, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X1, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X23, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X14, X11,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X4, X11,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 428fe4 <hypre_BoomerAMGCoarsenPMIS+0xf40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X19, X1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X23, X19,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X14, X19,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X4, X19,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X16, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 429014 <hypre_BoomerAMGCoarsenPMIS+0xf70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X19, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X18, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X18, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 42864c <hypre_BoomerAMGCoarsenPMIS+0x5a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR XZR, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X6, [X14, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X4, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X6, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 428ef8 <hypre_BoomerAMGCoarsenPMIS+0xe54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X27, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X18, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 428ef8 <hypre_BoomerAMGCoarsenPMIS+0xe54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X12, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X26, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X14, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X4, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 428f18 <hypre_BoomerAMGCoarsenPMIS+0xe74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X27, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X10, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 428f18 <hypre_BoomerAMGCoarsenPMIS+0xe74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X11, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X12, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X26, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X23, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X14, X11,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X4, X11,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 428f38 <hypre_BoomerAMGCoarsenPMIS+0xe94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X17, X11,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X27, X11,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X13, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 428f38 <hypre_BoomerAMGCoarsenPMIS+0xe94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X19, X1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X12, [X23, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X26, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X23, X19,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X14, X19,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X4, X19,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X16, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 428f58 <hypre_BoomerAMGCoarsenPMIS+0xeb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X6, [X17, X19,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X27, X19,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X6, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 428f58 <hypre_BoomerAMGCoarsenPMIS+0xeb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X12, [X23, X19,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X26, X19,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 428f60 <hypre_BoomerAMGCoarsenPMIS+0xebc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_BoomerAMGCoarsenPMIS
Source file and lines	par_coarsen.c:2232-2243
Module	exec

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 81 paths individually, rerun with max-paths=81
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 184 bytes. The binary loop is storing 152 bytes.

General properties

nb instructions	78
loop length	312
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.50	6.50	5.75	5.75	5.75	5.75	0.00	0.00	0.00	0.00	14.17	13.83	14.00	9.50	9.50
cycles	6.50	6.50	5.75	5.75	5.75	5.75	0.00	0.00	0.00	0.00	14.17	13.83	14.00	9.50	9.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.75
Overall L1	14.17

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.17 cycles. At this rate:

13% of peak load performance is reached (12.99 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (10.73 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 428f70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STR X1, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X14, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X4, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 428fb4 <hypre_BoomerAMGCoarsenPMIS+0xf10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X11, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X1, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X23, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X14, X11,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X4, X11,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 428fe4 <hypre_BoomerAMGCoarsenPMIS+0xf40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X19, X1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X23, X19,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X14, X19,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X4, X19,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X16, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 429014 <hypre_BoomerAMGCoarsenPMIS+0xf70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X19, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X18, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X18, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 42864c <hypre_BoomerAMGCoarsenPMIS+0x5a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR XZR, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X6, [X14, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X4, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X6, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 428ef8 <hypre_BoomerAMGCoarsenPMIS+0xe54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X27, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X18, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 428ef8 <hypre_BoomerAMGCoarsenPMIS+0xe54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X12, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X26, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X14, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X4, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 428f18 <hypre_BoomerAMGCoarsenPMIS+0xe74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X27, X1,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X10, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 428f18 <hypre_BoomerAMGCoarsenPMIS+0xe74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X11, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X12, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X26, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X23, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X14, X11,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X4, X11,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 428f38 <hypre_BoomerAMGCoarsenPMIS+0xe94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X17, X11,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X27, X11,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X13, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 428f38 <hypre_BoomerAMGCoarsenPMIS+0xe94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X19, X1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X12, [X23, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X26, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X23, X19,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X14, X19,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X4, X19,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X16, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 428f58 <hypre_BoomerAMGCoarsenPMIS+0xeb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X6, [X17, X19,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X27, X19,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X6, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 428f58 <hypre_BoomerAMGCoarsenPMIS+0xeb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X12, [X23, X19,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X26, X19,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 428f60 <hypre_BoomerAMGCoarsenPMIS+0xebc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code