OV - exec - Loop 2582

	Loop Id: 2582	Module: exec	Source: ams.c:3662-3682 [...]	Coverage: 4.29%

0x4be658 ADD	X1, X1, #1

0x4be65c CMP	X2, X1

0x4be660 B.EQ	4be980

0x4be664 LDR	X0, [X10, X1,LSL #3]

0x4be668 LDR	D1, [X4, X0,LSL #3]

0x4be66c FCMP	D4, D1

0x4be670 B.EQ	4be658

0x4be674 LDR	X21, [X30, X1,LSL #3]

0x4be678 LDR	D0, [X17, X1,LSL #3]

0x4be67c CMP	X0, X21

0x4be680 B.GE	4be7e8

0x4be684 ORN	X3, XZR, X0

0x4be688 ADD	X11, X3, X21

0x4be68c ANDS	X12, X11, #4224

0x4be690 B.EQ	4be7b4

0x4be694 LDR	X13, [X6, X0,LSL #3]

0x4be698 ADD	X0, X0, #1

0x4be69c LDR	D2, [X5, X13,LSL #3]

0x4be6a0 FMSUB	D0, D2, D1, D0

0x4be6a4 LDR	D1, [X4, X0,LSL #3]

0x4be6a8 CMP	X12, #1

0x4be6ac B.EQ	4be7b4

0x4be6b0 CMP	X12, #2

0x4be6b4 B.EQ	4be728

0x4be6b8 CMP	X12, #3

0x4be6bc B.EQ	4be714

0x4be6c0 CMP	X12, #4

0x4be6c4 B.EQ	4be700

0x4be6c8 CMP	X12, #5

0x4be6cc B.EQ	4be6ec

0x4be6d0 CMP	X12, #6

0x4be6d4 B.NE	4be9a0

0x4be6d8 LDR	X22, [X6, X0,LSL #3]

0x4be6dc ADD	X0, X0, #1

0x4be6e0 LDR	D5, [X5, X22,LSL #3]

0x4be6e4 FMSUB	D0, D5, D1, D0

0x4be6e8 LDR	D1, [X4, X0,LSL #3]

0x4be6ec LDR	X23, [X6, X0,LSL #3]

0x4be6f0 ADD	X0, X0, #1

0x4be6f4 LDR	D7, [X5, X23,LSL #3]

0x4be6f8 FMSUB	D0, D7, D1, D0

0x4be6fc LDR	D1, [X4, X0,LSL #3]

0x4be700 LDR	X19, [X6, X0,LSL #3]

0x4be704 ADD	X0, X0, #1

0x4be708 LDR	D16, [X5, X19,LSL #3]

0x4be70c FMSUB	D0, D16, D1, D0

0x4be710 LDR	D1, [X4, X0,LSL #3]

0x4be714 LDR	X3, [X6, X0,LSL #3]

0x4be718 ADD	X0, X0, #1

0x4be71c LDR	D17, [X5, X3,LSL #3]

0x4be720 FMSUB	D0, D17, D1, D0

0x4be724 LDR	D1, [X4, X0,LSL #3]

0x4be728 LDR	X11, [X6, X0,LSL #3]

0x4be72c ADD	X0, X0, #1

0x4be730 LDR	D18, [X5, X11,LSL #3]

0x4be734 FMSUB	D0, D18, D1, D0

0x4be738 LDR	D1, [X4, X0,LSL #3]

0x4be73c B	4be7b4

  (2584) 0x4be740 LDR	X19, [X6, X3,LSL #3]

  (2584) 0x4be744 LDR	D19, [X4, X3,LSL #3]

  (2584) 0x4be748 LDR	X3, [X6, X14,LSL #3]

  (2584) 0x4be74c LDR	D1, [X5, X19,LSL #3]

  (2584) 0x4be750 LDR	D20, [X4, X14,LSL #3]

  (2584) 0x4be754 LDR	D21, [X5, X3,LSL #3]

  (2584) 0x4be758 LDR	X14, [X6, X13,LSL #3]

  (2584) 0x4be75c FMSUB	D22, D1, D19, D0

  (2584) 0x4be760 LDR	D23, [X4, X13,LSL #3]

  (2584) 0x4be764 LDR	X13, [X6, X12,LSL #3]

  (2584) 0x4be768 FMSUB	D24, D21, D20, D22

  (2584) 0x4be76c LDR	D25, [X5, X14,LSL #3]

  (2584) 0x4be770 LDR	D26, [X4, X12,LSL #3]

  (2584) 0x4be774 LDR	D27, [X5, X13,LSL #3]

  (2584) 0x4be778 LDR	X12, [X6, X11,LSL #3]

  (2584) 0x4be77c FMSUB	D28, D25, D23, D24

  (2584) 0x4be780 LDR	D29, [X4, X11,LSL #3]

  (2584) 0x4be784 LDR	X11, [X6, X23,LSL #3]

  (2584) 0x4be788 FMSUB	D30, D27, D26, D28

  (2584) 0x4be78c LDR	D31, [X5, X12,LSL #3]

  (2584) 0x4be790 LDR	D16, [X4, X23,LSL #3]

  (2584) 0x4be794 LDR	D5, [X5, X11,LSL #3]

  (2584) 0x4be798 LDR	X23, [X6, X22,LSL #3]

  (2584) 0x4be79c FMSUB	D2, D31, D29, D30

  (2584) 0x4be7a0 LDR	D3, [X4, X22,LSL #3]

  (2584) 0x4be7a4 LDR	D1, [X4, X0,LSL #3]

  (2584) 0x4be7a8 FMSUB	D7, D5, D16, D2

  (2584) 0x4be7ac LDR	D17, [X5, X23,LSL #3]

  (2584) 0x4be7b0 FMSUB	D0, D17, D3, D7

  (2584) 0x4be7b4 LDR	X19, [X6, X0,LSL #3]

  (2584) 0x4be7b8 ADD	X3, X0, #1

  (2584) 0x4be7bc ADD	X13, X0, #3

  (2584) 0x4be7c0 ADD	X12, X0, #4

  (2584) 0x4be7c4 ADD	X11, X0, #5

  (2584) 0x4be7c8 ADD	X23, X0, #6

  (2584) 0x4be7cc ADD	X22, X0, #7

  (2584) 0x4be7d0 ADD	X14, X0, #2

  (2584) 0x4be7d4 ADD	X0, X0, #8

  (2584) 0x4be7d8 LDR	D19, [X5, X19,LSL #3]

  (2584) 0x4be7dc FMSUB	D0, D19, D1, D0

  (2584) 0x4be7e0 CMP	X3, X21

  (2584) 0x4be7e4 B.NE	4be740

0x4be7e8 LDR	X14, [X16, X1,LSL #3]

0x4be7ec LDR	X19, [X20, X1,LSL #3]

0x4be7f0 CMP	X14, X19

0x4be7f4 B.GE	4be95c

0x4be7f8 SUB	X21, X19, X14

0x4be7fc ANDS	X0, X21, #4224

0x4be800 B.EQ	4be8b4

0x4be804 CMP	X0, #1

0x4be808 B.EQ	4be898

0x4be80c CMP	X0, #2

0x4be810 B.EQ	4be884

0x4be814 CMP	X0, #3

0x4be818 B.EQ	4be870

0x4be81c CMP	X0, #4

0x4be820 B.EQ	4be85c

0x4be824 CMP	X0, #5

0x4be828 B.EQ	4be848

0x4be82c CMP	X0, #6

0x4be830 B.NE	4be9b8

0x4be834 LDR	X12, [X8, X14,LSL #3]

0x4be838 LDR	D22, [X9, X14,LSL #3]

0x4be83c ADD	X14, X14, #1

0x4be840 LDR	D23, [X7, X12,LSL #3]

0x4be844 FMSUB	D0, D22, D23, D0

0x4be848 LDR	X11, [X8, X14,LSL #3]

0x4be84c LDR	D24, [X9, X14,LSL #3]

0x4be850 ADD	X14, X14, #1

0x4be854 LDR	D25, [X7, X11,LSL #3]

0x4be858 FMSUB	D0, D24, D25, D0

0x4be85c LDR	X23, [X8, X14,LSL #3]

0x4be860 LDR	D26, [X9, X14,LSL #3]

0x4be864 ADD	X14, X14, #1

0x4be868 LDR	D27, [X7, X23,LSL #3]

0x4be86c FMSUB	D0, D26, D27, D0

0x4be870 LDR	X22, [X8, X14,LSL #3]

0x4be874 LDR	D28, [X9, X14,LSL #3]

0x4be878 ADD	X14, X14, #1

0x4be87c LDR	D29, [X7, X22,LSL #3]

0x4be880 FMSUB	D0, D28, D29, D0

0x4be884 LDR	X3, [X8, X14,LSL #3]

0x4be888 LDR	D30, [X9, X14,LSL #3]

0x4be88c ADD	X14, X14, #1

0x4be890 LDR	D31, [X7, X3,LSL #3]

0x4be894 FMSUB	D0, D30, D31, D0

0x4be898 LDR	X21, [X8, X14,LSL #3]

0x4be89c LDR	D2, [X9, X14,LSL #3]

0x4be8a0 ADD	X14, X14, #1

0x4be8a4 LDR	D3, [X7, X21,LSL #3]

0x4be8a8 FMSUB	D0, D2, D3, D0

0x4be8ac CMP	X14, X19

0x4be8b0 B.EQ	4be95c

  (2583) 0x4be8b4 LDR	X11, [X8, X14,LSL #3]

  (2583) 0x4be8b8 ADD	X0, X14, #1

  (2583) 0x4be8bc ADD	X23, X14, #2

  (2583) 0x4be8c0 ADD	X13, X14, #3

  (2583) 0x4be8c4 ADD	X12, X14, #4

  (2583) 0x4be8c8 LDR	D5, [X9, X14,LSL #3]

  (2583) 0x4be8cc ADD	X22, X14, #5

  (2583) 0x4be8d0 LDR	X3, [X8, X0,LSL #3]

  (2583) 0x4be8d4 LDR	D7, [X7, X11,LSL #3]

  (2583) 0x4be8d8 LDR	D16, [X9, X0,LSL #3]

  (2583) 0x4be8dc ADD	X0, X14, #7

  (2583) 0x4be8e0 LDR	X21, [X8, X23,LSL #3]

  (2583) 0x4be8e4 FMSUB	D17, D5, D7, D0

  (2583) 0x4be8e8 LDR	D0, [X7, X3,LSL #3]

  (2583) 0x4be8ec LDR	D18, [X9, X23,LSL #3]

  (2583) 0x4be8f0 ADD	X23, X14, #6

  (2583) 0x4be8f4 ADD	X14, X14, #8

  (2583) 0x4be8f8 LDR	X11, [X8, X13,LSL #3]

  (2583) 0x4be8fc LDR	D19, [X7, X21,LSL #3]

  (2583) 0x4be900 FMSUB	D1, D16, D0, D17

  (2583) 0x4be904 LDR	D20, [X9, X13,LSL #3]

  (2583) 0x4be908 LDR	D22, [X7, X11,LSL #3]

  (2583) 0x4be90c LDR	X13, [X8, X12,LSL #3]

  (2583) 0x4be910 FMSUB	D23, D18, D19, D1

  (2583) 0x4be914 LDR	D21, [X9, X12,LSL #3]

  (2583) 0x4be918 LDR	X12, [X8, X22,LSL #3]

  (2583) 0x4be91c FMSUB	D24, D20, D22, D23

  (2583) 0x4be920 LDR	D26, [X7, X13,LSL #3]

  (2583) 0x4be924 LDR	D25, [X9, X22,LSL #3]

  (2583) 0x4be928 LDR	D27, [X7, X12,LSL #3]

  (2583) 0x4be92c LDR	X22, [X8, X23,LSL #3]

  (2583) 0x4be930 FMSUB	D28, D21, D26, D24

  (2583) 0x4be934 LDR	D29, [X9, X23,LSL #3]

  (2583) 0x4be938 LDR	X3, [X8, X0,LSL #3]

  (2583) 0x4be93c FMSUB	D31, D25, D27, D28

  (2583) 0x4be940 LDR	D30, [X7, X22,LSL #3]

  (2583) 0x4be944 LDR	D3, [X9, X0,LSL #3]

  (2583) 0x4be948 LDR	D2, [X7, X3,LSL #3]

  (2583) 0x4be94c FMSUB	D5, D29, D30, D31

  (2583) 0x4be950 FMSUB	D0, D3, D2, D5

  (2583) 0x4be954 CMP	X14, X19

  (2583) 0x4be958 B.NE	4be8b4

0x4be95c FMUL	D16, D6, D0

0x4be960 LDR	D7, [X18, X1,LSL #3]

0x4be964 LDR	D17, [X15, X1,LSL #3]

0x4be968 FDIV	D18, D16, D7

0x4be96c FADD	D0, D17, D18

0x4be970 STR	D0, [X15, X1,LSL #3]

0x4be974 ADD	X1, X1, #1

0x4be978 CMP	X2, X1

0x4be97c B.NE	4be664

0x4be9a0 LDR	X14, [X6, X0,LSL #3]

0x4be9a4 ADD	X0, X0, #1

0x4be9a8 LDR	D3, [X5, X14,LSL #3]

0x4be9ac FMSUB	D0, D3, D1, D0

0x4be9b0 LDR	D1, [X4, X0,LSL #3]

0x4be9b4 B	4be6d8

0x4be9b8 LDR	X13, [X8, X14,LSL #3]

0x4be9bc LDR	D20, [X9, X14,LSL #3]

0x4be9c0 ADD	X14, X14, #1

0x4be9c4 LDR	D21, [X7, X13,LSL #3]

0x4be9c8 FMSUB	D0, D20, D21, D0

0x4be9cc B	4be834

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3662 - 3682

--------------------------------------------------------------------------------

3662: #pragma omp parallel for private(i,ii,jj,res) HYPRE_SMP_SCHEDULE

[...]

3669:          if (A_diag_data[A_diag_i[i]] != zero)

3670:          {

3671:             res = f_data[i];

3672:             for (jj = A_diag_i[i]; jj < A_diag_i[i+1]; jj++)

3673:             {

3674:                ii = A_diag_j[jj];

3675:                res -= A_diag_data[jj] * Vtemp_data[ii];

3676:             }

3677:             for (jj = A_offd_i[i]; jj < A_offd_i[i+1]; jj++)

3678:             {

3679:                ii = A_offd_j[jj];

3680:                res -= A_offd_data[jj] * Vext_data[ii];

3681:             }

3682:             u_data[i] += (relax_weight*res)/l1_norms[i];

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.45
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.01
Bottlenecks	P10,
Function	hypre_ParCSRRelaxThreads._omp_fn.1
Source	ams.c:3662-3662,ams.c:3669-3672,ams.c:3675-3677,ams.c:3680-3682
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.17
CQA cycles if no scalar integer	11.83
CQA cycles if FP arith vectorized	17.17
CQA cycles if fully vectorized	4.29
Front-end cycles	16.25
DIV/SQRT cycles	11.50
P0 cycles	11.50
P1 cycles	9.50
P2 cycles	9.50
P3 cycles	9.50
P4 cycles	9.50
P5 cycles	4.75
P6 cycles	4.75
P7 cycles	4.75
P8 cycles	4.75
P9 cycles	17.17
P10 cycles	16.83
P11 cycles	17.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.75 - 3.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	130.00
Nb uops	130.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	1.81
Nb FLOP add-sub	1.00
Nb FLOP mul	1.00
Nb FLOP fma	14.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.77
Bytes prefetched	0.00
Bytes loaded	400.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.45
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.01
Bottlenecks	P10,
Function	hypre_ParCSRRelaxThreads._omp_fn.1
Source	ams.c:3662-3662,ams.c:3669-3672,ams.c:3675-3677,ams.c:3680-3682
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.17
CQA cycles if no scalar integer	11.83
CQA cycles if FP arith vectorized	17.17
CQA cycles if fully vectorized	4.29
Front-end cycles	16.25
DIV/SQRT cycles	11.50
P0 cycles	11.50
P1 cycles	9.50
P2 cycles	9.50
P3 cycles	9.50
P4 cycles	9.50
P5 cycles	4.75
P6 cycles	4.75
P7 cycles	4.75
P8 cycles	4.75
P9 cycles	17.17
P10 cycles	16.83
P11 cycles	17.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.75 - 3.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	130.00
Nb uops	130.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	1.81
Nb FLOP add-sub	1.00
Nb FLOP mul	1.00
Nb FLOP fma	14.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.77
Bytes prefetched	0.00
Bytes loaded	400.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParCSRRelaxThreads._omp_fn.1
Source file and lines	ams.c:3662-3682
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662,3669-3682.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662,3669-3672,3675-3677,3680-3682.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 153 paths individually, rerun with max-paths=153
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 153 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.17 to 11.83 cycles (1.45x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 17.17 to 4.29 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 14 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 31 FP arithmetical operations:

15: addition or subtraction (14 inside FMA instructions)
15: multiply (14 inside FMA instructions)
1: divide

The binary loop is loading 400 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	130
loop length	520
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

16.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	11.50	11.50	9.50	9.50	9.50	9.50	4.75	4.75	4.75	4.75	17.17	16.83	17.00	0.00	0.00
cycles	11.50	11.50	9.50	9.50	9.50	9.50	4.75	4.75	4.75	4.75	17.17	16.83	17.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.75-3.50

Cycles summary

Front-end	16.25
Overall L1	17.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.17 cycles. At this rate:

24% of peak load performance is reached (23.30 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4be664

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4be980 <hypre_ParCSRRelaxThreads._omp_fn.1+0x3a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D1, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMP D4, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.EQ 4be658 <hypre_ParCSRRelaxThreads._omp_fn.1+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X21, [X30, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D0, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
CMP X0, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 4be7e8 <hypre_ParCSRRelaxThreads._omp_fn.1+0x208>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORN X3, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X11, X3, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ANDS X12, X11, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4be7b4 <hypre_ParCSRRelaxThreads._omp_fn.1+0x1d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D2, [X5, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D2, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D1, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
CMP X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4be7b4 <hypre_ParCSRRelaxThreads._omp_fn.1+0x1d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X12, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4be728 <hypre_ParCSRRelaxThreads._omp_fn.1+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X12, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4be714 <hypre_ParCSRRelaxThreads._omp_fn.1+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X12, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4be700 <hypre_ParCSRRelaxThreads._omp_fn.1+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X12, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4be6ec <hypre_ParCSRRelaxThreads._omp_fn.1+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X12, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 4be9a0 <hypre_ParCSRRelaxThreads._omp_fn.1+0x3c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X22, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D5, [X5, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D5, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D1, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X23, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D7, [X5, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D7, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D1, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X19, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D16, [X5, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D16, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D1, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X3, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D17, [X5, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D17, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D1, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X11, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D18, [X5, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D18, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D1, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
B 4be7b4 <hypre_ParCSRRelaxThreads._omp_fn.1+0x1d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [X16, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X19, [X20, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X14, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 4be95c <hypre_ParCSRRelaxThreads._omp_fn.1+0x37c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X21, X19, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ANDS X0, X21, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4be8b4 <hypre_ParCSRRelaxThreads._omp_fn.1+0x2d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4be898 <hypre_ParCSRRelaxThreads._omp_fn.1+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4be884 <hypre_ParCSRRelaxThreads._omp_fn.1+0x2a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4be870 <hypre_ParCSRRelaxThreads._omp_fn.1+0x290>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X0, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4be85c <hypre_ParCSRRelaxThreads._omp_fn.1+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X0, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4be848 <hypre_ParCSRRelaxThreads._omp_fn.1+0x268>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X0, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 4be9b8 <hypre_ParCSRRelaxThreads._omp_fn.1+0x3d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X12, [X8, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D22, [X9, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D23, [X7, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D22, D23, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X11, [X8, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D24, [X9, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D25, [X7, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D24, D25, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X23, [X8, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D26, [X9, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D27, [X7, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D26, D27, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X22, [X8, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D28, [X9, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D29, [X7, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D28, D29, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X3, [X8, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D30, [X9, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D31, [X7, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D30, D31, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X21, [X8, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D2, [X9, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D3, [X7, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D2, D3, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
CMP X14, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4be95c <hypre_ParCSRRelaxThreads._omp_fn.1+0x37c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMUL D16, D6, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D7, [X18, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D17, [X15, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FDIV D18, D16, D7	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50
FADD D0, D17, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D0, [X15, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 4be664 <hypre_ParCSRRelaxThreads._omp_fn.1+0x84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D3, [X5, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D3, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D1, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
B 4be6d8 <hypre_ParCSRRelaxThreads._omp_fn.1+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X8, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D20, [X9, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D21, [X7, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D20, D21, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
B 4be834 <hypre_ParCSRRelaxThreads._omp_fn.1+0x254>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_ParCSRRelaxThreads._omp_fn.1
Source file and lines	ams.c:3662-3682
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 153 paths individually, rerun with max-paths=153
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 14 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 31 FP arithmetical operations:

15: addition or subtraction (14 inside FMA instructions)
15: multiply (14 inside FMA instructions)
1: divide

The binary loop is loading 400 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	130
loop length	520
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

16.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	11.50	11.50	9.50	9.50	9.50	9.50	4.75	4.75	4.75	4.75	17.17	16.83	17.00	0.00	0.00
cycles	11.50	11.50	9.50	9.50	9.50	9.50	4.75	4.75	4.75	4.75	17.17	16.83	17.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.75-3.50

Cycles summary

Front-end	16.25
Overall L1	17.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.17 cycles. At this rate:

24% of peak load performance is reached (23.30 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4be664

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4be980 <hypre_ParCSRRelaxThreads._omp_fn.1+0x3a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D1, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMP D4, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.EQ 4be658 <hypre_ParCSRRelaxThreads._omp_fn.1+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X21, [X30, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D0, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
CMP X0, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 4be7e8 <hypre_ParCSRRelaxThreads._omp_fn.1+0x208>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORN X3, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X11, X3, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ANDS X12, X11, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4be7b4 <hypre_ParCSRRelaxThreads._omp_fn.1+0x1d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D2, [X5, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D2, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D1, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
CMP X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4be7b4 <hypre_ParCSRRelaxThreads._omp_fn.1+0x1d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X12, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4be728 <hypre_ParCSRRelaxThreads._omp_fn.1+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X12, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4be714 <hypre_ParCSRRelaxThreads._omp_fn.1+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X12, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4be700 <hypre_ParCSRRelaxThreads._omp_fn.1+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X12, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4be6ec <hypre_ParCSRRelaxThreads._omp_fn.1+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X12, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 4be9a0 <hypre_ParCSRRelaxThreads._omp_fn.1+0x3c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X22, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D5, [X5, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D5, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D1, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X23, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D7, [X5, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D7, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D1, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X19, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D16, [X5, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D16, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D1, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X3, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D17, [X5, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D17, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D1, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X11, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D18, [X5, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D18, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D1, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
B 4be7b4 <hypre_ParCSRRelaxThreads._omp_fn.1+0x1d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [X16, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X19, [X20, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X14, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 4be95c <hypre_ParCSRRelaxThreads._omp_fn.1+0x37c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X21, X19, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ANDS X0, X21, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4be8b4 <hypre_ParCSRRelaxThreads._omp_fn.1+0x2d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4be898 <hypre_ParCSRRelaxThreads._omp_fn.1+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4be884 <hypre_ParCSRRelaxThreads._omp_fn.1+0x2a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4be870 <hypre_ParCSRRelaxThreads._omp_fn.1+0x290>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X0, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4be85c <hypre_ParCSRRelaxThreads._omp_fn.1+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X0, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4be848 <hypre_ParCSRRelaxThreads._omp_fn.1+0x268>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X0, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 4be9b8 <hypre_ParCSRRelaxThreads._omp_fn.1+0x3d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X12, [X8, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D22, [X9, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D23, [X7, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D22, D23, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X11, [X8, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D24, [X9, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D25, [X7, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D24, D25, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X23, [X8, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D26, [X9, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D27, [X7, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D26, D27, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X22, [X8, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D28, [X9, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D29, [X7, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D28, D29, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X3, [X8, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D30, [X9, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D31, [X7, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D30, D31, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR X21, [X8, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D2, [X9, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D3, [X7, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D2, D3, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
CMP X14, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4be95c <hypre_ParCSRRelaxThreads._omp_fn.1+0x37c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMUL D16, D6, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D7, [X18, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D17, [X15, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FDIV D18, D16, D7	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50
FADD D0, D17, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D0, [X15, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 4be664 <hypre_ParCSRRelaxThreads._omp_fn.1+0x84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D3, [X5, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D3, D1, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D1, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
B 4be6d8 <hypre_ParCSRRelaxThreads._omp_fn.1+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X8, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D20, [X9, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D21, [X7, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D0, D20, D21, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
B 4be834 <hypre_ParCSRRelaxThreads._omp_fn.1+0x254>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code