OV - exec - Loop 2544

	Loop Id: 2544	Module: exec	Source: ams.c:3382-3409 [...]	Coverage: 0.03%

0x4baf48 LDR	X30, [X21, X3,LSL #3]

0x4baf4c CMP	X5, X0

0x4baf50 B.LE	4bb180

0x4baf54 SUB	X1, X5, X0

0x4baf58 ANDS	X16, X1, #4224

0x4baf5c B.EQ	4bb038

0x4baf60 CMP	X16, #1

0x4baf64 B.EQ	4bb008

0x4baf68 CMP	X16, #2

0x4baf6c B.EQ	4baff4

0x4baf70 CMP	X16, #3

0x4baf74 B.EQ	4bafe0

0x4baf78 CMP	X16, #4

0x4baf7c B.EQ	4bafcc

0x4baf80 CMP	X16, #5

0x4baf84 B.EQ	4bafb8

0x4baf88 CMP	X16, #6

0x4baf8c B.EQ	4bafa4

0x4baf90 LDR	X18, [X20, X0,LSL #3]

0x4baf94 LDR	X17, [X21, X18,LSL #3]

0x4baf98 CMP	X17, X30

0x4baf9c B.EQ	4be040

0x4bafa0 ADD	X0, X0, #1

0x4bafa4 LDR	X11, [X20, X0,LSL #3]

0x4bafa8 LDR	X14, [X21, X11,LSL #3]

0x4bafac CMP	X14, X30

0x4bafb0 B.EQ	4bcf04

0x4bafb4 ADD	X0, X0, #1

0x4bafb8 LDR	X13, [X20, X0,LSL #3]

0x4bafbc LDR	X2, [X21, X13,LSL #3]

0x4bafc0 CMP	X2, X30

0x4bafc4 B.EQ	4bce44

0x4bafc8 ADD	X0, X0, #1

0x4bafcc LDR	X15, [X20, X0,LSL #3]

0x4bafd0 LDR	X1, [X21, X15,LSL #3]

0x4bafd4 CMP	X1, X30

0x4bafd8 B.EQ	4bc278

0x4bafdc ADD	X0, X0, #1

0x4bafe0 LDR	X16, [X20, X0,LSL #3]

0x4bafe4 LDR	X18, [X21, X16,LSL #3]

0x4bafe8 CMP	X18, X30

0x4bafec B.EQ	4bc260

0x4baff0 ADD	X0, X0, #1

0x4baff4 LDR	X17, [X20, X0,LSL #3]

0x4baff8 LDR	X11, [X21, X17,LSL #3]

0x4baffc CMP	X11, X30

0x4bb000 B.EQ	4bc248

0x4bb004 ADD	X0, X0, #1

0x4bb008 LDR	X14, [X20, X0,LSL #3]

0x4bb00c LDR	X13, [X21, X14,LSL #3]

0x4bb010 CMP	X13, X30

0x4bb014 B.NE	4bb02c

0x4bb018 LDR	D19, [X22, X0,LSL #3]

0x4bb01c LDR	D20, [X19, X3,LSL #3]

0x4bb020 FABS	D21, D19

0x4bb024 FADD	D29, D20, D21

0x4bb028 STR	D29, [X19, X3,LSL #3]

0x4bb02c ADD	X0, X0, #1

0x4bb030 CMP	X0, X5

0x4bb034 B.EQ	4bb180

  (2546) 0x4bb038 LDR	X2, [X20, X0,LSL #3]

  (2546) 0x4bb03c LDR	X15, [X21, X2,LSL #3]

  (2546) 0x4bb040 CMP	X15, X30

  (2546) 0x4bb044 B.NE	4bb05c

  (2546) 0x4bb048 LDR	D22, [X22, X0,LSL #3]

  (2546) 0x4bb04c LDR	D0, [X19, X3,LSL #3]

  (2546) 0x4bb050 FABS	D23, D22

  (2546) 0x4bb054 FADD	D24, D0, D23

  (2546) 0x4bb058 STR	D24, [X19, X3,LSL #3]

  (2546) 0x4bb05c ADD	X0, X0, #1

  (2546) 0x4bb060 LDR	X1, [X20, X0,LSL #3]

  (2546) 0x4bb064 LDR	X16, [X21, X1,LSL #3]

  (2546) 0x4bb068 CMP	X16, X30

  (2546) 0x4bb06c B.NE	4bb084

  (2546) 0x4bb070 LDR	D25, [X22, X0,LSL #3]

  (2546) 0x4bb074 LDR	D26, [X19, X3,LSL #3]

  (2546) 0x4bb078 FABS	D27, D25

  (2546) 0x4bb07c FADD	D28, D26, D27

  (2546) 0x4bb080 STR	D28, [X19, X3,LSL #3]

  (2546) 0x4bb084 ADD	X18, X0, #1

  (2546) 0x4bb088 LDR	X17, [X20, X18,LSL #3]

  (2546) 0x4bb08c LDR	X11, [X21, X17,LSL #3]

  (2546) 0x4bb090 CMP	X11, X30

  (2546) 0x4bb094 B.NE	4bb0ac

  (2546) 0x4bb098 LDR	D30, [X22, X18,LSL #3]

  (2546) 0x4bb09c LDR	D31, [X19, X3,LSL #3]

  (2546) 0x4bb0a0 FABS	D2, D30

  (2546) 0x4bb0a4 FADD	D3, D31, D2

  (2546) 0x4bb0a8 STR	D3, [X19, X3,LSL #3]

  (2546) 0x4bb0ac ADD	X13, X0, #2

  (2546) 0x4bb0b0 LDR	X14, [X20, X13,LSL #3]

  (2546) 0x4bb0b4 LDR	X2, [X21, X14,LSL #3]

  (2546) 0x4bb0b8 CMP	X2, X30

  (2546) 0x4bb0bc B.NE	4bb0d4

  (2546) 0x4bb0c0 LDR	D1, [X22, X13,LSL #3]

  (2546) 0x4bb0c4 LDR	D4, [X19, X3,LSL #3]

  (2546) 0x4bb0c8 FABS	D5, D1

  (2546) 0x4bb0cc FADD	D6, D4, D5

  (2546) 0x4bb0d0 STR	D6, [X19, X3,LSL #3]

  (2546) 0x4bb0d4 ADD	X15, X0, #3

  (2546) 0x4bb0d8 LDR	X1, [X20, X15,LSL #3]

  (2546) 0x4bb0dc LDR	X16, [X21, X1,LSL #3]

  (2546) 0x4bb0e0 CMP	X16, X30

  (2546) 0x4bb0e4 B.NE	4bb0fc

  (2546) 0x4bb0e8 LDR	D7, [X22, X15,LSL #3]

  (2546) 0x4bb0ec LDR	D16, [X19, X3,LSL #3]

  (2546) 0x4bb0f0 FABS	D17, D7

  (2546) 0x4bb0f4 FADD	D18, D16, D17

  (2546) 0x4bb0f8 STR	D18, [X19, X3,LSL #3]

  (2546) 0x4bb0fc ADD	X18, X0, #4

  (2546) 0x4bb100 LDR	X17, [X20, X18,LSL #3]

  (2546) 0x4bb104 LDR	X11, [X21, X17,LSL #3]

  (2546) 0x4bb108 CMP	X11, X30

  (2546) 0x4bb10c B.NE	4bb124

  (2546) 0x4bb110 LDR	D19, [X22, X18,LSL #3]

  (2546) 0x4bb114 LDR	D20, [X19, X3,LSL #3]

  (2546) 0x4bb118 FABS	D21, D19

  (2546) 0x4bb11c FADD	D29, D20, D21

  (2546) 0x4bb120 STR	D29, [X19, X3,LSL #3]

  (2546) 0x4bb124 ADD	X13, X0, #5

  (2546) 0x4bb128 LDR	X14, [X20, X13,LSL #3]

  (2546) 0x4bb12c LDR	X2, [X21, X14,LSL #3]

  (2546) 0x4bb130 CMP	X2, X30

  (2546) 0x4bb134 B.NE	4bb14c

  (2546) 0x4bb138 LDR	D22, [X22, X13,LSL #3]

  (2546) 0x4bb13c LDR	D0, [X19, X3,LSL #3]

  (2546) 0x4bb140 FABS	D23, D22

  (2546) 0x4bb144 FADD	D24, D0, D23

  (2546) 0x4bb148 STR	D24, [X19, X3,LSL #3]

  (2546) 0x4bb14c ADD	X15, X0, #6

  (2546) 0x4bb150 LDR	X1, [X20, X15,LSL #3]

  (2546) 0x4bb154 LDR	X16, [X21, X1,LSL #3]

  (2546) 0x4bb158 CMP	X16, X30

  (2546) 0x4bb15c B.NE	4bb174

  (2546) 0x4bb160 LDR	D25, [X22, X15,LSL #3]

  (2546) 0x4bb164 LDR	D26, [X19, X3,LSL #3]

  (2546) 0x4bb168 FABS	D27, D25

  (2546) 0x4bb16c FADD	D28, D26, D27

  (2546) 0x4bb170 STR	D28, [X19, X3,LSL #3]

  (2546) 0x4bb174 ADD	X0, X0, #7

  (2546) 0x4bb178 CMP	X0, X5

  (2546) 0x4bb17c B.NE	4bb038

0x4bb180 CBNZ	X26, 4bc290

0x4bb184 ADD	X3, X3, #1

0x4bb188 CMP	X3, X23

0x4bb18c B.EQ	4bac28

0x4bb190 STR	XZR, [X19, X3,LSL #3]

0x4bb194 LDR	X0, [X24, X3,LSL #3]

0x4bb198 LDR	X5, [X27, X3,LSL #3]

0x4bb19c CBNZ	X21, 4baf48

0x4bc248 LDR	D7, [X22, X0,LSL #3]

0x4bc24c LDR	D16, [X19, X3,LSL #3]

0x4bc250 FABS	D17, D7

0x4bc254 FADD	D18, D16, D17

0x4bc258 STR	D18, [X19, X3,LSL #3]

0x4bc25c B	4bb004

0x4bc260 LDR	D1, [X22, X0,LSL #3]

0x4bc264 LDR	D4, [X19, X3,LSL #3]

0x4bc268 FABS	D5, D1

0x4bc26c FADD	D6, D4, D5

0x4bc270 STR	D6, [X19, X3,LSL #3]

0x4bc274 B	4baff0

0x4bc278 LDR	D30, [X22, X0,LSL #3]

0x4bc27c LDR	D31, [X19, X3,LSL #3]

0x4bc280 FABS	D2, D30

0x4bc284 FADD	D3, D31, D2

0x4bc288 STR	D3, [X19, X3,LSL #3]

0x4bc28c B	4bafdc

0x4bc290 LDR	X14, [X8, X3,LSL #3]

0x4bc294 LDR	X5, [X12, X3,LSL #3]

0x4bc298 CMP	X5, X14

0x4bc29c B.LE	4bb184

0x4bc2a0 SUB	X18, X5, X14

0x4bc2a4 ANDS	X17, X18, #4224

0x4bc2a8 B.EQ	4bc384

0x4bc2ac CMP	X17, #1

0x4bc2b0 B.EQ	4bc354

0x4bc2b4 CMP	X17, #2

0x4bc2b8 B.EQ	4bc340

0x4bc2bc CMP	X17, #3

0x4bc2c0 B.EQ	4bc32c

0x4bc2c4 CMP	X17, #4

0x4bc2c8 B.EQ	4bc318

0x4bc2cc CMP	X17, #5

0x4bc2d0 B.EQ	4bc304

0x4bc2d4 CMP	X17, #6

0x4bc2d8 B.EQ	4bc2f0

0x4bc2dc LDR	X11, [X4, X14,LSL #3]

0x4bc2e0 LDR	X13, [X28, X11,LSL #3]

0x4bc2e4 CMP	X13, X30

0x4bc2e8 B.EQ	4be358

0x4bc2ec ADD	X14, X14, #1

0x4bc2f0 LDR	X2, [X4, X14,LSL #3]

0x4bc2f4 LDR	X15, [X28, X2,LSL #3]

0x4bc2f8 CMP	X15, X30

0x4bc2fc B.EQ	4be220

0x4bc300 ADD	X14, X14, #1

0x4bc304 LDR	X1, [X4, X14,LSL #3]

0x4bc308 LDR	X16, [X28, X1,LSL #3]

0x4bc30c CMP	X16, X30

0x4bc310 B.EQ	4be128

0x4bc314 ADD	X14, X14, #1

0x4bc318 LDR	X0, [X4, X14,LSL #3]

0x4bc31c LDR	X18, [X28, X0,LSL #3]

0x4bc320 CMP	X18, X30

0x4bc324 B.EQ	4be008

0x4bc328 ADD	X14, X14, #1

0x4bc32c LDR	X17, [X4, X14,LSL #3]

0x4bc330 LDR	X11, [X28, X17,LSL #3]

0x4bc334 CMP	X11, X30

0x4bc338 B.EQ	4bcfdc

0x4bc33c ADD	X14, X14, #1

0x4bc340 LDR	X13, [X4, X14,LSL #3]

0x4bc344 LDR	X2, [X28, X13,LSL #3]

0x4bc348 CMP	X2, X30

0x4bc34c B.EQ	4bcf34

0x4bc350 ADD	X14, X14, #1

0x4bc354 LDR	X15, [X4, X14,LSL #3]

0x4bc358 LDR	X1, [X28, X15,LSL #3]

0x4bc35c CMP	X1, X30

0x4bc360 B.NE	4bc378

0x4bc364 LDR	D30, [X7, X14,LSL #3]

0x4bc368 LDR	D31, [X19, X3,LSL #3]

0x4bc36c FABS	D2, D30

0x4bc370 FADD	D3, D31, D2

0x4bc374 STR	D3, [X19, X3,LSL #3]

0x4bc378 ADD	X14, X14, #1

0x4bc37c CMP	X14, X5

0x4bc380 B.EQ	4bb184

  (2545) 0x4bc384 LDR	X16, [X4, X14,LSL #3]

  (2545) 0x4bc388 LDR	X0, [X28, X16,LSL #3]

  (2545) 0x4bc38c CMP	X0, X30

  (2545) 0x4bc390 B.NE	4bc3a8

  (2545) 0x4bc394 LDR	D1, [X7, X14,LSL #3]

  (2545) 0x4bc398 LDR	D4, [X19, X3,LSL #3]

  (2545) 0x4bc39c FABS	D5, D1

  (2545) 0x4bc3a0 FADD	D6, D4, D5

  (2545) 0x4bc3a4 STR	D6, [X19, X3,LSL #3]

  (2545) 0x4bc3a8 ADD	X18, X14, #1

  (2545) 0x4bc3ac LDR	X14, [X4, X18,LSL #3]

  (2545) 0x4bc3b0 LDR	X17, [X28, X14,LSL #3]

  (2545) 0x4bc3b4 CMP	X17, X30

  (2545) 0x4bc3b8 B.NE	4bc3d0

  (2545) 0x4bc3bc LDR	D7, [X7, X18,LSL #3]

  (2545) 0x4bc3c0 LDR	D16, [X19, X3,LSL #3]

  (2545) 0x4bc3c4 FABS	D17, D7

  (2545) 0x4bc3c8 FADD	D18, D16, D17

  (2545) 0x4bc3cc STR	D18, [X19, X3,LSL #3]

  (2545) 0x4bc3d0 ADD	X11, X18, #1

  (2545) 0x4bc3d4 LDR	X13, [X4, X11,LSL #3]

  (2545) 0x4bc3d8 LDR	X2, [X28, X13,LSL #3]

  (2545) 0x4bc3dc CMP	X2, X30

  (2545) 0x4bc3e0 B.NE	4bc3f8

  (2545) 0x4bc3e4 LDR	D19, [X7, X11,LSL #3]

  (2545) 0x4bc3e8 LDR	D20, [X19, X3,LSL #3]

  (2545) 0x4bc3ec FABS	D21, D19

  (2545) 0x4bc3f0 FADD	D29, D20, D21

  (2545) 0x4bc3f4 STR	D29, [X19, X3,LSL #3]

  (2545) 0x4bc3f8 ADD	X15, X18, #2

  (2545) 0x4bc3fc LDR	X1, [X4, X15,LSL #3]

  (2545) 0x4bc400 LDR	X16, [X28, X1,LSL #3]

  (2545) 0x4bc404 CMP	X16, X30

  (2545) 0x4bc408 B.NE	4bc420

  (2545) 0x4bc40c LDR	D22, [X7, X15,LSL #3]

  (2545) 0x4bc410 LDR	D0, [X19, X3,LSL #3]

  (2545) 0x4bc414 FABS	D23, D22

  (2545) 0x4bc418 FADD	D24, D0, D23

  (2545) 0x4bc41c STR	D24, [X19, X3,LSL #3]

  (2545) 0x4bc420 ADD	X0, X18, #3

  (2545) 0x4bc424 LDR	X14, [X4, X0,LSL #3]

  (2545) 0x4bc428 LDR	X17, [X28, X14,LSL #3]

  (2545) 0x4bc42c CMP	X17, X30

  (2545) 0x4bc430 B.NE	4bc448

  (2545) 0x4bc434 LDR	D25, [X7, X0,LSL #3]

  (2545) 0x4bc438 LDR	D26, [X19, X3,LSL #3]

  (2545) 0x4bc43c FABS	D27, D25

  (2545) 0x4bc440 FADD	D28, D26, D27

  (2545) 0x4bc444 STR	D28, [X19, X3,LSL #3]

  (2545) 0x4bc448 ADD	X11, X18, #4

  (2545) 0x4bc44c LDR	X13, [X4, X11,LSL #3]

  (2545) 0x4bc450 LDR	X2, [X28, X13,LSL #3]

  (2545) 0x4bc454 CMP	X2, X30

  (2545) 0x4bc458 B.NE	4bc470

  (2545) 0x4bc45c LDR	D30, [X7, X11,LSL #3]

  (2545) 0x4bc460 LDR	D31, [X19, X3,LSL #3]

  (2545) 0x4bc464 FABS	D2, D30

  (2545) 0x4bc468 FADD	D3, D31, D2

  (2545) 0x4bc46c STR	D3, [X19, X3,LSL #3]

  (2545) 0x4bc470 ADD	X15, X18, #5

  (2545) 0x4bc474 LDR	X1, [X4, X15,LSL #3]

  (2545) 0x4bc478 LDR	X16, [X28, X1,LSL #3]

  (2545) 0x4bc47c CMP	X16, X30

  (2545) 0x4bc480 B.NE	4bc498

  (2545) 0x4bc484 LDR	D1, [X7, X15,LSL #3]

  (2545) 0x4bc488 LDR	D4, [X19, X3,LSL #3]

  (2545) 0x4bc48c FABS	D5, D1

  (2545) 0x4bc490 FADD	D6, D4, D5

  (2545) 0x4bc494 STR	D6, [X19, X3,LSL #3]

  (2545) 0x4bc498 ADD	X0, X18, #6

  (2545) 0x4bc49c LDR	X14, [X4, X0,LSL #3]

  (2545) 0x4bc4a0 LDR	X17, [X28, X14,LSL #3]

  (2545) 0x4bc4a4 CMP	X17, X30

  (2545) 0x4bc4a8 B.NE	4bc4c0

  (2545) 0x4bc4ac LDR	D7, [X7, X0,LSL #3]

  (2545) 0x4bc4b0 LDR	D16, [X19, X3,LSL #3]

  (2545) 0x4bc4b4 FABS	D17, D7

  (2545) 0x4bc4b8 FADD	D18, D16, D17

  (2545) 0x4bc4bc STR	D18, [X19, X3,LSL #3]

  (2545) 0x4bc4c0 ADD	X14, X18, #7

  (2545) 0x4bc4c4 CMP	X14, X5

  (2545) 0x4bc4c8 B.NE	4bc384

0x4bc4cc B	4bb184

0x4bce44 LDR	D25, [X22, X0,LSL #3]

0x4bce48 LDR	D26, [X19, X3,LSL #3]

0x4bce4c FABS	D27, D25

0x4bce50 FADD	D28, D26, D27

0x4bce54 STR	D28, [X19, X3,LSL #3]

0x4bce58 B	4bafc8

0x4bcf04 LDR	D22, [X22, X0,LSL #3]

0x4bcf08 LDR	D0, [X19, X3,LSL #3]

0x4bcf0c FABS	D23, D22

0x4bcf10 FADD	D24, D0, D23

0x4bcf14 STR	D24, [X19, X3,LSL #3]

0x4bcf18 B	4bafb4

0x4bcf34 LDR	D25, [X7, X14,LSL #3]

0x4bcf38 LDR	D26, [X19, X3,LSL #3]

0x4bcf3c FABS	D27, D25

0x4bcf40 FADD	D28, D26, D27

0x4bcf44 STR	D28, [X19, X3,LSL #3]

0x4bcf48 B	4bc350

0x4bcfdc LDR	D22, [X7, X14,LSL #3]

0x4bcfe0 LDR	D0, [X19, X3,LSL #3]

0x4bcfe4 FABS	D23, D22

0x4bcfe8 FADD	D24, D0, D23

0x4bcfec STR	D24, [X19, X3,LSL #3]

0x4bcff0 B	4bc33c

0x4be008 LDR	D19, [X7, X14,LSL #3]

0x4be00c ADD	X14, X14, #1

0x4be010 LDR	D20, [X19, X3,LSL #3]

0x4be014 FABS	D21, D19

0x4be018 FADD	D29, D20, D21

0x4be01c STR	D29, [X19, X3,LSL #3]

0x4be020 B	4bc32c

0x4be040 LDR	D19, [X22, X0,LSL #3]

0x4be044 ADD	X0, X0, #1

0x4be048 LDR	D20, [X19, X3,LSL #3]

0x4be04c FABS	D21, D19

0x4be050 FADD	D29, D20, D21

0x4be054 STR	D29, [X19, X3,LSL #3]

0x4be058 B	4bafa4

0x4be128 LDR	D7, [X7, X14,LSL #3]

0x4be12c LDR	D16, [X19, X3,LSL #3]

0x4be130 FABS	D17, D7

0x4be134 FADD	D18, D16, D17

0x4be138 STR	D18, [X19, X3,LSL #3]

0x4be13c B	4bc314

0x4be220 LDR	D1, [X7, X14,LSL #3]

0x4be224 LDR	D4, [X19, X3,LSL #3]

0x4be228 FABS	D5, D1

0x4be22c FADD	D6, D4, D5

0x4be230 STR	D6, [X19, X3,LSL #3]

0x4be234 B	4bc300

0x4be358 LDR	D30, [X7, X14,LSL #3]

0x4be35c ADD	X14, X14, #1

0x4be360 LDR	D31, [X19, X3,LSL #3]

0x4be364 FABS	D2, D30

0x4be368 FADD	D3, D31, D2

0x4be36c STR	D3, [X19, X3,LSL #3]

0x4be370 B	4bc2f0

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3382 - 3409

--------------------------------------------------------------------------------

3382:          for (i = ns; i < ne; i++)

3383:          {

3384:             l1_norm[i] = 0.0;

3385:             if (cf_marker == NULL)

[...]

3399:                cf_diag = cf_marker[i];

3400:                /* Add the CF l1 norm of the diag part of the ith row */

3401:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3402:                   if (cf_diag == cf_marker[A_diag_J[j]])

3403:                      l1_norm[i] += fabs(A_diag_data[j]);

3404:                /* Add the CF l1 norm of the offd part of the ith row */

3405:                if (num_cols_offd)

3406:                {

3407:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3408:                      if (cf_diag == cf_marker_offd[A_offd_J[j]])

3409:                         l1_norm[i] += fabs(A_offd_data[j]);

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.83
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.00
Bottlenecks	micro-operation queue,
Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source	ams.c:3382-3385,ams.c:3399-3409
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	25.63
CQA cycles if no scalar integer	14.00
CQA cycles if FP arith vectorized	25.63
CQA cycles if fully vectorized	6.41
Front-end cycles	25.63
DIV/SQRT cycles	24.00
P0 cycles	24.00
P1 cycles	13.25
P2 cycles	13.25
P3 cycles	13.25
P4 cycles	13.25
P5 cycles	10.50
P6 cycles	10.50
P7 cycles	10.50
P8 cycles	10.50
P9 cycles	25.50
P10 cycles	25.17
P11 cycles	25.33
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	205.00
Nb uops	205.00
Nb loads	NA
Nb stores	15.00
Nb stack references	0.00
FLOP/cycle	0.55
Nb FLOP add-sub	14.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.73
Bytes prefetched	0.00
Bytes loaded	488.00
Bytes stored	120.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.83
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.00
Bottlenecks	micro-operation queue,
Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source	ams.c:3382-3385,ams.c:3399-3409
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	25.63
CQA cycles if no scalar integer	14.00
CQA cycles if FP arith vectorized	25.63
CQA cycles if fully vectorized	6.41
Front-end cycles	25.63
DIV/SQRT cycles	24.00
P0 cycles	24.00
P1 cycles	13.25
P2 cycles	13.25
P3 cycles	13.25
P4 cycles	13.25
P5 cycles	10.50
P6 cycles	10.50
P7 cycles	10.50
P8 cycles	10.50
P9 cycles	25.50
P10 cycles	25.17
P11 cycles	25.33
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	205.00
Nb uops	205.00
Nb loads	NA
Nb stores	15.00
Nb stack references	0.00
FLOP/cycle	0.55
Nb FLOP add-sub	14.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.73
Bytes prefetched	0.00
Bytes loaded	488.00
Bytes stored	120.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source file and lines	ams.c:3382-3409
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3382-3385,3399-3409.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.63 to 14.00 cycles (1.83x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 25.63 to 6.41 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 14 FP arithmetical operations:

14: addition or subtraction

The binary loop is loading 488 bytes. The binary loop is storing 120 bytes.

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	205
loop length	820
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

25.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	24.00	24.00	13.25	13.25	13.25	13.25	10.50	10.50	10.50	10.50	25.50	25.17	25.33	0.50	0.50
cycles	24.00	24.00	13.25	13.25	13.25	13.25	10.50	10.50	10.50	10.50	25.50	25.17	25.33	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	25.63
Overall L1	25.63

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 25.63 cycles. At this rate:

19% of peak load performance is reached (19.04 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.68 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4bb184

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X30, [X21, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X5, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4bb180 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xfa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X1, X5, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X16, X1, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bb038 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xe58>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bb008 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xe28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X16, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4baff4 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xe14>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X16, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bafe0 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xe00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X16, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bafcc <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xdec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X16, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bafb8 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xdd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X16, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bafa4 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xdc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X21, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X17, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4be040 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x3e60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X21, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bcf04 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2d24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X13, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X21, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bce44 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2c64>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X15, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X21, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X1, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bc278 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2098>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X16, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X21, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X18, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bc260 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2080>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X17, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X21, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X11, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bc248 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2068>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X21, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X13, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 4bb02c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xe4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D19, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D20, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FABS D21, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D29, D20, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D29, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bb180 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xfa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBNZ X26, 4bc290 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x20b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X3, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bac28 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xa48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR XZR, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X24, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X27, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X21, 4baf48 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xd68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D7, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D16, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FABS D17, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D18, D16, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D18, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
B 4bb004 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xe24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D1, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D4, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FABS D5, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D6, D4, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D6, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
B 4baff0 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xe10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D30, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D31, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FABS D2, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D3, D31, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D3, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
B 4bafdc <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xdfc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [X8, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X12, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X5, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4bb184 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xfa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X18, X5, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X17, X18, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bc384 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x21a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bc354 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X17, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bc340 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X17, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bc32c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x214c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X17, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bc318 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X17, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bc304 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X17, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bc2f0 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X4, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X28, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X13, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4be358 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4178>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X2, [X4, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X28, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X15, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4be220 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4040>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X4, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X28, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X16, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4be128 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x3f48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X4, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X28, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X18, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4be008 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x3e28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X17, [X4, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X28, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X11, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bcfdc <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2dfc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X13, [X4, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X28, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bcf34 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2d54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X15, [X4, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X28, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X1, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 4bc378 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2198>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D30, [X7, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D31, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FABS D2, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D3, D31, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D3, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X14, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bb184 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xfa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 4bb184 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xfa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D25, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D26, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FABS D27, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D28, D26, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D28, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
B 4bafc8 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xde8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D22, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D0, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FABS D23, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D24, D0, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D24, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
B 4bafb4 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xdd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D25, [X7, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D26, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FABS D27, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D28, D26, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D28, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
B 4bc350 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2170>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D22, [X7, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D0, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FABS D23, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D24, D0, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D24, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
B 4bc33c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x215c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D19, [X7, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D20, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FABS D21, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D29, D20, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D29, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
B 4bc32c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x214c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D19, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D20, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FABS D21, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D29, D20, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D29, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
B 4bafa4 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xdc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D7, [X7, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D16, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FABS D17, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D18, D16, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D18, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
B 4bc314 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D1, [X7, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D4, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FABS D5, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D6, D4, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D6, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
B 4bc300 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D30, [X7, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D31, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FABS D2, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D3, D31, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D3, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
B 4bc2f0 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source file and lines	ams.c:3382-3409
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3382-3385,3399-3409.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 14 FP arithmetical operations:

14: addition or subtraction

The binary loop is loading 488 bytes. The binary loop is storing 120 bytes.

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	205
loop length	820
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

25.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	24.00	24.00	13.25	13.25	13.25	13.25	10.50	10.50	10.50	10.50	25.50	25.17	25.33	0.50	0.50
cycles	24.00	24.00	13.25	13.25	13.25	13.25	10.50	10.50	10.50	10.50	25.50	25.17	25.33	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	25.63
Overall L1	25.63

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 25.63 cycles. At this rate:

19% of peak load performance is reached (19.04 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.68 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4bb184

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X30, [X21, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X5, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4bb180 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xfa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X1, X5, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X16, X1, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bb038 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xe58>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bb008 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xe28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X16, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4baff4 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xe14>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X16, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bafe0 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xe00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X16, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bafcc <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xdec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X16, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bafb8 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xdd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X16, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bafa4 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xdc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X21, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X17, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4be040 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x3e60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X21, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bcf04 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2d24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X13, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X21, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bce44 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2c64>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X15, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X21, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X1, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bc278 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2098>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X16, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X21, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X18, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bc260 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2080>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X17, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X21, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X11, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bc248 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2068>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X21, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X13, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 4bb02c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xe4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D19, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D20, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FABS D21, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D29, D20, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D29, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bb180 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xfa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBNZ X26, 4bc290 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x20b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X3, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bac28 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xa48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR XZR, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X24, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X27, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X21, 4baf48 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xd68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D7, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D16, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FABS D17, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D18, D16, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D18, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
B 4bb004 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xe24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D1, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D4, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FABS D5, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D6, D4, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D6, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
B 4baff0 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xe10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D30, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D31, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FABS D2, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D3, D31, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D3, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
B 4bafdc <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xdfc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [X8, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X12, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X5, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4bb184 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xfa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X18, X5, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X17, X18, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bc384 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x21a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bc354 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X17, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bc340 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X17, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bc32c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x214c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X17, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bc318 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X17, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bc304 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X17, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bc2f0 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X4, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X28, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X13, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4be358 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4178>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X2, [X4, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X28, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X15, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4be220 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4040>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X4, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X28, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X16, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4be128 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x3f48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X4, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X28, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X18, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4be008 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x3e28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X17, [X4, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X28, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X11, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bcfdc <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2dfc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X13, [X4, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X28, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bcf34 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2d54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X15, [X4, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X28, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X1, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 4bc378 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2198>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D30, [X7, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D31, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FABS D2, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D3, D31, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D3, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X14, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4bb184 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xfa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 4bb184 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xfa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D25, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D26, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FABS D27, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D28, D26, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D28, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
B 4bafc8 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xde8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D22, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D0, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FABS D23, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D24, D0, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D24, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
B 4bafb4 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xdd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D25, [X7, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D26, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FABS D27, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D28, D26, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D28, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
B 4bc350 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2170>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D22, [X7, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D0, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FABS D23, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D24, D0, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D24, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
B 4bc33c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x215c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D19, [X7, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D20, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FABS D21, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D29, D20, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D29, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
B 4bc32c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x214c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D19, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D20, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FABS D21, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D29, D20, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D29, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
B 4bafa4 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xdc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D7, [X7, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D16, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FABS D17, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D18, D16, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D18, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
B 4bc314 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D1, [X7, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D4, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FABS D5, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D6, D4, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D6, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
B 4bc300 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D30, [X7, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D31, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FABS D2, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D3, D31, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D3, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
B 4bc2f0 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code