OV - exec - Loop 2526

	Loop Id: 2526	Module: exec	Source: ams.c:3532-3534	Coverage: 0.04%

0x4bad18 LDR	X12, [X24, X0,LSL #3]    [18]

0x4bad1c LDR	D22, [X22, X12,LSL #3]    [20]

0x4bad20 FCMPE	D22, #0

0x4bad24 B.MI	4bc228

0x4bad28 ADD	X0, X0, #1

0x4bad2c LDR	X3, [X24, X0,LSL #3]    [12]

0x4bad30 LDR	D2, [X22, X3,LSL #3]    [16]

0x4bad34 FCMPE	D2, #0

0x4bad38 B.MI	4bc218

0x4bad3c ADD	X16, X0, #1

0x4bad40 LDR	X1, [X24, X16,LSL #3]    [9]

0x4bad44 LDR	D26, [X22, X1,LSL #3]    [6]

0x4bad48 FCMPE	D26, #0

0x4bad4c B.MI	4bc208

0x4bad50 ADD	X17, X0, #2

0x4bad54 LDR	X14, [X24, X17,LSL #3]    [22]

0x4bad58 LDR	D30, [X22, X14,LSL #3]    [11]

0x4bad5c FCMPE	D30, #0

0x4bad60 B.MI	4bc1f8

0x4bad64 ADD	X30, X0, #3

0x4bad68 LDR	X5, [X24, X30,LSL #3]    [19]

0x4bad6c LDR	D4, [X22, X5,LSL #3]    [10]

0x4bad70 FCMPE	D4, #0

0x4bad74 B.MI	4bc1e8

0x4bad78 ADD	X18, X0, #4

0x4bad7c LDR	X11, [X24, X18,LSL #3]    [5]

0x4bad80 LDR	D6, [X22, X11,LSL #3]    [3]

0x4bad84 FCMPE	D6, #0

0x4bad88 B.MI	4bc1d8

0x4bad8c ADD	X13, X0, #5

0x4bad90 LDR	X2, [X24, X13,LSL #3]    [21]

0x4bad94 LDR	D17, [X22, X2,LSL #3]    [14]

0x4bad98 FCMPE	D17, #0

0x4bad9c B.MI	4bc1c8

0x4bada0 ADD	X15, X0, #6

0x4bada4 LDR	X12, [X24, X15,LSL #3]    [2]

0x4bada8 LDR	D20, [X22, X12,LSL #3]    [15]

0x4badac FCMPE	D20, #0

0x4badb0 B.MI	4bc1b8

0x4badb4 ADD	X0, X0, #7

0x4badb8 CMP	X0, X23

0x4badbc B.LT	4bad18

0x4bc1b8 LDR	D21, [X19, X15,LSL #3]    [4]

0x4bc1bc FNEG	D29, D21

0x4bc1c0 STR	D29, [X19, X15,LSL #3]    [4]

0x4bc1c4 B	4badb4

0x4bc1c8 LDR	D18, [X19, X13,LSL #3]    [24]

0x4bc1cc FNEG	D19, D18

0x4bc1d0 STR	D19, [X19, X13,LSL #3]    [24]

0x4bc1d4 B	4bada0

0x4bc1d8 LDR	D7, [X19, X18,LSL #3]    [8]

0x4bc1dc FNEG	D16, D7

0x4bc1e0 STR	D16, [X19, X18,LSL #3]    [8]

0x4bc1e4 B	4bad8c

0x4bc1e8 LDR	D1, [X19, X30,LSL #3]    [23]

0x4bc1ec FNEG	D5, D1

0x4bc1f0 STR	D5, [X19, X30,LSL #3]    [23]

0x4bc1f4 B	4bad78

0x4bc1f8 LDR	D31, [X19, X17,LSL #3]    [1]

0x4bc1fc FNEG	D3, D31

0x4bc200 STR	D3, [X19, X17,LSL #3]    [1]

0x4bc204 B	4bad64

0x4bc208 LDR	D27, [X19, X16,LSL #3]    [7]

0x4bc20c FNEG	D28, D27

0x4bc210 STR	D28, [X19, X16,LSL #3]    [7]

0x4bc214 B	4bad50

0x4bc218 LDR	D24, [X19, X0,LSL #3]    [17]

0x4bc21c FNEG	D25, D24

0x4bc220 STR	D25, [X19, X0,LSL #3]    [17]

0x4bc224 B	4bad3c

0x4bc228 LDR	D0, [X19, X0,LSL #3]    [13]

0x4bc22c FNEG	D23, D0

0x4bc230 STR	D23, [X19, X0,LSL #3]    [13]

0x4bc234 B	4bad28

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3532 - 3534

--------------------------------------------------------------------------------

3532:       for (i = ns; i < ne; i++)

3533:          if (A_diag_data[A_diag_I[i]] < 0)

3534:             l1_norm[i] = -l1_norm[i];

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.33
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.15
Bottlenecks	P10, P11, P12,
Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source	ams.c:3532-3534
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.67
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	10.67
CQA cycles if fully vectorized	2.67
Front-end cycles	9.25
DIV/SQRT cycles	8.50
P0 cycles	8.50
P1 cycles	2.25
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.25
P5 cycles	8.00
P6 cycles	8.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	10.67
P10 cycles	10.67
P11 cycles	10.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	74.00
Nb uops	74.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.33
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.15
Bottlenecks	P10, P11, P12,
Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source	ams.c:3532-3534
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.67
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	10.67
CQA cycles if fully vectorized	2.67
Front-end cycles	9.25
DIV/SQRT cycles	8.50
P0 cycles	8.50
P1 cycles	2.25
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.25
P5 cycles	8.00
P6 cycles	8.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	10.67
P10 cycles	10.67
P11 cycles	10.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	74.00
Nb uops	74.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source file and lines	ams.c:3532-3534
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3532-3534.

The related source loop is multi-versionned.
Warnings:

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 256 paths individually, rerun with max-paths=256
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 256 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.67 to 8.00 cycles (1.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 10.67 to 2.67 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 192 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	74
loop length	296
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	8.50	8.50	2.25	2.25	2.25	2.25	8.00	8.00	4.00	4.00	10.67	10.67	10.67	0.00	0.00
cycles	8.50	8.50	2.25	2.25	2.25	2.25	8.00	8.00	4.00	4.00	10.67	10.67	10.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.25
Overall L1	10.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.67 cycles. At this rate:

18% of peak load performance is reached (18.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4bad18

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR X12, [X24, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D22, [X22, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D22, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 4bc228 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2048>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X3, [X24, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D2, [X22, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D2, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 4bc218 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2038>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X16, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X1, [X24, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D26, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D26, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 4bc208 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2028>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X17, X0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X14, [X24, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D30, [X22, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D30, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 4bc1f8 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2018>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X30, X0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X5, [X24, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D4, [X22, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D4, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 4bc1e8 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2008>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X18, X0, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X11, [X24, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D6, [X22, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D6, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 4bc1d8 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1ff8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X13, X0, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X2, [X24, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D17, [X22, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D17, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 4bc1c8 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1fe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X15, X0, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X12, [X24, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D20, [X22, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D20, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 4bc1b8 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1fd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X0, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LT 4bad18 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xb38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D21, [X19, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D29, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D29, [X19, X15,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B 4badb4 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xbd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D18, [X19, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D19, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D19, [X19, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B 4bada0 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xbc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D7, [X19, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D16, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D16, [X19, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B 4bad8c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xbac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D1, [X19, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D5, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D5, [X19, X30,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B 4bad78 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xb98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D31, [X19, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D3, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D3, [X19, X17,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B 4bad64 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xb84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D27, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D28, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D28, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B 4bad50 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xb70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D24, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D25, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D25, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B 4bad3c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xb5c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D23, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D23, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B 4bad28 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xb48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source file and lines	ams.c:3532-3534
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3532-3534.

The related source loop is multi-versionned.
Warnings:

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 256 paths individually, rerun with max-paths=256
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.67 to 8.00 cycles (1.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 192 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	74
loop length	296
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	8.50	8.50	2.25	2.25	2.25	2.25	8.00	8.00	4.00	4.00	10.67	10.67	10.67	0.00	0.00
cycles	8.50	8.50	2.25	2.25	2.25	2.25	8.00	8.00	4.00	4.00	10.67	10.67	10.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.25
Overall L1	10.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.67 cycles. At this rate:

18% of peak load performance is reached (18.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4bad18

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR X12, [X24, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D22, [X22, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D22, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 4bc228 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2048>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X3, [X24, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D2, [X22, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D2, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 4bc218 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2038>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X16, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X1, [X24, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D26, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D26, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 4bc208 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2028>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X17, X0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X14, [X24, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D30, [X22, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D30, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 4bc1f8 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2018>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X30, X0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X5, [X24, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D4, [X22, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D4, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 4bc1e8 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x2008>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X18, X0, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X11, [X24, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D6, [X22, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D6, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 4bc1d8 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1ff8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X13, X0, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X2, [X24, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D17, [X22, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D17, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 4bc1c8 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1fe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X15, X0, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X12, [X24, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D20, [X22, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D20, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 4bc1b8 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1fd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X0, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LT 4bad18 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xb38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D21, [X19, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D29, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D29, [X19, X15,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B 4badb4 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xbd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D18, [X19, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D19, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D19, [X19, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B 4bada0 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xbc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D7, [X19, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D16, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D16, [X19, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B 4bad8c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xbac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D1, [X19, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D5, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D5, [X19, X30,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B 4bad78 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xb98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D31, [X19, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D3, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D3, [X19, X17,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B 4bad64 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xb84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D27, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D28, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D28, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B 4bad50 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xb70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D24, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D25, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D25, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B 4bad3c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xb5c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D23, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D23, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B 4bad28 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0xb48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code