OV - exec - Loop 2339

	Loop Id: 2339	Module: exec	Source: par_strength.c:1268-1278	Coverage: 0.07%

0x4acff0 ADD	X8, X4, #1

0x4acff4 STR	X1, [X20, X4,LSL #3]    [4]

0x4acff8 STR	X4, [X22, X1,LSL #3]    [7]

0x4acffc ADD	X1, X1, #1

0x4ad000 LDR	X9, [X19, X8,LSL #3]    [15]

0x4ad004 CMP	X9, #0

0x4ad008 B.LE	4ad0e4

0x4ad028 ADD	X21, X4, #3

0x4ad02c STR	X1, [X20, X2,LSL #3]    [3]

0x4ad030 STR	X2, [X22, X1,LSL #3]    [6]

0x4ad034 ADD	X1, X1, #1

0x4ad038 LDR	X5, [X19, X21,LSL #3]    [8]

0x4ad03c CMP	X5, #0

0x4ad040 B.LE	4ad10c

0x4ad060 ADD	X12, X4, #5

0x4ad064 STR	X1, [X20, X23,LSL #3]    [20]

0x4ad068 STR	X23, [X22, X1,LSL #3]    [10]

0x4ad06c ADD	X1, X1, #1

0x4ad070 LDR	X13, [X19, X12,LSL #3]    [17]

0x4ad074 CMP	X13, #0

0x4ad078 B.LE	4ad134

0x4ad098 STR	X1, [X20, X14,LSL #3]    [11]

0x4ad09c STR	X14, [X22, X1,LSL #3]    [1]

0x4ad0a0 ADD	X1, X1, #1

0x4ad0a4 ADD	X4, X4, #7

0x4ad0a8 CMP	X4, X6

0x4ad0ac B.EQ	4acfa4

0x4ad0b0 LDR	X3, [X19, X4,LSL #3]    [16]

0x4ad0b4 CMP	X3, #0

0x4ad0b8 B.GT	4acfd4

0x4ad0bc STR	X11, [X20, X4,LSL #3]    [5]

0x4ad0c0 ADD	X4, X4, #1

0x4ad0c4 LDR	X7, [X19, X4,LSL #3]    [18]

0x4ad0c8 CMP	X7, #0

0x4ad0cc B.GT	4acff0

0x4ad0e4 ADD	X2, X4, #2

0x4ad0e8 STR	X11, [X20, X8,LSL #3]    [2]

0x4ad0ec LDR	X0, [X19, X2,LSL #3]    [14]

0x4ad0f0 CMP	X0, #0

0x4ad0f4 B.GT	4ad028

0x4ad10c ADD	X23, X4, #4

0x4ad110 STR	X11, [X20, X21,LSL #3]    [13]

0x4ad114 LDR	X10, [X19, X23,LSL #3]    [19]

0x4ad118 CMP	X10, #0

0x4ad11c B.GT	4ad060

0x4ad134 ADD	X14, X4, #6

0x4ad138 STR	X11, [X20, X12,LSL #3]    [9]

0x4ad13c LDR	X15, [X19, X14,LSL #3]    [12]

0x4ad140 CMP	X15, #0

0x4ad144 B.GT	4ad098

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 1268 - 1278

--------------------------------------------------------------------------------

1268:       for (i = i_begin; i < i_end; i++)

1269:       {

1270:          if (CF_marker[i] > 0)

1271:          {

1272:             fine_to_coarse[i] = num_coarse_private;

1273:             coarse_to_fine[num_coarse_private] = i;

1274:             num_coarse_private++;

1275:          }

1276:          else

1277:          {

1278:             fine_to_coarse[i] = -1;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGCreate2ndS._omp_fn.0
Source	par_strength.c:1268-1278
Source loop unroll info	unrolled by 12
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	12
CQA cycles	6.67
CQA cycles if no scalar integer	6.67
CQA cycles if FP arith vectorized	6.67
CQA cycles if fully vectorized	1.67
Front-end cycles	6.25
DIV/SQRT cycles	4.50
P0 cycles	4.50
P1 cycles	5.25
P2 cycles	5.25
P3 cycles	5.25
P4 cycles	5.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	6.67
P10 cycles	6.67
P11 cycles	6.67
P12 cycles	6.00
P13 cycles	6.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	50.00
Nb uops	50.00
Nb loads	NA
Nb stores	12.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	96.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGCreate2ndS._omp_fn.0
Source	par_strength.c:1268-1278
Source loop unroll info	unrolled by 12
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	12
CQA cycles	6.67
CQA cycles if no scalar integer	6.67
CQA cycles if FP arith vectorized	6.67
CQA cycles if fully vectorized	1.67
Front-end cycles	6.25
DIV/SQRT cycles	4.50
P0 cycles	4.50
P1 cycles	5.25
P2 cycles	5.25
P3 cycles	5.25
P4 cycles	5.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	6.67
P10 cycles	6.67
P11 cycles	6.67
P12 cycles	6.00
P13 cycles	6.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	50.00
Nb uops	50.00
Nb loads	NA
Nb stores	12.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	96.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGCreate2ndS._omp_fn.0
Source file and lines	par_strength.c:1268-1278
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1268-1278.

The related source loop is unrolled by 12 (including vectorization).
Warnings:

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.67 to 1.67 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 96 bytes.

General properties

nb instructions	50
loop length	200
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	6.67	6.67	6.67	6.00	6.00
cycles	4.50	4.50	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	6.67	6.67	6.67	6.00	6.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.25
Overall L1	6.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.67 cycles. At this rate:

10% of peak load performance is reached (9.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
30% of peak store performance is reached (14.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4ad0a4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADD X8, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X1, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X9, [X19, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4ad0e4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x484>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X21, X4, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X1, [X20, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X2, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X5, [X19, X21,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4ad10c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X12, X4, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X1, [X20, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X23, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X13, [X19, X12,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4ad134 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X1, [X20, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X14, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X4, #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X4, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4acfa4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x344>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X3, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 4acfd4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x374>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X11, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X7, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 4acff0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X2, X4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X20, X8,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 4ad028 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x3c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X23, X4, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X20, X21,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X19, X23,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 4ad060 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x400>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X14, X4, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X20, X12,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [X19, X14,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 4ad098 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x438>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_BoomerAMGCreate2ndS._omp_fn.0
Source file and lines	par_strength.c:1268-1278
Module	exec

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.67 to 1.67 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 96 bytes.

General properties

nb instructions	50
loop length	200
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	6.67	6.67	6.67	6.00	6.00
cycles	4.50	4.50	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	6.67	6.67	6.67	6.00	6.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.25
Overall L1	6.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.67 cycles. At this rate:

10% of peak load performance is reached (9.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
30% of peak store performance is reached (14.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4ad0a4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADD X8, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X1, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X9, [X19, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4ad0e4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x484>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X21, X4, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X1, [X20, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X2, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X5, [X19, X21,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4ad10c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X12, X4, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X1, [X20, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X23, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X13, [X19, X12,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4ad134 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X1, [X20, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X14, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X4, #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X4, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4acfa4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x344>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X3, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 4acfd4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x374>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X11, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X7, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 4acff0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X2, X4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X20, X8,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 4ad028 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x3c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X23, X4, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X20, X21,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X19, X23,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 4ad060 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x400>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X14, X4, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X20, X12,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [X19, X14,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 4ad098 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x438>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code