OV - exec - Loop 2319

0x4ac634 LDR	X20, [SP, #128]

0x4ac638 LDR	X0, [SP, #144]

0x4ac63c LDR	X3, [SP, #176]

0x4ac640 LDR	X22, [X20, X9,LSL #3]

0x4ac644 STR	X11, [X0, X9,LSL #3]

0x4ac648 LDR	X10, [X3]

0x4ac64c STR	X22, [SP, #120]

0x4ac650 CBZ	X10, 4ac65c

0x4ac654 LDR	X14, [SP, #192]

0x4ac658 STR	X6, [X14, X9,LSL #3]

0x4ac65c LDR	X12, [SP, #120]

0x4ac660 ORR	X4, XZR, X11

0x4ac664 ORR	X2, XZR, X6

0x4ac668 UBFM	X5, X12, #61, #60

0x4ac66c LDR	X14, [X18, X12,LSL #3]

0x4ac670 ADD	X3, X5, #8

0x4ac674 ORR	X5, XZR, X27

0x4ac678 LDR	X1, [X18, X3]

0x4ac67c ADD	X22, X18, X3

0x4ac680 CMP	X14, X1

0x4ac684 B.GE	4ac794

  (2323) 0x4ac688 LDR	X20, [X26, X14,LSL #3]

  (2323) 0x4ac68c LDR	X27, [X23, X20,LSL #3]

  (2323) 0x4ac690 UBFM	X10, X20, #61, #60

  (2323) 0x4ac694 CMP	X27, #0

  (2323) 0x4ac698 B.LE	4ac6b8

  (2323) 0x4ac69c LDR	X0, [X8, X20,LSL #3]

  (2323) 0x4ac6a0 LDR	X12, [X21, X0,LSL #3]

  (2323) 0x4ac6a4 CMP	X12, X11

  (2323) 0x4ac6a8 B.GE	4ac6b8

  (2323) 0x4ac6ac MOVZ	W30, #1

  (2323) 0x4ac6b0 STR	X4, [X21, X0,LSL #3]

  (2323) 0x4ac6b4 ADD	X4, X4, #1

  (2323) 0x4ac6b8 ADD	X12, X10, #8

  (2323) 0x4ac6bc LDR	X0, [X18, X20,LSL #3]

  (2323) 0x4ac6c0 ADD	X27, X18, X12

  (2323) 0x4ac6c4 LDR	X10, [X18, X12]

  (2323) 0x4ac6c8 CMP	X0, X10

  (2323) 0x4ac6cc B.GE	4ac730

  (2323) 0x4ac6d0 STR	X2, [SP, #112]

  (2323) 0x4ac6d4 HINT	#0

  (2323) 0x4ac6d8 HINT	#0

  (2323) 0x4ac6dc HINT	#0

    (2325) 0x4ac6e0 LDR	X1, [X26, X0,LSL #3]

    (2325) 0x4ac6e4 LDR	X2, [X23, X1,LSL #3]

    (2325) 0x4ac6e8 CMP	X2, #0

    (2325) 0x4ac6ec B.LE	4ac720

    (2325) 0x4ac6f0 LDR	X1, [X8, X1,LSL #3]

    (2325) 0x4ac6f4 CMP	X1, X9

    (2325) 0x4ac6f8 B.EQ	4ac720

    (2325) 0x4ac6fc LDR	X2, [X21, X1,LSL #3]

    (2325) 0x4ac700 CMP	X11, X2

    (2325) 0x4ac704 B.LE	4ac720

    (2325) 0x4ac708 STR	X4, [X21, X1,LSL #3]

    (2325) 0x4ac70c MOVZ	W30, #1

    (2325) 0x4ac710 ADD	X4, X4, #1

    (2325) 0x4ac714 LDR	X10, [X27]

    (2325) 0x4ac718 HINT	#0

    (2325) 0x4ac71c HINT	#0

    (2325) 0x4ac720 ADD	X0, X0, #1

    (2325) 0x4ac724 CMP	X0, X10

    (2325) 0x4ac728 B.LT	4ac6e0

  (2323) 0x4ac72c LDR	X2, [SP, #112]

  (2323) 0x4ac730 LDR	X0, [X15, X20,LSL #3]

  (2323) 0x4ac734 ADD	X20, X15, X12

  (2323) 0x4ac738 LDR	X10, [X15, X12]

  (2323) 0x4ac73c CMP	X0, X10

  (2323) 0x4ac740 B.GE	4ac780

    (2324) 0x4ac744 LDR	X27, [X25, X0,LSL #3]

    (2324) 0x4ac748 LDR	X12, [X24, X27,LSL #3]

    (2324) 0x4ac74c CMP	X12, #0

    (2324) 0x4ac750 B.LE	4ac774

    (2324) 0x4ac754 LDR	X1, [X7, X27,LSL #3]

    (2324) 0x4ac758 LDR	X27, [X19, X1,LSL #3]

    (2324) 0x4ac75c CMP	X27, X6

    (2324) 0x4ac760 B.GE	4ac774

    (2324) 0x4ac764 STR	X2, [X19, X1,LSL #3]

    (2324) 0x4ac768 MOVZ	W13, #1

    (2324) 0x4ac76c ADD	X2, X2, #1

    (2324) 0x4ac770 LDR	X10, [X20]

    (2324) 0x4ac774 ADD	X0, X0, #1

    (2324) 0x4ac778 CMP	X0, X10

    (2324) 0x4ac77c B.LT	4ac744

  (2323) 0x4ac780 LDR	X20, [X22]

  (2323) 0x4ac784 ADD	X14, X14, #1

  (2323) 0x4ac788 CMP	X20, X14

  (2323) 0x4ac78c B.GT	4ac688

0x4ac790 ORR	X27, XZR, X5

0x4ac794 LDR	X22, [SP, #120]

0x4ac798 ADD	X20, X15, X3

0x4ac79c LDR	X3, [X15, X3]

0x4ac7a0 LDR	X14, [X15, X22,LSL #3]

0x4ac7a4 CMP	X14, X3

0x4ac7a8 B.GE	4ac874

  (2320) 0x4ac7ac LDR	X12, [X25, X14,LSL #3]

  (2320) 0x4ac7b0 LDR	X5, [X24, X12,LSL #3]

  (2320) 0x4ac7b4 UBFM	X10, X12, #61, #60

  (2320) 0x4ac7b8 CMP	X5, #0

  (2320) 0x4ac7bc B.LE	4ac7dc

  (2320) 0x4ac7c0 LDR	X0, [X7, X12,LSL #3]

  (2320) 0x4ac7c4 LDR	X1, [X19, X0,LSL #3]

  (2320) 0x4ac7c8 CMP	X1, X6

  (2320) 0x4ac7cc B.GE	4ac7dc

  (2320) 0x4ac7d0 MOVZ	W13, #1

  (2320) 0x4ac7d4 STR	X2, [X19, X0,LSL #3]

  (2320) 0x4ac7d8 ADD	X2, X2, #1

  (2320) 0x4ac7dc ADD	X10, X10, #8

  (2320) 0x4ac7e0 LDR	X0, [X17, X12,LSL #3]

  (2320) 0x4ac7e4 ADD	X22, X17, X10

  (2320) 0x4ac7e8 LDR	X3, [X17, X10]

  (2320) 0x4ac7ec CMP	X0, X3

  (2320) 0x4ac7f0 B.GE	4ac834

  (2320) 0x4ac7f4 HINT	#0

  (2320) 0x4ac7f8 HINT	#0

  (2320) 0x4ac7fc HINT	#0

    (2322) 0x4ac800 LDR	X1, [X28, X0,LSL #3]

    (2322) 0x4ac804 CMP	X1, X9

    (2322) 0x4ac808 B.EQ	4ac828

    (2322) 0x4ac80c LDR	X5, [X21, X1,LSL #3]

    (2322) 0x4ac810 CMP	X5, X11

    (2322) 0x4ac814 B.GE	4ac828

    (2322) 0x4ac818 STR	X4, [X21, X1,LSL #3]

    (2322) 0x4ac81c MOVZ	W30, #1

    (2322) 0x4ac820 ADD	X4, X4, #1

    (2322) 0x4ac824 LDR	X3, [X22]

    (2322) 0x4ac828 ADD	X0, X0, #1

    (2322) 0x4ac82c CMP	X0, X3

    (2322) 0x4ac830 B.LT	4ac800

  (2320) 0x4ac834 LDR	X1, [X16, X12,LSL #3]

  (2320) 0x4ac838 ADD	X12, X16, X10

  (2320) 0x4ac83c LDR	X5, [X16, X10]

  (2320) 0x4ac840 CMP	X1, X5

  (2320) 0x4ac844 B.GE	4ac864

    (2321) 0x4ac848 LDR	X10, [X27, X1,LSL #3]

    (2321) 0x4ac84c LDR	X22, [X19, X10,LSL #3]

    (2321) 0x4ac850 CMP	X22, X6

    (2321) 0x4ac854 B.LT	4ac890

    (2321) 0x4ac858 ADD	X1, X1, #1

    (2321) 0x4ac85c CMP	X1, X5

    (2321) 0x4ac860 B.LT	4ac848

  (2320) 0x4ac864 LDR	X3, [X20]

  (2320) 0x4ac868 ADD	X14, X14, #1

  (2320) 0x4ac86c CMP	X3, X14

  (2320) 0x4ac870 B.GT	4ac7ac

0x4ac874 LDR	X11, [SP, #136]

0x4ac878 ADD	X9, X9, #1

0x4ac87c CMP	X11, X9

0x4ac880 B.EQ	4ac8c0

0x4ac884 ORR	X11, XZR, X4

0x4ac888 ORR	X6, XZR, X2

0x4ac88c B	4ac634

    (2321) 0x4ac890 STR	X2, [X19, X10,LSL #3]

    (2321) 0x4ac894 ADD	X1, X1, #1

    (2321) 0x4ac898 ADD	X2, X2, #1

    (2321) 0x4ac89c LDR	X5, [X12]

    (2321) 0x4ac8a0 MOVZ	W13, #1

    (2321) 0x4ac8a4 CMP	X1, X5

    (2321) 0x4ac8a8 B.LT	4ac848

  (2320) 0x4ac8ac LDR	X3, [X20]

  (2320) 0x4ac8b0 ADD	X14, X14, #1

  (2320) 0x4ac8b4 CMP	X3, X14

  (2320) 0x4ac8b8 B.GT	4ac7ac

0x4ac8bc B	4ac874

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 1714 - 1797

--------------------------------------------------------------------------------

1714:          for (ic = ic_begin; ic < ic_end; ic++)

[...]

1720:              HYPRE_Int i1 = coarse_to_fine[ic];

1721:

1722:              HYPRE_Int jj_row_begin_diag = num_nonzeros_diag;

1723:              HYPRE_Int jj_row_begin_offd = num_nonzeros_offd;

1724:

1725:              C_diag_i[ic] = num_nonzeros_diag;

1726:              if (num_cols_offd_C)

1727:              {

1728:                 C_offd_i[ic] = num_nonzeros_offd;

1729:              }

1730:

1731:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

1732:              {

1733:                  i2 = S_diag_j[jj1];

1734:                  if (CF_marker[i2] > 0)

1735:                  {

1736:                     index = fine_to_coarse[i2];

1737:                     if (S_marker[index] < jj_row_begin_diag)

1738:                     {

1739:                        S_marker[index] = num_nonzeros_diag;

1740:                        num_nonzeros_diag++;

1741:                     }

1742:                  }

1743:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

1744:                  {

1745:                     i3 = S_diag_j[jj2];

1746:                     if (CF_marker[i3] > 0)

1747:                     {

1748:                        index = fine_to_coarse[i3];

1749:                        if (index != ic && S_marker[index] < jj_row_begin_diag)

1750:                        {

1751:                           S_marker[index] = num_nonzeros_diag;

1752:                           num_nonzeros_diag++;

1753:                        }

1754:                     }

1755:                  }

1756:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

1757:                  {

1758:                     i3 = S_offd_j[jj2];

1759:                     if (CF_marker_offd[i3] > 0)

1760:                     {

1761:                        index = map_S_to_C[i3];

1762:                        if (S_marker_offd[index] < jj_row_begin_offd)

1763:                        {

1764:                           S_marker_offd[index] = num_nonzeros_offd;

1765:                           num_nonzeros_offd++;

1766:                        }

1767:                     }

1768:                  }

1769:              }

1770:              for (jj1 = S_offd_i[i1]; jj1 < S_offd_i[i1+1]; jj1++)

1771:              {

1772:                  i2 = S_offd_j[jj1];

1773:                  if (CF_marker_offd[i2] > 0)

1774:                  {

1775:                     index = map_S_to_C[i2];

1776:                     if (S_marker_offd[index] < jj_row_begin_offd)

1777:                     {

1778:                        S_marker_offd[index] = num_nonzeros_offd;

1779:                        num_nonzeros_offd++;

1780:                     }

1781:                  }

1782:                  for (jj2 = S_ext_diag_i[i2]; jj2 < S_ext_diag_i[i2+1]; jj2++)

1783:                  {

1784:                     i3 = S_ext_diag_j[jj2];

1785:                     if (i3 != ic && S_marker[i3] < jj_row_begin_diag)

1786:                     {

1787:                        S_marker[i3] = num_nonzeros_diag;

1788:                        num_nonzeros_diag++;

1789:                     }

1790:                  }

1791:                  for (jj2 = S_ext_offd_i[i2]; jj2 < S_ext_offd_i[i2+1]; jj2++)

1792:                  {

1793:                     i3 = S_ext_offd_j[jj2];

1794:                     if (S_marker_offd[i3] < jj_row_begin_offd)

1795:                     {

1796:                        S_marker_offd[i3] = num_nonzeros_offd;

1797:                        num_nonzeros_offd++;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	P10,
Function	hypre_BoomerAMGCreate2ndS._omp_fn.7
Source	par_strength.c:1714-1714,par_strength.c:1720-1720,par_strength.c:1725-1728,par_strength.c:1731-1731,par_strength.c:1770-1770
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.50
CQA cycles if no scalar integer	5.50
CQA cycles if FP arith vectorized	5.50
CQA cycles if fully vectorized	1.38
Front-end cycles	4.50
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	3.50
P2 cycles	3.50
P3 cycles	3.50
P4 cycles	3.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	5.50
P10 cycles	5.17
P11 cycles	5.33
P12 cycles	1.50
P13 cycles	1.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	36.00
Nb uops	36.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.27
Bytes prefetched	0.00
Bytes loaded	104.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	P10,
Function	hypre_BoomerAMGCreate2ndS._omp_fn.7
Source	par_strength.c:1714-1714,par_strength.c:1720-1720,par_strength.c:1725-1728,par_strength.c:1731-1731,par_strength.c:1770-1770
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.50
CQA cycles if no scalar integer	5.50
CQA cycles if FP arith vectorized	5.50
CQA cycles if fully vectorized	1.38
Front-end cycles	4.50
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	3.50
P2 cycles	3.50
P3 cycles	3.50
P4 cycles	3.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	5.50
P10 cycles	5.17
P11 cycles	5.33
P12 cycles	1.50
P13 cycles	1.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	36.00
Nb uops	36.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.27
Bytes prefetched	0.00
Bytes loaded	104.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGCreate2ndS._omp_fn.7
Source file and lines	par_strength.c:1714-1797
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1714,1720-1797.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1714,1720,1725-1728,1731,1770.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 4514 paths individually, rerun with max-paths=4514
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 4514 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 5.50 to 1.37 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 104 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	36
loop length	144
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	3.50	3.50	3.50	3.50	0.00	0.00	0.00	0.00	5.50	5.17	5.33	1.50	1.50
cycles	3.00	3.00	3.50	3.50	3.50	3.50	0.00	0.00	0.00	0.00	5.50	5.17	5.33	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.50
Overall L1	5.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.50 cycles. At this rate:

19% of peak load performance is reached (18.91 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.36 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4ac634

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X20, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [SP, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X20, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X11, [X0, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X22, [SP, #120]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ X10, 4ac65c <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x131c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [SP, #192]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X6, [X14, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X4, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X2, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X5, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X14, [X18, X12,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X5, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X1, [X18, X3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X22, X18, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X14, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4ac794 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1454>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X27, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X22, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X20, X15, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X3, [X15, X3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X15, X22,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4ac874 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1534>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X11, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4ac8c0 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1580>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X11, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X6, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 4ac634 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x12f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
B 4ac874 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1534>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_BoomerAMGCreate2ndS._omp_fn.7
Source file and lines	par_strength.c:1714-1797
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1714,1720-1797.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1714,1720,1725-1728,1731,1770.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 4514 paths individually, rerun with max-paths=4514
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 4514 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 5.50 to 1.37 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 104 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	36
loop length	144
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	3.50	3.50	3.50	3.50	0.00	0.00	0.00	0.00	5.50	5.17	5.33	1.50	1.50
cycles	3.00	3.00	3.50	3.50	3.50	3.50	0.00	0.00	0.00	0.00	5.50	5.17	5.33	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.50
Overall L1	5.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.50 cycles. At this rate:

19% of peak load performance is reached (18.91 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.36 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4ac634

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X20, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [SP, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X20, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X11, [X0, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X22, [SP, #120]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ X10, 4ac65c <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x131c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [SP, #192]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X6, [X14, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X4, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X2, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X5, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X14, [X18, X12,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X5, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X1, [X18, X3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X22, X18, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X14, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4ac794 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1454>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X27, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X22, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X20, X15, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X3, [X15, X3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X15, X22,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4ac874 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1534>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X11, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4ac8c0 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1580>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X11, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X6, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 4ac634 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x12f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
B 4ac874 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1534>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code