OV - exec - Loop 179

	Loop Id: 179	Module: exec	Source: par_coarsen.c:2528-2540	Coverage: 0.04%

0x421b54 LDR	X17, [X1]    [26]

0x421b58 LDR	X18, [X20, X17,LSL #3]    [15]

0x421b5c CBNZ	X18, 42221c

0x421b60 LDR	X30, [X1, #8]    [26]

0x421b64 ADD	X3, X3, #1

0x421b68 MOVZ	W4, #1

0x421b6c ADD	X1, X1, #8

0x421b70 LDR	X2, [X20, X30,LSL #3]    [27]

0x421b74 CBZ	X2, 422230

0x421b78 LDR	X5, [X1, #8]    [3]

0x421b7c STR	XZR, [X25, X30,LSL #3]    [19]

0x421b80 LDR	X0, [X20, X5,LSL #3]    [31]

0x421b84 CBZ	X0, 422244

0x421b88 LDR	X7, [X1, #16]    [5]

0x421b8c STR	XZR, [X25, X5,LSL #3]    [1]

0x421b90 LDR	X8, [X20, X7,LSL #3]    [18]

0x421b94 CBZ	X8, 422258

0x421b98 LDR	X9, [X1, #24]    [7]

0x421b9c STR	XZR, [X25, X7,LSL #3]    [14]

0x421ba0 LDR	X10, [X20, X9,LSL #3]    [16]

0x421ba4 CBZ	X10, 42226c

0x421ba8 LDR	X11, [X1, #32]    [9]

0x421bac STR	XZR, [X25, X9,LSL #3]    [21]

0x421bb0 LDR	X12, [X20, X11,LSL #3]    [24]

0x421bb4 CBZ	X12, 422280

0x421bb8 LDR	X13, [X1, #40]    [11]

0x421bbc STR	XZR, [X25, X11,LSL #3]    [20]

0x421bc0 LDR	X14, [X20, X13,LSL #3]    [23]

0x421bc4 CBZ	X14, 422294

0x421bc8 LDR	X15, [X1, #48]    [25]

0x421bcc STR	XZR, [X25, X13,LSL #3]    [22]

0x421bd0 LDR	X16, [X20, X15,LSL #3]    [13]

0x421bd4 CBZ	X16, 4222a8

0x421bd8 STR	XZR, [X25, X15,LSL #3]    [28]

0x421bdc ADD	X1, X1, #56

0x421be0 CMP	X6, X1

0x421be4 B.NE	421b54

0x42221c LDR	X30, [X1, #8]    [26]

0x422220 ADD	X1, X1, #8

0x422224 STR	XZR, [X25, X17,LSL #3]    [29]

0x422228 LDR	X2, [X20, X30,LSL #3]    [27]

0x42222c CBNZ	X2, 421b78

0x422230 LDR	X5, [X1, #8]    [30]

0x422234 ADD	X3, X3, #1

0x422238 MOVZ	W4, #1

0x42223c LDR	X0, [X20, X5,LSL #3]    [34]

0x422240 CBNZ	X0, 421b88

0x422244 LDR	X7, [X1, #16]    [4]

0x422248 ADD	X3, X3, #1

0x42224c MOVZ	W4, #1

0x422250 LDR	X8, [X20, X7,LSL #3]    [33]

0x422254 CBNZ	X8, 421b98

0x422258 LDR	X9, [X1, #24]    [6]

0x42225c ADD	X3, X3, #1

0x422260 MOVZ	W4, #1

0x422264 LDR	X10, [X20, X9,LSL #3]    [32]

0x422268 CBNZ	X10, 421ba8

0x42226c LDR	X11, [X1, #32]    [8]

0x422270 ADD	X3, X3, #1

0x422274 MOVZ	W4, #1

0x422278 LDR	X12, [X20, X11,LSL #3]    [2]

0x42227c CBNZ	X12, 421bb8

0x422280 LDR	X13, [X1, #40]    [10]

0x422284 ADD	X3, X3, #1

0x422288 MOVZ	W4, #1

0x42228c LDR	X14, [X20, X13,LSL #3]    [35]

0x422290 CBNZ	X14, 421bc8

0x422294 LDR	X15, [X1, #48]    [12]

0x422298 ADD	X3, X3, #1

0x42229c MOVZ	W4, #1

0x4222a0 LDR	X16, [X20, X15,LSL #3]    [17]

0x4222a4 CBNZ	X16, 421bd8

0x4222a8 ADD	X3, X3, #1

0x4222ac MOVZ	W4, #1

0x4222b0 B	421bdc

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2528 - 2540

--------------------------------------------------------------------------------

2528:         for (ig = ig_begin; ig < ig_end; ig++)

2529:         {

2530:            i = graph_array[ig];

2531:

2532:            if (CF_marker[i]!=0) /* C or F point */

2533:            {

2534:               /* the independent set subroutine needs measure 0 for

2535:                  removed nodes */

2536:               measure_array[i] = 0;

2537:            }

2538:            else

2539:            {

2540:               private_graph_size_cnt++;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.35
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.8
Source	par_coarsen.c:2528-2540
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.67
CQA cycles if no scalar integer	12.67
CQA cycles if FP arith vectorized	12.67
CQA cycles if fully vectorized	1.58
Front-end cycles	9.38
DIV/SQRT cycles	8.50
P0 cycles	8.50
P1 cycles	5.00
P2 cycles	5.00
P3 cycles	5.00
P4 cycles	5.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	12.67
P10 cycles	12.67
P11 cycles	12.67
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	75.00
Nb uops	75.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	240.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	13.89
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	13.89

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.35
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.8
Source	par_coarsen.c:2528-2540
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.67
CQA cycles if no scalar integer	12.67
CQA cycles if FP arith vectorized	12.67
CQA cycles if fully vectorized	1.58
Front-end cycles	9.38
DIV/SQRT cycles	8.50
P0 cycles	8.50
P1 cycles	5.00
P2 cycles	5.00
P3 cycles	5.00
P4 cycles	5.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	12.67
P10 cycles	12.67
P11 cycles	12.67
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	75.00
Nb uops	75.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	240.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	13.89
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	13.89

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.8
Source file and lines	par_coarsen.c:2528-2540
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2528-2540.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 256 paths individually, rerun with max-paths=256
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 256 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 12.67 to 1.58 cycles (8.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 240 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	75
loop length	300
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	8.50	8.50	5.00	5.00	5.00	5.00	0.00	0.00	0.00	0.00	12.67	12.67	12.67	4.00	4.00
cycles	8.50	8.50	5.00	5.00	5.00	5.00	0.00	0.00	0.00	0.00	12.67	12.67	12.67	4.00	4.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.38
Overall L1	12.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.67 cycles. At this rate:

19% of peak load performance is reached (18.95 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (5.05 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 421b54

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X17, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X20, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X18, 42221c <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x854>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X30, [X1, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X2, [X20, X30,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X2, 422230 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x868>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X5, [X1, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X25, X30,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X20, X5,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X0, 422244 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x87c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X7, [X1, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X25, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X8, 422258 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x890>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X1, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X25, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X20, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X10, 42226c <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x8a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X1, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X25, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X20, X11,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X12, 422280 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x8b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X1, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X25, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X20, X13,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X14, 422294 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x8cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [X1, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X25, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X20, X15,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X16, 4222a8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x8e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR XZR, [X25, X15,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X6, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 421b54 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x18c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X30, [X1, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X25, X17,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X2, [X20, X30,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X2, 421b78 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x1b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X5, [X1, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X20, X5,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X0, 421b88 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X7, [X1, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X8, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X8, 421b98 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X1, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X10, [X20, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X10, 421ba8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X1, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X12, [X20, X11,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X12, 421bb8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X1, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X14, [X20, X13,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X14, 421bc8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [X1, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X16, [X20, X15,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X16, 421bd8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 421bdc <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.8
Source file and lines	par_coarsen.c:2528-2540
Module	exec

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 256 paths individually, rerun with max-paths=256
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 240 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	75
loop length	300
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	8.50	8.50	5.00	5.00	5.00	5.00	0.00	0.00	0.00	0.00	12.67	12.67	12.67	4.00	4.00
cycles	8.50	8.50	5.00	5.00	5.00	5.00	0.00	0.00	0.00	0.00	12.67	12.67	12.67	4.00	4.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.38
Overall L1	12.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.67 cycles. At this rate:

19% of peak load performance is reached (18.95 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (5.05 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 421b54

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X17, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X20, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X18, 42221c <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x854>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X30, [X1, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X2, [X20, X30,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X2, 422230 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x868>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X5, [X1, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X25, X30,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X20, X5,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X0, 422244 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x87c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X7, [X1, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X25, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X8, 422258 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x890>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X1, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X25, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X20, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X10, 42226c <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x8a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X1, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X25, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X20, X11,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X12, 422280 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x8b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X1, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X25, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X20, X13,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X14, 422294 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x8cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [X1, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X25, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X20, X15,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X16, 4222a8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x8e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR XZR, [X25, X15,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X6, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 421b54 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x18c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X30, [X1, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X25, X17,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X2, [X20, X30,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X2, 421b78 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x1b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X5, [X1, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X20, X5,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X0, 421b88 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X7, [X1, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X8, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X8, 421b98 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X1, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X10, [X20, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X10, 421ba8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X1, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X12, [X20, X11,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X12, 421bb8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X1, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X14, [X20, X13,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X14, 421bc8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [X1, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X16, [X20, X15,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X16, 421bd8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 421bdc <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code