OV - exec - Loop 178

	Loop Id: 178	Module: exec	Source: par_coarsen.c:2562-2567	Coverage: 0.03%

0x421ed0 LDR	X24, [X0]    [18]

0x421ed4 LDR	X25, [X20, X24,LSL #3]    [10]

0x421ed8 CBNZ	X25, 421ee8

0x421edc MOVZ	W3, #1

0x421ee0 STR	X24, [X23, X2,LSL #3]    [15]

0x421ee4 ADD	X2, X2, #1

0x421ee8 LDR	X27, [X0, #8]    [18]

0x421eec ADD	X0, X0, #8

0x421ef0 LDR	X28, [X20, X27,LSL #3]    [16]

0x421ef4 CBNZ	X28, 421f04

0x421ef8 MOVZ	W3, #1

0x421efc STR	X27, [X23, X2,LSL #3]    [14]

0x421f00 ADD	X2, X2, #1

0x421f04 LDR	X18, [X0, #8]    [12]

0x421f08 LDR	X5, [X20, X18,LSL #3]    [8]

0x421f0c CBNZ	X5, 421f1c

0x421f10 MOVZ	W3, #1

0x421f14 STR	X18, [X23, X2,LSL #3]    [13]

0x421f18 ADD	X2, X2, #1

0x421f1c LDR	X7, [X0, #16]    [12]

0x421f20 LDR	X8, [X20, X7,LSL #3]    [17]

0x421f24 CBNZ	X8, 421f34

0x421f28 MOVZ	W3, #1

0x421f2c STR	X7, [X23, X2,LSL #3]    [9]

0x421f30 ADD	X2, X2, #1

0x421f34 LDR	X9, [X0, #24]    [12]

0x421f38 LDR	X10, [X20, X9,LSL #3]    [1]

0x421f3c CBNZ	X10, 421f4c

0x421f40 MOVZ	W3, #1

0x421f44 STR	X9, [X23, X2,LSL #3]    [7]

0x421f48 ADD	X2, X2, #1

0x421f4c LDR	X11, [X0, #32]    [12]

0x421f50 LDR	X12, [X20, X11,LSL #3]    [2]

0x421f54 CBNZ	X12, 421f64

0x421f58 MOVZ	W3, #1

0x421f5c STR	X11, [X23, X2,LSL #3]    [6]

0x421f60 ADD	X2, X2, #1

0x421f64 LDR	X13, [X0, #40]    [12]

0x421f68 LDR	X14, [X20, X13,LSL #3]    [3]

0x421f6c CBNZ	X14, 421f7c

0x421f70 MOVZ	W3, #1

0x421f74 STR	X13, [X23, X2,LSL #3]    [5]

0x421f78 ADD	X2, X2, #1

0x421f7c LDR	X15, [X0, #48]    [12]

0x421f80 LDR	X16, [X20, X15,LSL #3]    [11]

0x421f84 CBNZ	X16, 421f94

0x421f88 MOVZ	W3, #1

0x421f8c STR	X15, [X23, X2,LSL #3]    [4]

0x421f90 ADD	X2, X2, #1

0x421f94 ADD	X0, X0, #56

0x421f98 CMP	X26, X0

0x421f9c B.NE	421ed0

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2562 - 2567

--------------------------------------------------------------------------------

2562:         for (ig = ig_begin; ig < ig_end; ig++)

2563:         {

2564:            i = graph_array[ig];

2565:            if (CF_marker[i]==0)

2566:            {

2567:               graph_array2[private_graph_size_cnt++] = i;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.23
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.8
Source	par_coarsen.c:2562-2567
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	1.00
Front-end cycles	6.50
DIV/SQRT cycles	4.50
P0 cycles	4.50
P1 cycles	4.75
P2 cycles	4.75
P3 cycles	4.75
P4 cycles	4.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	8.00
P10 cycles	8.00
P11 cycles	8.00
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	52.00
Nb uops	52.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.23
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.8
Source	par_coarsen.c:2562-2567
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	1.00
Front-end cycles	6.50
DIV/SQRT cycles	4.50
P0 cycles	4.50
P1 cycles	4.75
P2 cycles	4.75
P3 cycles	4.75
P4 cycles	4.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	8.00
P10 cycles	8.00
P11 cycles	8.00
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	52.00
Nb uops	52.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.8
Source file and lines	par_coarsen.c:2562-2567
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2562-2567.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 256 paths individually, rerun with max-paths=256
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 256 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 8.00 to 1.00 cycles (8.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 128 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	52
loop length	208
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	8.00	8.00	8.00	4.00	4.00
cycles	4.50	4.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	8.00	8.00	8.00	4.00	4.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.50
Overall L1	8.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (8.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 421ed0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X24, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X20, X24,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X25, 421ee8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x520>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X24, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X27, [X0, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X28, [X20, X27,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X28, 421f04 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x53c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X27, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X18, [X0, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X20, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X5, 421f1c <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x554>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X18, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X7, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X8, 421f34 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x56c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X7, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X9, [X0, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X20, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X10, 421f4c <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x584>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X9, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X11, [X0, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X20, X11,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X12, 421f64 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x59c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X13, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X20, X13,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X14, 421f7c <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x5b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X13, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X15, [X0, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X20, X15,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X16, 421f94 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x5cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X15, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, X0, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X26, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 421ed0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x508>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.8
Source file and lines	par_coarsen.c:2562-2567
Module	exec

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 256 paths individually, rerun with max-paths=256
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 8.00 to 1.00 cycles (8.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 128 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	52
loop length	208
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	8.00	8.00	8.00	4.00	4.00
cycles	4.50	4.50	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	8.00	8.00	8.00	4.00	4.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.50
Overall L1	8.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (8.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 421ed0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X24, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X20, X24,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X25, 421ee8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x520>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X24, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X27, [X0, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X28, [X20, X27,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X28, 421f04 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x53c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X27, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X18, [X0, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X20, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X5, 421f1c <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x554>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X18, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X7, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X8, 421f34 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x56c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X7, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X9, [X0, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X20, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X10, 421f4c <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x584>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X9, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X11, [X0, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X20, X11,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X12, 421f64 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x59c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X13, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X20, X13,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X14, 421f7c <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x5b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X13, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X15, [X0, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X20, X15,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X16, 421f94 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x5cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X15, [X23, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, X0, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X26, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 421ed0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x508>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code