OV - exec - Loop 164

0x421760 ADD	X14, X13, #1

0x421764 LDR	D22, [X0, X13,LSL #3]    [1]

0x421768 ADD	X10, X13, #2

0x42176c ADD	X9, X13, #3

0x421770 ADD	X8, X13, #4

0x421774 LDR	D23, [X0, X14,LSL #3]    [7]

0x421778 ADD	X7, X13, #5

0x42177c ADD	X6, X13, #6

0x421780 ADD	X15, X13, #7

0x421784 LDR	D24, [X0, X10,LSL #3]    [6]

0x421788 SCVTF	D25, D22

0x42178c LDR	D26, [X0, X9,LSL #3]    [5]

0x421790 SCVTF	D27, D23

0x421794 LDR	D28, [X0, X8,LSL #3]    [4]

0x421798 SCVTF	D29, D24

0x42179c LDR	D30, [X0, X7,LSL #3]    [3]

0x4217a0 SCVTF	D31, D26

0x4217a4 STR	D25, [X12, X13,LSL #3]    [1]

0x4217a8 ADD	X13, X13, #8

0x4217ac LDR	D1, [X0, X6,LSL #3]    [2]

0x4217b0 SCVTF	D3, D28

0x4217b4 STR	D27, [X12, X14,LSL #3]    [7]

0x4217b8 LDR	D0, [X0, X15,LSL #3]    [8]

0x4217bc SCVTF	D2, D30

0x4217c0 STR	D29, [X12, X10,LSL #3]    [6]

0x4217c4 SCVTF	D4, D1

0x4217c8 STR	D31, [X12, X9,LSL #3]    [5]

0x4217cc SCVTF	D5, D0

0x4217d0 STR	D3, [X12, X8,LSL #3]    [4]

0x4217d4 STR	D2, [X12, X7,LSL #3]    [3]

0x4217d8 STR	D4, [X12, X6,LSL #3]    [2]

0x4217dc STR	D5, [X12, X15,LSL #3]    [8]

0x4217e0 CMP	X11, X13

0x4217e4 B.NE	421760

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2142 - 2142

--------------------------------------------------------------------------------

2142:      measure_array[i] = measure_array_temp[i];

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.50
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	P4,
Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.3
Source	par_coarsen.c:2142-2142
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	5.33
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	2.00
Front-end cycles	4.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	8.00
P4 cycles	3.00
P5 cycles	4.00
P6 cycles	4.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	5.33
P10 cycles	5.33
P11 cycles	5.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	34.00
Nb uops	34.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.50
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	P4,
Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.3
Source	par_coarsen.c:2142-2142
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	5.33
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	2.00
Front-end cycles	4.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	8.00
P4 cycles	3.00
P5 cycles	4.00
P6 cycles	4.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	5.33
P10 cycles	5.33
P11 cycles	5.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	34.00
Nb uops	34.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.3
Source file and lines	par_coarsen.c:2142-2142
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2142.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.00 to 5.33 cycles (1.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 8.00 to 2.00 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Conversion instructions

Detected expensive conversion instructions.

Details

SCVTF: 8 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	34
loop length	136
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	3.00	3.00	8.00	3.00	4.00	4.00	0.00	0.00	5.33	5.33	5.33	0.00	0.00
cycles	0.50	0.50	3.00	3.00	8.00	3.00	4.00	4.00	0.00	0.00	5.33	5.33	5.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.25
Data deps.	1.00
Overall L1	8.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (8.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 421760

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
ADD X14, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D22, [X0, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X10, X13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X9, X13, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X8, X13, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D23, [X0, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X7, X13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X6, X13, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X15, X13, #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D24, [X0, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SCVTF D25, D22	1	0	0	0	0	1	0	0	0	0	0	0	3	1
LDR D26, [X0, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SCVTF D27, D23	1	0	0	0	0	1	0	0	0	0	0	0	3	1
LDR D28, [X0, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SCVTF D29, D24	1	0	0	0	0	1	0	0	0	0	0	0	3	1
LDR D30, [X0, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SCVTF D31, D26	1	0	0	0	0	1	0	0	0	0	0	0	3	1
STR D25, [X12, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
ADD X13, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D1, [X0, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SCVTF D3, D28	1	0	0	0	0	1	0	0	0	0	0	0	3	1
STR D27, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D0, [X0, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SCVTF D2, D30	1	0	0	0	0	1	0	0	0	0	0	0	3	1
STR D29, [X12, X10,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SCVTF D4, D1	1	0	0	0	0	1	0	0	0	0	0	0	3	1
STR D31, [X12, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SCVTF D5, D0	1	0	0	0	0	1	0	0	0	0	0	0	3	1
STR D3, [X12, X8,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STR D2, [X12, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STR D4, [X12, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STR D5, [X12, X15,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
CMP X11, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 421760 <hypre_BoomerAMGCoarsenPMIS._omp_fn.3+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.3
Source file and lines	par_coarsen.c:2142-2142
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2142.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.00 to 5.33 cycles (1.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 8.00 to 2.00 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Conversion instructions

Detected expensive conversion instructions.

Details

SCVTF: 8 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	34
loop length	136
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	3.00	3.00	8.00	3.00	4.00	4.00	0.00	0.00	5.33	5.33	5.33	0.00	0.00
cycles	0.50	0.50	3.00	3.00	8.00	3.00	4.00	4.00	0.00	0.00	5.33	5.33	5.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.25
Data deps.	1.00
Overall L1	8.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (8.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 421760

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
ADD X14, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D22, [X0, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X10, X13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X9, X13, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X8, X13, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D23, [X0, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X7, X13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X6, X13, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X15, X13, #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D24, [X0, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SCVTF D25, D22	1	0	0	0	0	1	0	0	0	0	0	0	3	1
LDR D26, [X0, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SCVTF D27, D23	1	0	0	0	0	1	0	0	0	0	0	0	3	1
LDR D28, [X0, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SCVTF D29, D24	1	0	0	0	0	1	0	0	0	0	0	0	3	1
LDR D30, [X0, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SCVTF D31, D26	1	0	0	0	0	1	0	0	0	0	0	0	3	1
STR D25, [X12, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
ADD X13, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D1, [X0, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SCVTF D3, D28	1	0	0	0	0	1	0	0	0	0	0	0	3	1
STR D27, [X12, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D0, [X0, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SCVTF D2, D30	1	0	0	0	0	1	0	0	0	0	0	0	3	1
STR D29, [X12, X10,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SCVTF D4, D1	1	0	0	0	0	1	0	0	0	0	0	0	3	1
STR D31, [X12, X9,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SCVTF D5, D0	1	0	0	0	0	1	0	0	0	0	0	0	3	1
STR D3, [X12, X8,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STR D2, [X12, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STR D4, [X12, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STR D5, [X12, X15,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
CMP X11, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 421760 <hypre_BoomerAMGCoarsenPMIS._omp_fn.3+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code