OV - exec - Loop 154

	Loop Id: 154	Module: exec	Source: par_coarsen.c:2332-2334	Coverage: 0.02%

0x42132c LDR	X12, [X0]    [10]

0x421330 LDR	D16, [X9, X12,LSL #3]    [17]

0x421334 FCMPE	D16, D0

0x421338 B.GT	421470

0x42133c LDR	X13, [X0, #8]    [18]

0x421340 ADD	X0, X0, #8

0x421344 LDR	D17, [X9, X13,LSL #3]    [14]

0x421348 FCMPE	D17, D0

0x42134c B.GT	421458

0x421350 LDR	X14, [X0, #8]    [20]

0x421354 LDR	D18, [X9, X14,LSL #3]    [34]

0x421358 FCMPE	D18, D0

0x42135c B.GT	421440

0x421360 LDR	X15, [X0, #16]    [22]

0x421364 LDR	D19, [X9, X15,LSL #3]    [37]

0x421368 FCMPE	D19, D0

0x42136c B.GT	421428

0x421370 LDR	X16, [X0, #24]    [24]

0x421374 LDR	D20, [X9, X16,LSL #3]    [27]

0x421378 FCMPE	D20, D0

0x42137c B.GT	421410

0x421380 LDR	X17, [X0, #32]    [26]

0x421384 LDR	D21, [X9, X17,LSL #3]    [4]

0x421388 FCMPE	D21, D0

0x42138c B.GT	4213f8

0x421390 LDR	X18, [X0, #40]    [30]

0x421394 LDR	D22, [X9, X18,LSL #3]    [7]

0x421398 FCMPE	D22, D0

0x42139c B.GT	4213e0

0x4213a0 LDR	X30, [X0, #48]    [32]

0x4213a4 LDR	D23, [X9, X30,LSL #3]    [1]

0x4213a8 FCMPE	D23, D0

0x4213ac B.GT	4213cc

0x4213b0 ADD	X0, X0, #56

0x4213b4 CMP	X10, X0

0x4213b8 B.NE	42132c

0x4213e0 STR	X5, [X4, X18,LSL #3]    [35]

0x4213e4 LDR	X30, [X0, #48]    [31]

0x4213e8 LDR	D23, [X9, X30,LSL #3]    [12]

0x4213ec FCMPE	D23, D0

0x4213f0 B.GT	4213cc

0x4213f4 B	4213b0

0x4213f8 STR	X5, [X4, X17,LSL #3]    [16]

0x4213fc LDR	X18, [X0, #40]    [29]

0x421400 LDR	D22, [X9, X18,LSL #3]    [15]

0x421404 FCMPE	D22, D0

0x421408 B.GT	4213e0

0x42140c B	4213a0

0x421410 STR	X5, [X4, X16,LSL #3]    [5]

0x421414 LDR	X17, [X0, #32]    [25]

0x421418 LDR	D21, [X9, X17,LSL #3]    [6]

0x42141c FCMPE	D21, D0

0x421420 B.GT	4213f8

0x421424 B	421390

0x421428 STR	X5, [X4, X15,LSL #3]    [8]

0x42142c LDR	X16, [X0, #24]    [23]

0x421430 LDR	D20, [X9, X16,LSL #3]    [9]

0x421434 FCMPE	D20, D0

0x421438 B.GT	421410

0x42143c B	421380

0x421440 STR	X5, [X4, X14,LSL #3]    [33]

0x421444 LDR	X15, [X0, #16]    [21]

0x421448 LDR	D19, [X9, X15,LSL #3]    [36]

0x42144c FCMPE	D19, D0

0x421450 B.GT	421428

0x421454 B	421370

0x421458 STR	X5, [X4, X13,LSL #3]    [13]

0x42145c LDR	X14, [X0, #8]    [19]

0x421460 LDR	D18, [X9, X14,LSL #3]    [3]

0x421464 FCMPE	D18, D0

0x421468 B.GT	421440

0x42146c B	421360

0x421470 STR	X5, [X4, X12,LSL #3]    [2]

0x421474 ADD	X0, X0, #8

0x421478 LDR	X13, [X0]    [28]

0x42147c LDR	D17, [X9, X13,LSL #3]    [11]

0x421480 FCMPE	D17, D0

0x421484 B.GT	421458

0x421488 B	421350

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2332 - 2334

--------------------------------------------------------------------------------

2332:            if (measure_array[i] > 1)

2333:            {

2334:               CF_marker[i] = 1;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	3.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	P6,
Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.4
Source	par_coarsen.c:2332-2334
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	15.00
CQA cycles if fully vectorized	3.75
Front-end cycles	9.88
DIV/SQRT cycles	11.50
P0 cycles	11.50
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	15.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	12.50
P10 cycles	12.17
P11 cycles	12.33
P12 cycles	3.50
P13 cycles	3.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	79.00
Nb uops	79.00
Nb loads	NA
Nb stores	7.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.73
Bytes prefetched	0.00
Bytes loaded	240.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	3.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	P6,
Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.4
Source	par_coarsen.c:2332-2334
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	15.00
CQA cycles if fully vectorized	3.75
Front-end cycles	9.88
DIV/SQRT cycles	11.50
P0 cycles	11.50
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	15.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	12.50
P10 cycles	12.17
P11 cycles	12.33
P12 cycles	3.50
P13 cycles	3.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	79.00
Nb uops	79.00
Nb loads	NA
Nb stores	7.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.73
Bytes prefetched	0.00
Bytes loaded	240.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.4
Source file and lines	par_coarsen.c:2332-2334
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332-2334.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.00 to 5.00 cycles (3.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 15.00 to 3.75 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 240 bytes. The binary loop is storing 56 bytes.

General properties

nb instructions	79
loop length	316
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	11.50	11.50	1.00	1.00	1.00	1.00	15.00	0.00	0.00	0.00	12.50	12.17	12.33	3.50	3.50
cycles	11.50	11.50	1.00	1.00	1.00	1.00	15.00	0.00	0.00	0.00	12.50	12.17	12.33	3.50	3.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.88
Overall L1	15.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (3.73 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 42132c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X12, [X0]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D16, [X9, X12,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D16, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
B.GT 421470 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X0, #8]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR D17, [X9, X13,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D17, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
B.GT 421458 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x288>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [X0, #8]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D18, [X9, X14,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D18, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
B.GT 421440 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x270>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [X0, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D19, [X9, X15,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D19, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
B.GT 421428 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x258>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X16, [X0, #24]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D20, [X9, X16,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D20, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
B.GT 421410 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x240>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X17, [X0, #32]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D21, [X9, X17,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D21, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
B.GT 4213f8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x228>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X0, #40]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D22, [X9, X18,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D22, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
B.GT 4213e0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X30, [X0, #48]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D23, [X9, X30,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D23, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
B.GT 4213cc <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP X10, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
B.NE 42132c <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X5, [X4, X18,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X30, [X0, #48]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D23, [X9, X30,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D23, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
B.GT 4213cc <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
B 4213b0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X5, [X4, X17,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X0, #40]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D22, [X9, X18,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D22, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
B.GT 4213e0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
B 4213a0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X5, [X4, X16,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X17, [X0, #32]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D21, [X9, X17,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D21, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
B.GT 4213f8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x228>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
B 421390 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X5, [X4, X15,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X0, #24]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D20, [X9, X16,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D20, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
B.GT 421410 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x240>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
B 421380 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X5, [X4, X14,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [X0, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D19, [X9, X15,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D19, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
B.GT 421428 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x258>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
B 421370 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X5, [X4, X13,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X0, #8]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D18, [X9, X14,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D18, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
B.GT 421440 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x270>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
B 421360 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X5, [X4, X12,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR X13, [X0]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D17, [X9, X13,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D17, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
B.GT 421458 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x288>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
B 421350 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.4
Source file and lines	par_coarsen.c:2332-2334
Module	exec

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.00 to 5.00 cycles (3.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 240 bytes. The binary loop is storing 56 bytes.

General properties

nb instructions	79
loop length	316
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	11.50	11.50	1.00	1.00	1.00	1.00	15.00	0.00	0.00	0.00	12.50	12.17	12.33	3.50	3.50
cycles	11.50	11.50	1.00	1.00	1.00	1.00	15.00	0.00	0.00	0.00	12.50	12.17	12.33	3.50	3.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.88
Overall L1	15.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (3.73 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 42132c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X12, [X0]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D16, [X9, X12,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D16, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
B.GT 421470 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X0, #8]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR D17, [X9, X13,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D17, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
B.GT 421458 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x288>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [X0, #8]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D18, [X9, X14,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D18, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
B.GT 421440 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x270>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [X0, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D19, [X9, X15,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D19, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
B.GT 421428 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x258>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X16, [X0, #24]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D20, [X9, X16,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D20, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
B.GT 421410 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x240>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X17, [X0, #32]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D21, [X9, X17,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D21, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
B.GT 4213f8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x228>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X0, #40]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D22, [X9, X18,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D22, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
B.GT 4213e0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X30, [X0, #48]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D23, [X9, X30,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D23, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
B.GT 4213cc <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP X10, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
B.NE 42132c <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X5, [X4, X18,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X30, [X0, #48]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D23, [X9, X30,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D23, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
B.GT 4213cc <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
B 4213b0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X5, [X4, X17,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X0, #40]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D22, [X9, X18,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D22, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
B.GT 4213e0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
B 4213a0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X5, [X4, X16,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X17, [X0, #32]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D21, [X9, X17,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D21, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
B.GT 4213f8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x228>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
B 421390 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X5, [X4, X15,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X0, #24]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D20, [X9, X16,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D20, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
B.GT 421410 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x240>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
B 421380 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X5, [X4, X14,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [X0, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D19, [X9, X15,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D19, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
B.GT 421428 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x258>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
B 421370 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X5, [X4, X13,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X0, #8]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D18, [X9, X14,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D18, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
B.GT 421440 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x270>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
B 421360 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X5, [X4, X12,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LDR X13, [X0]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D17, [X9, X13,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D17, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
B.GT 421458 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x288>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
B 421350 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code