OV - exec - Loop 12

	Loop Id: 12	Module: exec	Source: amg.c:794-1409 [...]	Coverage: 0.33%

    (10) 0x410b90 ORR	X5, XZR, X15

    (10) 0x410b94 ORR	X3, XZR, X15

    (10) 0x410b98 HINT	#0

    (10) 0x410b9c HINT	#0

    (10) 0x410ba0 ADD	X3, X3, #1

    (10) 0x410ba4 CMP	X26, X18

    (10) 0x410ba8 B.GE	411414

  (11) 0x410bac CMP	X26, X4

  (11) 0x410bb0 B.GE	4111c8

0x410bb4 CMP	X18, X4

0x410bb8 ORR	X2, XZR, X26

0x410bbc CSEL	X28, X18, X4, #13

0x410bc0 ORR	X1, XZR, X26

0x410bc4 ORR	X0, XZR, X17

0x410bc8 B	410cb0

0x410bcc LDR	X8, [X19, X0,LSL #3]

0x410bd0 ADD	X11, X8, #1

0x410bd4 STR	X11, [X19, X0,LSL #3]

0x410bd8 CMP	X15, X5

0x410bdc B.GE	4110c8

0x410be0 ADD	X11, X8, #2

0x410be4 STR	X11, [X19, X0,LSL #3]

0x410be8 CMP	X26, X2

0x410bec B.GE	411164

0x410bf0 ADD	X11, X8, #3

0x410bf4 STR	X11, [X19, X0,LSL #3]

0x410bf8 CMP	X4, X2

0x410bfc B.GT	411174

0x410c00 CMP	X24, X1

0x410c04 B.LE	410c14

0x410c08 LDR	X8, [X20, X0,LSL #3]

0x410c0c ADD	X10, X8, #1

0x410c10 STR	X10, [X20, X0,LSL #3]

0x410c14 CMP	X26, X2

0x410c18 B.GE	4110b4

0x410c1c LDR	X8, [X19, X0,LSL #3]

0x410c20 ADD	X10, X8, #1

0x410c24 STR	X10, [X19, X0,LSL #3]

0x410c28 CMP	X6, X1

0x410c2c B.LE	411068

0x410c30 LDR	X10, [X19, X0,LSL #3]

0x410c34 ADD	X11, X10, #1

0x410c38 STR	X11, [X19, X0,LSL #3]

0x410c3c CMP	X7, X3

0x410c40 B.GT	410eb8

0x410c44 LDR	X8, [X20, X0,LSL #3]

0x410c48 CMP	X25, X3

0x410c4c B.LE	410ee8

0x410c50 CMP	X26, X2

0x410c54 B.GE	411b60

0x410c58 ADD	X8, X8, #2

0x410c5c STR	X8, [X20, X0,LSL #3]

0x410c60 CMP	X4, X2

0x410c64 B.GT	410c70

0x410c68 CMP	X16, X2

0x410c6c B.LE	410ee8

0x410c70 ADD	X8, X8, #1

0x410c74 STR	X8, [X20, X0,LSL #3]

0x410c78 LDR	X10, [X19, X0,LSL #3]

0x410c7c ADD	X10, X10, X8

0x410c80 ADD	X8, X22, X0

0x410c84 LDR	X11, [X9]

0x410c88 ADD	X2, X2, #1

0x410c8c ADD	X10, X11, X10

0x410c90 STR	X10, [X9]

0x410c94 STR	X8, [X27, X0,LSL #3]

0x410c98 LDR	X8, [X19, X0,LSL #3]

0x410c9c LDR	X11, [X20, X0,LSL #3]

0x410ca0 ADD	X10, X8, X11

0x410ca4 STR	X10, [X21, X0,LSL #3]

0x410ca8 CMP	X28, X1

0x410cac B.LE	41164c

0x410cb0 ADD	X0, X0, #1

0x410cb4 ADD	X1, X1, #1

0x410cb8 LDR	X8, [X19, X0,LSL #3]

0x410cbc ADD	X10, X8, #1

0x410cc0 STR	X10, [X19, X0,LSL #3]

0x410cc4 CMP	X12, X23

0x410cc8 B.LE	410f38

0x410ccc ADD	X11, X8, #2

0x410cd0 STR	X11, [X19, X0,LSL #3]

0x410cd4 CMP	X15, X5

0x410cd8 B.GE	4110f4

0x410cdc ADD	X10, X8, #3

0x410ce0 STR	X10, [X19, X0,LSL #3]

0x410ce4 CMP	X26, X2

0x410ce8 B.GE	411120

0x410cec ADD	X10, X8, #4

0x410cf0 STR	X10, [X19, X0,LSL #3]

0x410cf4 CMP	X4, X2

0x410cf8 B.GT	411130

0x410cfc CMP	X24, X1

0x410d00 B.LE	410d10

0x410d04 LDR	X11, [X20, X0,LSL #3]

0x410d08 ADD	X8, X11, #1

0x410d0c STR	X8, [X20, X0,LSL #3]

0x410d10 CMP	X26, X2

0x410d14 B.GE	4110a0

0x410d18 LDR	X11, [X19, X0,LSL #3]

0x410d1c ADD	X8, X11, #1

0x410d20 STR	X8, [X19, X0,LSL #3]

0x410d24 CMP	X6, X1

0x410d28 B.LE	411050

0x410d2c LDR	X8, [X19, X0,LSL #3]

0x410d30 ADD	X10, X8, #1

0x410d34 STR	X10, [X19, X0,LSL #3]

0x410d38 CMP	X7, X3

0x410d3c B.GT	41101c

0x410d40 CMP	X25, X3

0x410d44 B.LE	410d74

0x410d48 LDR	X11, [X20, X0,LSL #3]

0x410d4c CMP	X26, X2

0x410d50 B.GE	410fb0

0x410d54 ADD	X11, X11, #2

0x410d58 STR	X11, [X20, X0,LSL #3]

0x410d5c CMP	X4, X2

0x410d60 B.GT	410d6c

0x410d64 CMP	X16, X2

0x410d68 B.LE	410d74

0x410d74 CMP	X15, X5

0x410d78 B.GE	410fd0

0x410d7c LDR	X11, [X19, X0,LSL #3]

0x410d80 ADD	X10, X11, #1

0x410d84 STR	X10, [X19, X0,LSL #3]

0x410d88 CMP	X26, X2

0x410d8c B.GE	410ffc

0x410d90 ADD	X10, X11, #2

0x410d94 STR	X10, [X19, X0,LSL #3]

0x410d98 CMP	X4, X2

0x410d9c B.GT	41100c

0x410da0 CMP	X24, X1

0x410da4 B.LE	410db4

0x410da8 LDR	X8, [X20, X0,LSL #3]

0x410dac ADD	X11, X8, #1

0x410db0 STR	X11, [X20, X0,LSL #3]

0x410db4 CMP	X26, X2

0x410db8 B.GE	410fbc

0x410dbc LDR	X8, [X19, X0,LSL #3]

0x410dc0 ADD	X11, X8, #1

0x410dc4 STR	X11, [X19, X0,LSL #3]

0x410dc8 CMP	X6, X1

0x410dcc B.LE	410f20

0x410dd0 LDR	X11, [X19, X0,LSL #3]

0x410dd4 ADD	X10, X11, #1

0x410dd8 STR	X10, [X19, X0,LSL #3]

0x410ddc CMP	X7, X3

0x410de0 B.LE	410ef0

0x410de4 LDR	X11, [X19, X0,LSL #3]

0x410de8 ADD	X10, X11, #1

0x410dec STR	X10, [X19, X0,LSL #3]

0x410df0 CMP	X26, X2

0x410df4 B.GE	411080

0x410df8 ADD	X10, X11, #2

0x410dfc STR	X10, [X19, X0,LSL #3]

0x410e00 CMP	X4, X2

0x410e04 B.GT	411090

0x410e08 CMP	X24, X1

0x410e0c B.LE	410e1c

0x410e10 LDR	X8, [X20, X0,LSL #3]

0x410e14 ADD	X11, X8, #1

0x410e18 STR	X11, [X20, X0,LSL #3]

0x410e1c CMP	X14, X13

0x410e20 B.GT	410bcc

0x410e24 LDR	X8, [X20, X0,LSL #3]

0x410e28 CMP	X30, X13

0x410e2c B.LE	410ee8

0x410e30 CMP	X15, X5

0x410e34 B.GE	411a60

0x410e38 CMP	X26, X2

0x410e3c B.GE	411b6c

0x410e40 ADD	X8, X8, #3

0x410e44 STR	X8, [X20, X0,LSL #3]

0x410e48 CMP	X4, X2

0x410e4c B.GT	410e58

0x410e50 CMP	X24, X1

0x410e54 B.LE	410e60

0x410e58 ADD	X8, X8, #1

0x410e5c STR	X8, [X20, X0,LSL #3]

0x410e60 CMP	X26, X2

0x410e64 B.GE	411a58

0x410e68 ADD	X8, X8, #1

0x410e6c STR	X8, [X20, X0,LSL #3]

0x410e70 CMP	X6, X1

0x410e74 B.GT	410e80

0x410e78 CMP	X24, X1

0x410e7c B.LE	410e88

0x410e80 ADD	X8, X8, #1

0x410e84 STR	X8, [X20, X0,LSL #3]

0x410e88 CMP	X7, X3

0x410e8c B.LE	410c48

0x410e90 ADD	X10, X8, #2

0x410e94 CMP	X26, X2

0x410e98 B.LT	410ea8

0x410e9c CMP	X2, #0

0x410ea0 CSINC	X11, X8, X8, #0

0x410ea4 ADD	X10, X11, #1

0x410ea8 ADD	X8, X10, #1

0x410eac STR	X8, [X20, X0,LSL #3]

0x410eb0 LDR	X10, [X19, X0,LSL #3]

0x410eb4 B	410c7c

0x410eb8 LDR	X8, [X19, X0,LSL #3]

0x410ebc ADD	X10, X8, #1

0x410ec0 STR	X10, [X19, X0,LSL #3]

0x410ec4 CMP	X26, X2

0x410ec8 B.GE	4111a4

0x410ecc ADD	X10, X8, #2

0x410ed0 STR	X10, [X19, X0,LSL #3]

0x410ed4 CMP	X4, X2

0x410ed8 B.GT	4111b4

0x410edc LDR	X8, [X20, X0,LSL #3]

0x410ee0 CMP	X24, X1

0x410ee4 B.GT	410c70

0x410ee8 LDR	X10, [X19, X0,LSL #3]

0x410eec B	410c7c

0x410ef0 CMP	X25, X3

0x410ef4 B.LE	410e1c

0x410ef8 LDR	X8, [X20, X0,LSL #3]

0x410efc CMP	X26, X2

0x410f00 B.GE	411a88

0x410f04 ADD	X8, X8, #2

0x410f08 STR	X8, [X20, X0,LSL #3]

0x410f0c CMP	X4, X2

0x410f10 B.GT	410e14

0x410f14 CMP	X16, X2

0x410f18 B.LE	410e1c

0x410f1c B	410e14

0x410f20 CMP	X24, X1

0x410f24 B.LE	410ddc

0x410f28 LDR	X10, [X20, X0,LSL #3]

0x410f2c ADD	X8, X10, #1

0x410f30 STR	X8, [X20, X0,LSL #3]

0x410f34 B	410ddc

0x410f38 CBZ	X12, 410d74

0x410fb0 CBZ	X2, 411b1c

0x410fbc CBZ	X2, 410dc8

0x410fc0 LDR	X11, [X20, X0,LSL #3]

0x410fc4 ADD	X10, X11, #1

0x410fc8 STR	X10, [X20, X0,LSL #3]

0x410fcc B	410dc8

0x410fd0 CBZ	X5, 410db4

0x410fd4 LDR	X8, [X20, X0,LSL #3]

0x410fd8 CMP	X26, X2

0x410fdc B.GE	411b10

0x410fe0 ADD	X8, X8, #2

0x410fe4 STR	X8, [X20, X0,LSL #3]

0x410fe8 CMP	X4, X2

0x410fec B.GT	410dac

0x410ff0 CMP	X16, X2

0x410ff4 B.LE	410db4

0x410ff8 B	410dac

0x410ffc CBZ	X2, 410d98

0x411000 LDR	X8, [X20, X0,LSL #3]

0x411004 ADD	X11, X8, #1

0x411008 STR	X11, [X20, X0,LSL #3]

0x41100c LDR	X10, [X19, X0,LSL #3]

0x411010 ADD	X8, X10, #1

0x411014 STR	X8, [X19, X0,LSL #3]

0x411018 B	410db4

0x41101c LDR	X8, [X19, X0,LSL #3]

0x411020 ADD	X10, X8, #1

0x411024 STR	X10, [X19, X0,LSL #3]

0x411028 CMP	X26, X2

0x41102c B.GE	411184

0x411030 ADD	X10, X8, #2

0x411034 STR	X10, [X19, X0,LSL #3]

0x411038 CMP	X4, X2

0x41103c B.GT	411194

0x411040 CMP	X24, X1

0x411044 B.LE	410d74

0x411050 CMP	X24, X1

0x411054 B.LE	410d38

0x411058 LDR	X10, [X20, X0,LSL #3]

0x41105c ADD	X11, X10, #1

0x411060 STR	X11, [X20, X0,LSL #3]

0x411064 B	410d38

0x411068 CMP	X24, X1

0x41106c B.LE	410c3c

0x411070 LDR	X11, [X20, X0,LSL #3]

0x411074 ADD	X8, X11, #1

0x411078 STR	X8, [X20, X0,LSL #3]

0x41107c B	410c3c

0x411080 CBZ	X2, 410e00

0x411084 LDR	X8, [X20, X0,LSL #3]

0x411088 ADD	X11, X8, #1

0x41108c STR	X11, [X20, X0,LSL #3]

0x411090 LDR	X10, [X19, X0,LSL #3]

0x411094 ADD	X8, X10, #1

0x411098 STR	X8, [X19, X0,LSL #3]

0x41109c B	410e1c

0x4110a0 CBZ	X2, 410d24

0x4110a4 LDR	X8, [X20, X0,LSL #3]

0x4110a8 ADD	X10, X8, #1

0x4110ac STR	X10, [X20, X0,LSL #3]

0x4110b0 B	410d24

0x4110b4 CBZ	X2, 410c28

0x4110b8 LDR	X10, [X20, X0,LSL #3]

0x4110bc ADD	X11, X10, #1

0x4110c0 STR	X11, [X20, X0,LSL #3]

0x4110c4 B	410c28

0x4110c8 CBZ	X5, 410c14

0x4110cc LDR	X10, [X20, X0,LSL #3]

0x4110d0 CMP	X26, X2

0x4110d4 B.GE	411bf0

0x4110d8 ADD	X8, X10, #2

0x4110dc STR	X8, [X20, X0,LSL #3]

0x4110e0 CMP	X4, X2

0x4110e4 B.GT	410c0c

0x4110e8 CMP	X16, X2

0x4110ec B.LE	410c14

0x4110f0 B	410c0c

0x4110f4 CBZ	X5, 410d10

0x4110f8 LDR	X8, [X20, X0,LSL #3]

0x4110fc CMP	X26, X2

0x411100 B.GE	411bd4

0x411104 ADD	X11, X8, #2

0x411108 STR	X11, [X20, X0,LSL #3]

0x41110c CMP	X4, X2

0x411110 B.GT	410d08

0x411114 CMP	X16, X2

0x411118 B.LE	410d10

0x41111c B	410d08

0x411120 CBZ	X2, 410cf4

0x411124 LDR	X11, [X20, X0,LSL #3]

0x411128 ADD	X8, X11, #1

0x41112c STR	X8, [X20, X0,LSL #3]

0x411130 LDR	X10, [X19, X0,LSL #3]

0x411134 ADD	X11, X10, #1

0x411138 STR	X11, [X19, X0,LSL #3]

0x41113c B	410d10

0x411164 CBZ	X2, 410bf8

0x411168 LDR	X8, [X20, X0,LSL #3]

0x41116c ADD	X10, X8, #1

0x411170 STR	X10, [X20, X0,LSL #3]

0x411174 LDR	X11, [X19, X0,LSL #3]

0x411178 ADD	X8, X11, #1

0x41117c STR	X8, [X19, X0,LSL #3]

0x411180 B	410c14

0x411184 CBZ	X2, 411038

0x411188 LDR	X11, [X20, X0,LSL #3]

0x41118c ADD	X8, X11, #1

0x411190 STR	X8, [X20, X0,LSL #3]

0x411194 LDR	X10, [X19, X0,LSL #3]

0x411198 ADD	X11, X10, #1

0x41119c STR	X11, [X19, X0,LSL #3]

0x4111a0 B	410d74

0x4111a4 CBZ	X2, 410ed4

0x4111a8 LDR	X11, [X20, X0,LSL #3]

0x4111ac ADD	X8, X11, #1

0x4111b0 STR	X8, [X20, X0,LSL #3]

0x4111b4 LDR	X11, [X19, X0,LSL #3]

0x4111b8 ADD	X10, X11, #1

0x4111bc STR	X10, [X19, X0,LSL #3]

0x4111c0 LDR	X8, [X20, X0,LSL #3]

0x4111c4 B	410c7c

  (11) 0x4111c8 ORR	X1, XZR, X26

  (11) 0x4111cc ORR	X0, XZR, X17

  (11) 0x4111d0 ORR	X2, XZR, X1

  (11) 0x4111d4 HINT	#0

  (11) 0x4111d8 HINT	#0

  (11) 0x4111dc HINT	#0

    (9) 0x4111e0 ADD	X0, X0, #1

    (9) 0x4111e4 ADD	X1, X1, #1

    (9) 0x4111e8 LDR	X28, [X19, X0,LSL #3]

    (9) 0x4111ec ADD	X8, X28, #1

    (9) 0x4111f0 STR	X8, [X19, X0,LSL #3]

    (9) 0x4111f4 CMP	X12, X23

    (9) 0x4111f8 B.GT	41173c

    (9) 0x4111fc CBZ	X12, 411294

    (9) 0x411200 LDR	X8, [X20, X0,LSL #3]

    (9) 0x411204 CMP	X15, X5

    (9) 0x411208 B.GE	4119fc

    (9) 0x41120c CMP	X26, X2

    (9) 0x411210 B.GE	411b28

    (9) 0x411214 ADD	X8, X8, #3

    (9) 0x411218 STR	X8, [X20, X0,LSL #3]

    (9) 0x41121c CMP	X4, X2

    (9) 0x411220 B.GT	41122c

    (9) 0x411224 CMP	X24, X1

    (9) 0x411228 B.LE	411234

    (9) 0x41122c ADD	X8, X8, #1

    (9) 0x411230 STR	X8, [X20, X0,LSL #3]

    (9) 0x411234 CMP	X26, X2

    (9) 0x411238 B.GE	411a28

    (9) 0x41123c ADD	X8, X8, #1

    (9) 0x411240 STR	X8, [X20, X0,LSL #3]

    (9) 0x411244 CMP	X1, X6

    (9) 0x411248 B.LT	411254

    (9) 0x41124c CMP	X24, X1

    (9) 0x411250 B.LE	41125c

    (9) 0x411254 ADD	X8, X8, #1

    (9) 0x411258 STR	X8, [X20, X0,LSL #3]

    (9) 0x41125c CMP	X7, X3

    (9) 0x411260 B.GT	4119b4

    (9) 0x411264 CMP	X25, X3

    (9) 0x411268 B.LE	411294

    (9) 0x41126c CMP	X26, X2

    (9) 0x411270 B.GE	4117c4

    (9) 0x411274 ADD	X11, X8, #2

    (9) 0x411278 STR	X11, [X20, X0,LSL #3]

    (9) 0x41127c CMP	X4, X2

    (9) 0x411280 B.GT	41128c

    (9) 0x411284 CMP	X16, X2

    (9) 0x411288 B.LE	411294

    (9) 0x41128c ADD	X10, X11, #1

    (9) 0x411290 STR	X10, [X20, X0,LSL #3]

    (9) 0x411294 CMP	X15, X5

    (9) 0x411298 B.GE	4117e4

    (9) 0x41129c LDR	X8, [X19, X0,LSL #3]

    (9) 0x4112a0 ADD	X10, X8, #1

    (9) 0x4112a4 STR	X10, [X19, X0,LSL #3]

    (9) 0x4112a8 CMP	X26, X2

    (9) 0x4112ac B.GE	4118e8

    (9) 0x4112b0 ADD	X8, X8, #2

    (9) 0x4112b4 STR	X8, [X19, X0,LSL #3]

    (9) 0x4112b8 CMP	X4, X2

    (9) 0x4112bc B.GT	411834

    (9) 0x4112c0 CMP	X24, X1

    (9) 0x4112c4 B.LE	4112d4

    (9) 0x4112c8 LDR	X10, [X20, X0,LSL #3]

    (9) 0x4112cc ADD	X28, X10, #1

    (9) 0x4112d0 STR	X28, [X20, X0,LSL #3]

    (9) 0x4112d4 CMP	X26, X2

    (9) 0x4112d8 B.GE	411820

    (9) 0x4112dc LDR	X11, [X19, X0,LSL #3]

    (9) 0x4112e0 ADD	X8, X11, #1

    (9) 0x4112e4 STR	X8, [X19, X0,LSL #3]

    (9) 0x4112e8 CMP	X1, X6

    (9) 0x4112ec B.LT	4117d4

    (9) 0x4112f0 CMP	X24, X1

    (9) 0x4112f4 B.LE	411304

    (9) 0x4112f8 LDR	X10, [X20, X0,LSL #3]

    (9) 0x4112fc ADD	X28, X10, #1

    (9) 0x411300 STR	X28, [X20, X0,LSL #3]

    (9) 0x411304 CMP	X7, X3

    (9) 0x411308 B.GT	411708

    (9) 0x41130c CMP	X25, X3

    (9) 0x411310 B.LE	411340

    (9) 0x411314 LDR	X10, [X20, X0,LSL #3]

    (9) 0x411318 CMP	X26, X2

    (9) 0x41131c B.GE	411af0

    (9) 0x411320 ADD	X11, X10, #2

    (9) 0x411324 STR	X11, [X20, X0,LSL #3]

    (9) 0x411328 CMP	X4, X2

    (9) 0x41132c B.GT	411338

    (9) 0x411330 CMP	X16, X2

    (9) 0x411334 B.LE	411340

    (9) 0x411338 ADD	X8, X11, #1

    (9) 0x41133c STR	X8, [X20, X0,LSL #3]

    (9) 0x411340 CMP	X14, X13

    (9) 0x411344 B.GT	411660

    (9) 0x411348 LDR	X8, [X20, X0,LSL #3]

    (9) 0x41134c CMP	X30, X13

    (9) 0x411350 B.LE	4113d4

    (9) 0x411354 CMP	X15, X5

    (9) 0x411358 B.GE	411a94

    (9) 0x41135c CMP	X26, X2

    (9) 0x411360 B.GE	411ba4

    (9) 0x411364 ADD	X8, X8, #3

    (9) 0x411368 STR	X8, [X20, X0,LSL #3]

    (9) 0x41136c CMP	X4, X2

    (9) 0x411370 B.GT	41137c

    (9) 0x411374 CMP	X24, X1

    (9) 0x411378 B.LE	411384

    (9) 0x41137c ADD	X8, X8, #1

    (9) 0x411380 STR	X8, [X20, X0,LSL #3]

    (9) 0x411384 CMP	X26, X2

    (9) 0x411388 B.GE	411ac0

    (9) 0x41138c ADD	X8, X8, #1

    (9) 0x411390 STR	X8, [X20, X0,LSL #3]

    (9) 0x411394 CMP	X1, X6

    (9) 0x411398 B.LT	4113a4

    (9) 0x41139c CMP	X24, X1

    (9) 0x4113a0 B.LE	4113ac

    (9) 0x4113a4 ADD	X8, X8, #1

    (9) 0x4113a8 STR	X8, [X20, X0,LSL #3]

    (9) 0x4113ac CMP	X7, X3

    (9) 0x4113b0 B.LE	4116dc

    (9) 0x4113b4 CMP	X26, X2

    (9) 0x4113b8 B.GE	411bb4

    (9) 0x4113bc ADD	X8, X8, #2

    (9) 0x4113c0 STR	X8, [X20, X0,LSL #3]

    (9) 0x4113c4 CMP	X24, X1

    (9) 0x4113c8 B.LE	4113d4

    (9) 0x4113cc ADD	X8, X8, #1

    (9) 0x4113d0 STR	X8, [X20, X0,LSL #3]

    (9) 0x4113d4 LDR	X10, [X19, X0,LSL #3]

    (9) 0x4113d8 ADD	X28, X10, X8

    (9) 0x4113dc ADD	X10, X22, X0

    (9) 0x4113e0 LDR	X11, [X9]

    (9) 0x4113e4 ADD	X2, X2, #1

    (9) 0x4113e8 ADD	X8, X11, X28

    (9) 0x4113ec STR	X8, [X9]

    (9) 0x4113f0 STR	X10, [X27, X0,LSL #3]

    (9) 0x4113f4 LDR	X28, [X20, X0,LSL #3]

    (9) 0x4113f8 LDR	X10, [X19, X0,LSL #3]

    (9) 0x4113fc ADD	X11, X28, X10

    (9) 0x411400 STR	X11, [X21, X0,LSL #3]

    (9) 0x411404 CMP	X18, X1

    (9) 0x411408 B.GT	4111e0

  (11) 0x41140c LDR	X0, [SP, #96]

  (11) 0x411410 ADD	X17, X17, X0

    (10) 0x411414 LDR	X1, [SP, #512]

    (10) 0x411418 ADD	X5, X5, #1

    (10) 0x41141c CMP	X1, X3

    (10) 0x411420 B.NE	410ba0

    (10) 0x411424 LDR	X3, [SP, #1736]

    (10) 0x411428 ADD	X12, X12, #1

    (10) 0x41142c ADD	X13, X13, #1

    (10) 0x411430 CMP	X3, X12

    (10) 0x411434 B.NE	410b90

0x41164c CMP	X18, X1

0x411650 B.GT	4111d0

0x411654 LDR	X0, [SP, #96]

0x411658 ADD	X17, X17, X0

0x41165c B	411414

    (9) 0x411660 LDR	X11, [X19, X0,LSL #3]

    (9) 0x411664 ADD	X8, X11, #1

    (9) 0x411668 STR	X8, [X19, X0,LSL #3]

    (9) 0x41166c CMP	X15, X5

    (9) 0x411670 B.GE	41193c

    (9) 0x411674 ADD	X28, X11, #2

    (9) 0x411678 STR	X28, [X19, X0,LSL #3]

    (9) 0x41167c CMP	X26, X2

    (9) 0x411680 B.GE	411a44

    (9) 0x411684 ADD	X10, X11, #3

    (9) 0x411688 STR	X10, [X19, X0,LSL #3]

    (9) 0x41168c CMP	X4, X2

    (9) 0x411690 B.GT	4119a4

    (9) 0x411694 CMP	X24, X1

    (9) 0x411698 B.LE	4116a8

    (9) 0x41169c LDR	X28, [X20, X0,LSL #3]

    (9) 0x4116a0 ADD	X11, X28, #1

    (9) 0x4116a4 STR	X11, [X20, X0,LSL #3]

    (9) 0x4116a8 CMP	X26, X2

    (9) 0x4116ac B.GE	41196c

    (9) 0x4116b0 LDR	X8, [X19, X0,LSL #3]

    (9) 0x4116b4 ADD	X10, X8, #1

    (9) 0x4116b8 STR	X10, [X19, X0,LSL #3]

    (9) 0x4116bc CMP	X1, X6

    (9) 0x4116c0 B.GE	411870

    (9) 0x4116c4 LDR	X8, [X19, X0,LSL #3]

    (9) 0x4116c8 ADD	X10, X8, #1

    (9) 0x4116cc STR	X10, [X19, X0,LSL #3]

    (9) 0x4116d0 CMP	X7, X3

    (9) 0x4116d4 B.GT	411844

    (9) 0x4116d8 LDR	X8, [X20, X0,LSL #3]

    (9) 0x4116dc CMP	X25, X3

    (9) 0x4116e0 B.LE	4113d4

    (9) 0x4116e4 CMP	X26, X2

    (9) 0x4116e8 B.GE	411b50

    (9) 0x4116ec ADD	X8, X8, #2

    (9) 0x4116f0 STR	X8, [X20, X0,LSL #3]

    (9) 0x4116f4 CMP	X4, X2

    (9) 0x4116f8 B.GT	4113cc

    (9) 0x4116fc CMP	X16, X2

    (9) 0x411700 B.GT	4113cc

    (9) 0x411704 B	4113d4

    (9) 0x411708 LDR	X28, [X19, X0,LSL #3]

    (9) 0x41170c ADD	X11, X28, #1

    (9) 0x411710 STR	X11, [X19, X0,LSL #3]

    (9) 0x411714 CMP	X26, X2

    (9) 0x411718 B.GE	411980

    (9) 0x41171c ADD	X28, X28, #2

    (9) 0x411720 STR	X28, [X19, X0,LSL #3]

    (9) 0x411724 CMP	X4, X2

    (9) 0x411728 B.GT	4118d8

    (9) 0x41172c CMP	X24, X1

    (9) 0x411730 B.LE	411340

    (9) 0x411734 LDR	X11, [X20, X0,LSL #3]

    (9) 0x411738 B	411338

    (9) 0x41173c ADD	X11, X28, #2

    (9) 0x411740 STR	X11, [X19, X0,LSL #3]

    (9) 0x411744 CMP	X15, X5

    (9) 0x411748 B.GE	411910

    (9) 0x41174c ADD	X8, X28, #3

    (9) 0x411750 STR	X8, [X19, X0,LSL #3]

    (9) 0x411754 CMP	X26, X2

    (9) 0x411758 B.GE	411a30

    (9) 0x41175c ADD	X10, X28, #4

    (9) 0x411760 STR	X10, [X19, X0,LSL #3]

    (9) 0x411764 CMP	X4, X2

    (9) 0x411768 B.GT	411994

    (9) 0x41176c CMP	X24, X1

    (9) 0x411770 B.LE	411780

    (9) 0x411774 LDR	X8, [X20, X0,LSL #3]

    (9) 0x411778 ADD	X28, X8, #1

    (9) 0x41177c STR	X28, [X20, X0,LSL #3]

    (9) 0x411780 CMP	X26, X2

    (9) 0x411784 B.GE	4118fc

    (9) 0x411788 LDR	X11, [X19, X0,LSL #3]

    (9) 0x41178c ADD	X10, X11, #1

    (9) 0x411790 STR	X10, [X19, X0,LSL #3]

    (9) 0x411794 CMP	X1, X6

    (9) 0x411798 B.GE	411888

    (9) 0x41179c LDR	X11, [X19, X0,LSL #3]

    (9) 0x4117a0 ADD	X10, X11, #1

    (9) 0x4117a4 STR	X10, [X19, X0,LSL #3]

    (9) 0x4117a8 CMP	X7, X3

    (9) 0x4117ac B.GT	4118a4

    (9) 0x4117b0 CMP	X25, X3

    (9) 0x4117b4 B.LE	411294

    (9) 0x4117b8 LDR	X8, [X20, X0,LSL #3]

    (9) 0x4117bc CMP	X26, X2

    (9) 0x4117c0 B.LT	411274

    (9) 0x4117c4 CBNZ	X2, 411274

    (9) 0x4117c8 ADD	X11, X8, #1

    (9) 0x4117cc STR	X11, [X20, X0,LSL #3]

    (9) 0x4117d0 B	41127c

    (9) 0x4117d4 LDR	X11, [X19, X0,LSL #3]

    (9) 0x4117d8 ADD	X8, X11, #1

    (9) 0x4117dc STR	X8, [X19, X0,LSL #3]

    (9) 0x4117e0 B	411304

    (9) 0x4117e4 CBZ	X5, 4112d4

    (9) 0x4117e8 LDR	X11, [X20, X0,LSL #3]

    (9) 0x4117ec CMP	X26, X2

    (9) 0x4117f0 B.GE	411b00

    (9) 0x4117f4 ADD	X10, X11, #2

    (9) 0x4117f8 STR	X10, [X20, X0,LSL #3]

    (9) 0x4117fc CMP	X4, X2

    (9) 0x411800 B.GT	4112cc

    (9) 0x411804 CMP	X16, X2

    (9) 0x411808 B.GT	4112cc

    (9) 0x41180c CMP	X26, X2

    (9) 0x411810 B.LT	4112dc

    (9) 0x411814 HINT	#0

    (9) 0x411818 HINT	#0

    (9) 0x41181c HINT	#0

    (9) 0x411820 CBZ	X2, 4112e8

    (9) 0x411824 LDR	X10, [X20, X0,LSL #3]

    (9) 0x411828 ADD	X28, X10, #1

    (9) 0x41182c STR	X28, [X20, X0,LSL #3]

    (9) 0x411830 B	4112e8

    (9) 0x411834 LDR	X11, [X19, X0,LSL #3]

    (9) 0x411838 ADD	X8, X11, #1

    (9) 0x41183c STR	X8, [X19, X0,LSL #3]

    (9) 0x411840 B	4112d4

    (9) 0x411844 LDR	X28, [X19, X0,LSL #3]

    (9) 0x411848 ADD	X11, X28, #1

    (9) 0x41184c STR	X11, [X19, X0,LSL #3]

    (9) 0x411850 CMP	X26, X2

    (9) 0x411854 B.GE	411ac8

    (9) 0x411858 ADD	X28, X28, #2

    (9) 0x41185c STR	X28, [X19, X0,LSL #3]

    (9) 0x411860 CMP	X4, X2

    (9) 0x411864 B.GT	4119e8

    (9) 0x411868 LDR	X8, [X20, X0,LSL #3]

    (9) 0x41186c B	4113c4

    (9) 0x411870 CMP	X24, X1

    (9) 0x411874 B.LE	4116d0

    (9) 0x411878 LDR	X28, [X20, X0,LSL #3]

    (9) 0x41187c ADD	X11, X28, #1

    (9) 0x411880 STR	X11, [X20, X0,LSL #3]

    (9) 0x411884 B	4116d0

    (9) 0x411888 CMP	X24, X1

    (9) 0x41188c B.LE	4117a8

    (9) 0x411890 LDR	X8, [X20, X0,LSL #3]

    (9) 0x411894 ADD	X28, X8, #1

    (9) 0x411898 STR	X28, [X20, X0,LSL #3]

    (9) 0x41189c CMP	X7, X3

    (9) 0x4118a0 B.LE	4117b0

    (9) 0x4118a4 LDR	X28, [X19, X0,LSL #3]

    (9) 0x4118a8 ADD	X11, X28, #1

    (9) 0x4118ac STR	X11, [X19, X0,LSL #3]

    (9) 0x4118b0 CMP	X26, X2

    (9) 0x4118b4 B.GE	411adc

    (9) 0x4118b8 ADD	X28, X28, #2

    (9) 0x4118bc STR	X28, [X19, X0,LSL #3]

    (9) 0x4118c0 CMP	X4, X2

    (9) 0x4118c4 B.GT	4119d8

    (9) 0x4118c8 CMP	X24, X1

    (9) 0x4118cc B.LE	411294

    (9) 0x4118d0 LDR	X11, [X20, X0,LSL #3]

    (9) 0x4118d4 B	41128c

    (9) 0x4118d8 LDR	X10, [X19, X0,LSL #3]

    (9) 0x4118dc ADD	X28, X10, #1

    (9) 0x4118e0 STR	X28, [X19, X0,LSL #3]

    (9) 0x4118e4 B	411340

    (9) 0x4118e8 CBZ	X2, 4112b8

    (9) 0x4118ec LDR	X28, [X20, X0,LSL #3]

    (9) 0x4118f0 ADD	X11, X28, #1

    (9) 0x4118f4 STR	X11, [X20, X0,LSL #3]

    (9) 0x4118f8 B	4112b8

    (9) 0x4118fc CBZ	X2, 411794

    (9) 0x411900 LDR	X8, [X20, X0,LSL #3]

    (9) 0x411904 ADD	X28, X8, #1

    (9) 0x411908 STR	X28, [X20, X0,LSL #3]

    (9) 0x41190c B	411794

    (9) 0x411910 CBZ	X5, 411780

    (9) 0x411914 LDR	X10, [X20, X0,LSL #3]

    (9) 0x411918 CMP	X26, X2

    (9) 0x41191c B.GE	411be0

    (9) 0x411920 ADD	X8, X10, #2

    (9) 0x411924 STR	X8, [X20, X0,LSL #3]

    (9) 0x411928 CMP	X4, X2

    (9) 0x41192c B.GT	411778

    (9) 0x411930 CMP	X16, X2

    (9) 0x411934 B.LE	411780

    (9) 0x411938 B	411778

    (9) 0x41193c CBZ	X5, 4116a8

    (9) 0x411940 LDR	X10, [X20, X0,LSL #3]

    (9) 0x411944 CMP	X26, X2

    (9) 0x411948 B.GE	411bc4

    (9) 0x41194c ADD	X28, X10, #2

    (9) 0x411950 STR	X28, [X20, X0,LSL #3]

    (9) 0x411954 CMP	X4, X2

    (9) 0x411958 B.GT	4116a0

    (9) 0x41195c CMP	X16, X2

    (9) 0x411960 B.GT	4116a0

    (9) 0x411964 CMP	X26, X2

    (9) 0x411968 B.LT	4116b0

    (9) 0x41196c CBZ	X2, 4116bc

    (9) 0x411970 LDR	X28, [X20, X0,LSL #3]

    (9) 0x411974 ADD	X11, X28, #1

    (9) 0x411978 STR	X11, [X20, X0,LSL #3]

    (9) 0x41197c B	4116bc

    (9) 0x411980 CBZ	X2, 411724

    (9) 0x411984 LDR	X8, [X20, X0,LSL #3]

    (9) 0x411988 ADD	X10, X8, #1

    (9) 0x41198c STR	X10, [X20, X0,LSL #3]

    (9) 0x411990 B	411724

    (9) 0x411994 LDR	X11, [X19, X0,LSL #3]

    (9) 0x411998 ADD	X10, X11, #1

    (9) 0x41199c STR	X10, [X19, X0,LSL #3]

    (9) 0x4119a0 B	411780

    (9) 0x4119a4 LDR	X8, [X19, X0,LSL #3]

    (9) 0x4119a8 ADD	X10, X8, #1

    (9) 0x4119ac STR	X10, [X19, X0,LSL #3]

    (9) 0x4119b0 B	4116a8

    (9) 0x4119b4 CMP	X26, X2

    (9) 0x4119b8 B.GE	411b84

    (9) 0x4119bc ADD	X11, X8, #2

    (9) 0x4119c0 STR	X11, [X20, X0,LSL #3]

    (9) 0x4119c4 CMP	X4, X2

    (9) 0x4119c8 B.GT	41128c

    (9) 0x4119cc CMP	X24, X1

    (9) 0x4119d0 B.LE	411294

    (9) 0x4119d4 B	41128c

    (9) 0x4119d8 LDR	X8, [X19, X0,LSL #3]

    (9) 0x4119dc ADD	X28, X8, #1

    (9) 0x4119e0 STR	X28, [X19, X0,LSL #3]

    (9) 0x4119e4 B	411294

    (9) 0x4119e8 LDR	X11, [X19, X0,LSL #3]

    (9) 0x4119ec ADD	X10, X11, #1

    (9) 0x4119f0 STR	X10, [X19, X0,LSL #3]

    (9) 0x4119f4 LDR	X8, [X20, X0,LSL #3]

    (9) 0x4119f8 B	4113d8

    (9) 0x4119fc CBZ	X5, 41122c

    (9) 0x411a00 CMP	X26, X2

    (9) 0x411a04 B.GE	411c24

    (9) 0x411a08 ADD	X8, X8, #3

    (9) 0x411a0c STR	X8, [X20, X0,LSL #3]

    (9) 0x411a10 CMP	X4, X2

    (9) 0x411a14 B.GT	41122c

    (9) 0x411a18 CMP	X16, X2

    (9) 0x411a1c B.GT	41122c

    (9) 0x411a20 CMP	X26, X2

    (9) 0x411a24 B.LT	41123c

    (9) 0x411a28 CBNZ	X2, 41123c

    (9) 0x411a2c B	411244

    (9) 0x411a30 CBZ	X2, 411764

    (9) 0x411a34 LDR	X28, [X20, X0,LSL #3]

    (9) 0x411a38 ADD	X11, X28, #1

    (9) 0x411a3c STR	X11, [X20, X0,LSL #3]

    (9) 0x411a40 B	411764

    (9) 0x411a44 CBZ	X2, 41168c

    (9) 0x411a48 LDR	X11, [X20, X0,LSL #3]

    (9) 0x411a4c ADD	X8, X11, #1

    (9) 0x411a50 STR	X8, [X20, X0,LSL #3]

    (9) 0x411a54 B	41168c

0x411a58 CBNZ	X2, 410e68

0x411a5c B	410e70

0x411a60 CBZ	X5, 410e58

0x411a64 CMP	X26, X2

0x411a68 B.GE	411c50

0x411a6c ADD	X8, X8, #3

0x411a70 STR	X8, [X20, X0,LSL #3]

0x411a74 CMP	X4, X2

0x411a78 B.GT	410e58

0x411a7c CMP	X16, X2

0x411a80 B.LE	410e60

0x411a84 B	410e58

0x411a88 CBZ	X2, 411bfc

0x411a8c ADD	X8, X8, #2

0x411a90 B	410e14

    (9) 0x411a94 CBZ	X5, 41137c

    (9) 0x411a98 CMP	X26, X2

    (9) 0x411a9c B.GE	411c40

    (9) 0x411aa0 ADD	X8, X8, #3

    (9) 0x411aa4 STR	X8, [X20, X0,LSL #3]

    (9) 0x411aa8 CMP	X4, X2

    (9) 0x411aac B.GT	41137c

    (9) 0x411ab0 CMP	X16, X2

    (9) 0x411ab4 B.GT	41137c

    (9) 0x411ab8 CMP	X26, X2

    (9) 0x411abc B.LT	41138c

    (9) 0x411ac0 CBNZ	X2, 41138c

    (9) 0x411ac4 B	411394

    (9) 0x411ac8 CBZ	X2, 411860

    (9) 0x411acc LDR	X8, [X20, X0,LSL #3]

    (9) 0x411ad0 ADD	X10, X8, #1

    (9) 0x411ad4 STR	X10, [X20, X0,LSL #3]

    (9) 0x411ad8 B	411860

    (9) 0x411adc CBZ	X2, 4118c0

    (9) 0x411ae0 LDR	X10, [X20, X0,LSL #3]

    (9) 0x411ae4 ADD	X8, X10, #1

    (9) 0x411ae8 STR	X8, [X20, X0,LSL #3]

    (9) 0x411aec B	4118c0

    (9) 0x411af0 CBNZ	X2, 411320

    (9) 0x411af4 ADD	X11, X10, #1

    (9) 0x411af8 STR	X11, [X20, X0,LSL #3]

    (9) 0x411afc B	411328

    (9) 0x411b00 CBNZ	X2, 4117f4

    (9) 0x411b04 ADD	X10, X11, #1

    (9) 0x411b08 STR	X10, [X20, X0,LSL #3]

    (9) 0x411b0c B	4117fc

0x411b10 CBZ	X2, 411c08

0x411b14 ADD	X8, X8, #2

0x411b18 B	410dac

0x411b1c ADD	X11, X11, #1

0x411b20 STR	X11, [X20, X0,LSL #3]

0x411b24 B	410d5c

    (9) 0x411b28 CBNZ	X2, 411214

    (9) 0x411b2c ADD	X8, X8, #2

    (9) 0x411b30 STR	X8, [X20, X0,LSL #3]

    (9) 0x411b34 B	41121c

    (9) 0x411b50 CBNZ	X2, 4116ec

    (9) 0x411b54 ADD	X8, X8, #1

    (9) 0x411b58 STR	X8, [X20, X0,LSL #3]

    (9) 0x411b5c B	4116f4

0x411b60 CBZ	X2, 411c34

0x411b64 ADD	X8, X8, #2

0x411b68 B	410c70

0x411b6c CBZ	X2, 411b78

0x411b70 ADD	X8, X8, #3

0x411b74 B	410e58

0x411b78 ADD	X8, X8, #2

0x411b7c STR	X8, [X20, X0,LSL #3]

0x411b80 B	410e48

    (9) 0x411b84 CBNZ	X2, 4119bc

    (9) 0x411b88 ADD	X11, X8, #1

    (9) 0x411b8c STR	X11, [X20, X0,LSL #3]

    (9) 0x411b90 B	4119c4

    (9) 0x411ba4 CBNZ	X2, 411364

    (9) 0x411ba8 ADD	X8, X8, #2

    (9) 0x411bac STR	X8, [X20, X0,LSL #3]

    (9) 0x411bb0 B	41136c

    (9) 0x411bb4 CBNZ	X2, 4113bc

    (9) 0x411bb8 ADD	X8, X8, #1

    (9) 0x411bbc STR	X8, [X20, X0,LSL #3]

    (9) 0x411bc0 B	4113c4

    (9) 0x411bc4 CBNZ	X2, 41194c

    (9) 0x411bc8 ADD	X28, X10, #1

    (9) 0x411bcc STR	X28, [X20, X0,LSL #3]

    (9) 0x411bd0 B	411954

0x411bd4 CBZ	X2, 411c60

0x411bd8 ADD	X11, X8, #2

0x411bdc B	410d08

    (9) 0x411be0 CBNZ	X2, 411920

    (9) 0x411be4 ADD	X8, X10, #1

    (9) 0x411be8 STR	X8, [X20, X0,LSL #3]

    (9) 0x411bec B	411928

0x411bf0 CBZ	X2, 411c6c

0x411bf4 ADD	X8, X10, #2

0x411bf8 B	410c0c

0x411bfc ADD	X8, X8, #1

0x411c00 STR	X8, [X20, X0,LSL #3]

0x411c04 B	410f0c

0x411c08 ADD	X8, X8, #1

0x411c0c STR	X8, [X20, X0,LSL #3]

0x411c10 B	410fe8

    (9) 0x411c24 CBNZ	X2, 411a08

    (9) 0x411c28 ADD	X8, X8, #2

    (9) 0x411c2c STR	X8, [X20, X0,LSL #3]

    (9) 0x411c30 B	411a10

0x411c34 ADD	X8, X8, #1

0x411c38 STR	X8, [X20, X0,LSL #3]

0x411c3c B	410c60

    (9) 0x411c40 CBNZ	X2, 411aa0

    (9) 0x411c44 ADD	X8, X8, #2

    (9) 0x411c48 STR	X8, [X20, X0,LSL #3]

    (9) 0x411c4c B	411aa8

0x411c50 CBNZ	X2, 411b70

0x411c54 ADD	X8, X8, #2

0x411c58 STR	X8, [X20, X0,LSL #3]

0x411c5c B	411a74

0x411c60 ADD	X11, X8, #1

0x411c64 STR	X11, [X20, X0,LSL #3]

0x411c68 B	41110c

0x411c6c ADD	X8, X10, #1

0x411c70 STR	X8, [X20, X0,LSL #3]

0x411c74 B	4110e0

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/test/amg.c: 794 - 1409

--------------------------------------------------------------------------------

794:     for (iz = iz_start;  iz < iz_end; iz++)

795:     {

796:       for (iy = iy_start;  iy < iy_end; iy++)

797:       {

798:          for (ix = ix_start; ix < ix_end; ix++)

799:          {

800:             cnt++;

801:             o_cnt++;

802:             diag_i[cnt]++;

803:             if (iz > nz*pz)

804:             {

805:                diag_i[cnt]++;

806:                if (iy > ny*py)

807:                {

808:                   diag_i[cnt]++;

809:       	          if (ix > nx*px)

810:       	          {

811:       	             diag_i[cnt]++;

812:       	          }

813:       	          else

814:       	          {

815:       	             if (ix)

816:       		        offd_i[o_cnt]++;

817:       	          }

818:       	          if (ix < nx*(px+1)-1)

819:       	          {

820:       	             diag_i[cnt]++;

821:       	          }

822:       	          else

823:       	          {

824:       	             if (ix+1 < nx_global)

825:       		        offd_i[o_cnt]++;

826:       	          }

827:                }

828:                else

829:                {

830:                   if (iy)

831:                   {

832:                      offd_i[o_cnt]++;

833:       	             if (ix > nx*px)

834:       	             {

835:       	                offd_i[o_cnt]++;

836:       	             }

837:       	             else if (ix)

838:       	             {

839:       	                offd_i[o_cnt]++;

840:       	             }

841:       	             if (ix < nx*(px+1)-1)

842:       	             {

843:       	                offd_i[o_cnt]++;

844:       	             }

845:       	             else if (ix < nx_global-1)

[...]

851:                if (ix > nx*px)

852:                   diag_i[cnt]++;

853:                else

854:                {

855:                   if (ix)

856:                   {

857:                      offd_i[o_cnt]++;

858:                   }

859:                }

860:                if (ix+1 < nx*(px+1))

861:                   diag_i[cnt]++;

862:                else

863:                {

864:                   if (ix+1 < nx_global)

865:                   {

866:                      offd_i[o_cnt]++;

867:                   }

868:                }

869:                if (iy+1 < ny*(py+1))

870:                {

871:                   diag_i[cnt]++;

872:       	          if (ix > nx*px)

873:       	          {

874:       	             diag_i[cnt]++;

875:       	          }

876:       	          else

877:       	          {

878:       	             if (ix)

879:       		        offd_i[o_cnt]++;

880:       	          }

881:       	          if (ix < nx*(px+1)-1)

882:       	          {

883:       	             diag_i[cnt]++;

884:       	          }

885:       	          else

886:       	          {

887:       	             if (ix+1 < nx_global)

888:       		        offd_i[o_cnt]++;

889:       	          }

890:                }

891:                else

892:                {

893:                   if (iy+1 < ny_global)

894:                   {

895:                      offd_i[o_cnt]++;

896:       	             if (ix > nx*px)

897:       	             {

898:       	                offd_i[o_cnt]++;

899:       	             }

900:       	             else if (ix)

901:       	             {

902:       	                offd_i[o_cnt]++;

903:       	             }

904:       	             if (ix < nx*(px+1)-1)

905:       	             {

906:       	                offd_i[o_cnt]++;

907:       	             }

908:       	             else if (ix < nx_global-1)

[...]

917:                if (iz)

918: 	       {

919: 		  offd_i[o_cnt]++;

920:                   if (iy > ny*py)

921:                   {

922:                      offd_i[o_cnt]++;

923:       	             if (ix > nx*px)

924:       	             {

925:       	                offd_i[o_cnt]++;

926:       	             }

927:       	             else

928:       	             {

929:       	                if (ix)

930:       	   	        offd_i[o_cnt]++;

931:       	             }

932:       	             if (ix < nx*(px+1)-1)

933:       	             {

934:       	                offd_i[o_cnt]++;

935:       	             }

936:       	             else

937:       	             {

938:       	                if (ix+1 < nx_global)

[...]

944:                      if (iy)

945:                      {

946:                         offd_i[o_cnt]++;

947:       	                if (ix > nx*px)

948:       	                {

949:       	                   offd_i[o_cnt]++;

950:       	                }

951:       	                else if (ix)

952:       	                {

953:       	                   offd_i[o_cnt]++;

954:       	                }

955:       	                if (ix < nx*(px+1)-1)

956:       	                {

957:       	                   offd_i[o_cnt]++;

958:       	                }

959:       	                else if (ix < nx_global-1)

[...]

965:                   if (ix > nx*px)

966:                      offd_i[o_cnt]++;

967:                   else

968:                   {

969:                      if (ix)

970:                      {

971:                         offd_i[o_cnt]++;

972:                      }

973:                   }

974:                   if (ix+1 < nx*(px+1))

975:                      offd_i[o_cnt]++;

976:                   else

977:                   {

978:                      if (ix+1 < nx_global)

979:                      {

980:                         offd_i[o_cnt]++;

981:                      }

982:                   }

983:                   if (iy+1 < ny*(py+1))

984:                   {

985:                      offd_i[o_cnt]++;

986:       	             if (ix > nx*px)

987:       	             {

988:       	                offd_i[o_cnt]++;

989:       	             }

990:       	             else

991:       	             {

992:       	                if (ix)

993:       	   	           offd_i[o_cnt]++;

994:       	             }

995:       	             if (ix < nx*(px+1)-1)

[...]

1001:       	                if (ix+1 < nx_global)

[...]

1007:                      if (iy+1 < ny_global)

[...]

1030:             if (iy > ny*py)

1031:             {

1032:                diag_i[cnt]++;

1033:    	       if (ix > nx*px)

1034:    	       {

1035:    	          diag_i[cnt]++;

1036:    	       }

1037:    	       else

1038:    	       {

1039:    	          if (ix)

1040:    		     offd_i[o_cnt]++;

1041:    	       }

1042:    	       if (ix < nx*(px+1)-1)

1043:    	       {

1044:    	          diag_i[cnt]++;

1045:    	       }

1046:    	       else

1047:    	       {

1048:    	          if (ix+1 < nx_global)

1049:    		     offd_i[o_cnt]++;

1050:    	       }

1051:             }

1052:             else

1053:             {

1054:                if (iy)

1055:                {

1056:                   offd_i[o_cnt]++;

1057:    	          if (ix > nx*px)

1058:    	          {

1059:    	             offd_i[o_cnt]++;

1060:    	          }

1061:    	          else if (ix)

1062:    	          {

1063:    	             offd_i[o_cnt]++;

1064:    	          }

1065:    	          if (ix < nx*(px+1)-1)

1066:    	          {

1067:    	             offd_i[o_cnt]++;

1068:    	          }

1069:    	          else if (ix < nx_global-1)

[...]

1075:             if (ix > nx*px)

1076:                diag_i[cnt]++;

1077:             else

1078:             {

1079:                if (ix)

1080:                {

1081:                   offd_i[o_cnt]++;

1082:                }

1083:             }

1084:             if (ix+1 < nx*(px+1))

1085:                diag_i[cnt]++;

1086:             else

1087:             {

1088:                if (ix+1 < nx_global)

1089:                {

1090:                   offd_i[o_cnt]++;

1091:                }

1092:             }

1093:             if (iy+1 < ny*(py+1))

1094:             {

1095:                diag_i[cnt]++;

1096:    	       if (ix > nx*px)

1097:    	       {

1098:    	          diag_i[cnt]++;

1099:    	       }

1100:    	       else

1101:    	       {

1102:    	          if (ix)

1103:    		     offd_i[o_cnt]++;

1104:    	       }

1105:    	       if (ix < nx*(px+1)-1)

1106:    	       {

1107:    	          diag_i[cnt]++;

1108:    	       }

1109:    	       else

1110:    	       {

1111:    	          if (ix+1 < nx_global)

1112:    		     offd_i[o_cnt]++;

1113:    	       }

1114:             }

1115:             else

1116:             {

1117:                if (iy+1 < ny_global)

1118:                {

1119:                   offd_i[o_cnt]++;

1120:    	          if (ix > nx*px)

1121:    	          {

1122:    	             offd_i[o_cnt]++;

1123:    	          }

1124:    	          else if (ix)

1125:    	          {

1126:    	             offd_i[o_cnt]++;

1127:    	          }

1128:    	          if (ix < nx*(px+1)-1)

1129:    	          {

1130:    	             offd_i[o_cnt]++;

1131:    	          }

1132:    	          else if (ix < nx_global-1)

[...]

1138:             if (iz+1 < nz*(pz+1))

1139:             {

1140:                diag_i[cnt]++;

1141:                if (iy > ny*py)

1142:                {

1143:                   diag_i[cnt]++;

1144:       	          if (ix > nx*px)

1145:       	          {

1146:       	             diag_i[cnt]++;

1147:       	          }

1148:       	          else

1149:       	          {

1150:       	             if (ix)

1151:       		        offd_i[o_cnt]++;

1152:       	          }

1153:       	          if (ix < nx*(px+1)-1)

1154:       	          {

1155:       	             diag_i[cnt]++;

1156:       	          }

1157:       	          else

1158:       	          {

1159:       	             if (ix+1 < nx_global)

1160:       		        offd_i[o_cnt]++;

1161:       	          }

1162:                }

1163:                else

1164:                {

1165:                   if (iy)

1166:                   {

1167:                      offd_i[o_cnt]++;

1168:       	             if (ix > nx*px)

1169:       	             {

1170:       	                offd_i[o_cnt]++;

1171:       	             }

1172:       	             else if (ix)

1173:       	             {

1174:       	                offd_i[o_cnt]++;

1175:       	             }

1176:       	             if (ix < nx*(px+1)-1)

1177:       	             {

1178:       	                offd_i[o_cnt]++;

1179:       	             }

1180:       	             else if (ix < nx_global-1)

[...]

1186:                if (ix > nx*px)

1187:                   diag_i[cnt]++;

1188:                else

1189:                {

1190:                   if (ix)

1191:                   {

1192:                      offd_i[o_cnt]++;

1193:                   }

1194:                }

1195:                if (ix+1 < nx*(px+1))

1196:                   diag_i[cnt]++;

1197:                else

1198:                {

1199:                   if (ix+1 < nx_global)

1200:                   {

1201:                      offd_i[o_cnt]++;

1202:                   }

1203:                }

1204:                if (iy+1 < ny*(py+1))

1205:                {

1206:                   diag_i[cnt]++;

1207:       	          if (ix > nx*px)

1208:       	          {

1209:       	             diag_i[cnt]++;

1210:       	          }

1211:       	          else

1212:       	          {

1213:       	             if (ix)

1214:       		        offd_i[o_cnt]++;

1215:       	          }

1216:       	          if (ix < nx*(px+1)-1)

1217:       	          {

1218:       	             diag_i[cnt]++;

1219:       	          }

1220:       	          else

1221:       	          {

1222:       	             if (ix+1 < nx_global)

1223:       		        offd_i[o_cnt]++;

1224:       	          }

1225:                }

1226:                else

1227:                {

1228:                   if (iy+1 < ny_global)

1229:                   {

1230:                      offd_i[o_cnt]++;

1231:       	             if (ix > nx*px)

1232:       	             {

1233:       	                offd_i[o_cnt]++;

1234:       	             }

1235:       	             else if (ix)

1236:       	             {

1237:       	                offd_i[o_cnt]++;

1238:       	             }

1239:       	             if (ix < nx*(px+1)-1)

1240:       	             {

1241:       	                offd_i[o_cnt]++;

1242:       	             }

1243:       	             else if (ix < nx_global-1)

[...]

1252:                if (iz+1 < nz_global)

1253: 	       {

1254: 		  offd_i[o_cnt]++;

1255:                   if (iy > ny*py)

1256:                   {

1257:                      offd_i[o_cnt]++;

1258:       	             if (ix > nx*px)

1259:       	             {

1260:       	                offd_i[o_cnt]++;

1261:       	             }

1262:       	             else

1263:       	             {

1264:       	                if (ix)

1265:       	   	        offd_i[o_cnt]++;

1266:       	             }

1267:       	             if (ix < nx*(px+1)-1)

1268:       	             {

1269:       	                offd_i[o_cnt]++;

1270:       	             }

1271:       	             else

1272:       	             {

1273:       	                if (ix+1 < nx_global)

[...]

1279:                      if (iy)

1280:                      {

1281:                         offd_i[o_cnt]++;

1282:       	                if (ix > nx*px)

1283:       	                {

1284:       	                   offd_i[o_cnt]++;

1285:       	                }

1286:       	                else if (ix)

1287:       	                {

1288:       	                   offd_i[o_cnt]++;

1289:       	                }

1290:       	                if (ix < nx*(px+1)-1)

1291:       	                {

1292:       	                   offd_i[o_cnt]++;

1293:       	                }

1294:       	                else if (ix < nx_global-1)

[...]

1300:                   if (ix > nx*px)

1301:                      offd_i[o_cnt]++;

1302:                   else

1303:                   {

1304:                      if (ix)

1305:                      {

1306:                         offd_i[o_cnt]++;

1307:                      }

1308:                   }

1309:                   if (ix+1 < nx*(px+1))

1310:                      offd_i[o_cnt]++;

1311:                   else

1312:                   {

1313:                      if (ix+1 < nx_global)

1314:                      {

1315:                         offd_i[o_cnt]++;

1316:                      }

1317:                   }

1318:                   if (iy+1 < ny*(py+1))

1319:                   {

1320:                      offd_i[o_cnt]++;

1321:       	             if (ix > nx*px)

1322:       	             {

1323:       	                offd_i[o_cnt]++;

1324:       	             }

1325:       	             else

1326:       	             {

1327:       	                if (ix)

1328:       	   	           offd_i[o_cnt]++;

1329:       	             }

1330:       	             if (ix < nx*(px+1)-1)

1331:       	             {

1332:       	                offd_i[o_cnt]++;

[...]

1365:             nnz[my_thread] += diag_i[cnt]+offd_i[o_cnt];

1366:             row_nums[cnt] = row_index+cnt;

1367:             num_cols[cnt] = diag_i[cnt]+offd_i[o_cnt];

[...]

1409:             data[cnt++] = value[0];

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.28
Bottlenecks	P0, P1,
Function	BuildIJLaplacian27pt._omp_fn.0
Source	amg.c:798-811,amg.c:815-820,amg.c:824-825,amg.c:830-841,amg.c:845-845,amg.c:851-852,amg.c:855-857,amg.c:860-861,amg.c:864-866,amg.c:869-874,amg.c:878-883,amg.c:887-887,amg.c:893-900,amg.c:904-904,amg.c:908-908,amg.c:917-917,amg.c:969-969,amg.c:1030-1035,amg.c:1039-1044,amg.c:1048-1049,amg.c:1054-1065,amg.c:1069-1069,amg.c:1075-1076,amg.c:1079-1081,amg.c:1084-1085,amg.c:1088-1090,amg.c:1093-1098,amg.c:1102-1107,amg.c:1111-1112,amg.c:1117-1128,amg.c:1132-1132,amg.c:1138-1146,amg.c:1150-1155,amg.c:1159-1160,amg.c:1165-1176,amg.c:1180-1180,amg.c:1186-1187,amg.c:1190-1192,amg.c:1195-1196,amg.c:1199-1201,amg.c:1204-1209,amg.c:1213-1218,amg.c:1222-1223,amg.c:1228-1239,amg.c:1243-1243,amg.c:1252-1260,amg.c:1264-1267,amg.c:1273-1273,amg.c:1279-1286,amg.c:1290-1290,amg.c:1294-1294,amg.c:1300-1301,amg.c:1304-1304,amg.c:1309-1310,amg.c:1313-1313,amg.c:1318-1318,amg.c:1321-1323,amg.c:1328-1328,amg.c:1332-1332,amg.c:1365-1367
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	65.00
CQA cycles if no scalar integer	65.00
CQA cycles if FP arith vectorized	65.00
CQA cycles if fully vectorized	16.25
Front-end cycles	50.63
DIV/SQRT cycles	65.00
P0 cycles	65.00
P1 cycles	39.50
P2 cycles	39.50
P3 cycles	39.50
P4 cycles	39.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	39.17
P10 cycles	38.83
P11 cycles	39.00
P12 cycles	33.50
P13 cycles	33.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	405.00
Nb uops	405.00
Nb loads	NA
Nb stores	67.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.40
Bytes prefetched	0.00
Bytes loaded	400.00
Bytes stored	536.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.28
Bottlenecks	P0, P1,
Function	BuildIJLaplacian27pt._omp_fn.0
Source	amg.c:798-811,amg.c:815-820,amg.c:824-825,amg.c:830-841,amg.c:845-845,amg.c:851-852,amg.c:855-857,amg.c:860-861,amg.c:864-866,amg.c:869-874,amg.c:878-883,amg.c:887-887,amg.c:893-900,amg.c:904-904,amg.c:908-908,amg.c:917-917,amg.c:969-969,amg.c:1030-1035,amg.c:1039-1044,amg.c:1048-1049,amg.c:1054-1065,amg.c:1069-1069,amg.c:1075-1076,amg.c:1079-1081,amg.c:1084-1085,amg.c:1088-1090,amg.c:1093-1098,amg.c:1102-1107,amg.c:1111-1112,amg.c:1117-1128,amg.c:1132-1132,amg.c:1138-1146,amg.c:1150-1155,amg.c:1159-1160,amg.c:1165-1176,amg.c:1180-1180,amg.c:1186-1187,amg.c:1190-1192,amg.c:1195-1196,amg.c:1199-1201,amg.c:1204-1209,amg.c:1213-1218,amg.c:1222-1223,amg.c:1228-1239,amg.c:1243-1243,amg.c:1252-1260,amg.c:1264-1267,amg.c:1273-1273,amg.c:1279-1286,amg.c:1290-1290,amg.c:1294-1294,amg.c:1300-1301,amg.c:1304-1304,amg.c:1309-1310,amg.c:1313-1313,amg.c:1318-1318,amg.c:1321-1323,amg.c:1328-1328,amg.c:1332-1332,amg.c:1365-1367
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	65.00
CQA cycles if no scalar integer	65.00
CQA cycles if FP arith vectorized	65.00
CQA cycles if fully vectorized	16.25
Front-end cycles	50.63
DIV/SQRT cycles	65.00
P0 cycles	65.00
P1 cycles	39.50
P2 cycles	39.50
P3 cycles	39.50
P4 cycles	39.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	39.17
P10 cycles	38.83
P11 cycles	39.00
P12 cycles	33.50
P13 cycles	33.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	405.00
Nb uops	405.00
Nb loads	NA
Nb stores	67.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.40
Bytes prefetched	0.00
Bytes loaded	400.00
Bytes stored	536.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	BuildIJLaplacian27pt._omp_fn.0
Source file and lines	amg.c:794-1409
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/test/amg.c:794-845,851-908,917-938,944-959,965-995,1001,1007,1030-1069,1075-1132,1138-1180,1186-1243,1252-1273,1279-1294,1300-1332,1365-1367,1409.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/test/amg.c:798-811,815-820,824-825,830-841,845,851-852,855-857,860-861,864-866,869-874,878-883,887,893-900,904,908,917,969,1030-1035,1039-1044,1048-1049,1054-1065,1069,1075-1076,1079-1081,1084-1085,1088-1090,1093-1098,1102-1107,1111-1112,1117-1128,1132,1138-1146,1150-1155,1159-1160,1165-1176,1180,1186-1187,1190-1192,1195-1196,1199-1201,1204-1209,1213-1218,1222-1223,1228-1239,1243,1252-1260,1264-1267,1273,1279-1286,1290,1294,1300-1301,1304,1309-1310,1313,1318,1321-1323,1328,1332,1365-1367.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 65.00 to 16.25 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 400 bytes. The binary loop is storing 536 bytes.

General properties

nb instructions	405
loop length	1620
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

50.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	65.00	65.00	39.50	39.50	39.50	39.50	0.00	0.00	0.00	0.00	39.17	38.83	39.00	33.50	33.50
cycles	65.00	65.00	39.50	39.50	39.50	39.50	0.00	0.00	0.00	0.00	39.17	38.83	39.00	33.50	33.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	50.63
Overall L1	65.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 65.00 cycles. At this rate:

6% of peak load performance is reached (6.15 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (8.25 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 410d74

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
CMP X18, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
ORR X2, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CSEL X28, X18, X4, #13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X1, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X0, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 410cb0 <BuildIJLaplacian27pt._omp_fn.0+0x290>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X15, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4110c8 <BuildIJLaplacian27pt._omp_fn.0+0x6a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X11, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 411164 <BuildIJLaplacian27pt._omp_fn.0+0x744>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X11, X8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 411174 <BuildIJLaplacian27pt._omp_fn.0+0x754>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X24, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410c14 <BuildIJLaplacian27pt._omp_fn.0+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4110b4 <BuildIJLaplacian27pt._omp_fn.0+0x694>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X6, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 411068 <BuildIJLaplacian27pt._omp_fn.0+0x648>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X7, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 410eb8 <BuildIJLaplacian27pt._omp_fn.0+0x498>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X25, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410ee8 <BuildIJLaplacian27pt._omp_fn.0+0x4c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 411b60 <BuildIJLaplacian27pt._omp_fn.0+0x1140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 410c70 <BuildIJLaplacian27pt._omp_fn.0+0x250>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X16, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410ee8 <BuildIJLaplacian27pt._omp_fn.0+0x4c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X8, X22, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X11, [X9]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X10, X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X9]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [X27, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X8, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X28, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 41164c <BuildIJLaplacian27pt._omp_fn.0+0xc2c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X8, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X12, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410f38 <BuildIJLaplacian27pt._omp_fn.0+0x518>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X11, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X15, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4110f4 <BuildIJLaplacian27pt._omp_fn.0+0x6d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 411120 <BuildIJLaplacian27pt._omp_fn.0+0x700>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 411130 <BuildIJLaplacian27pt._omp_fn.0+0x710>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X24, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410d10 <BuildIJLaplacian27pt._omp_fn.0+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4110a0 <BuildIJLaplacian27pt._omp_fn.0+0x680>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X6, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 411050 <BuildIJLaplacian27pt._omp_fn.0+0x630>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X7, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 41101c <BuildIJLaplacian27pt._omp_fn.0+0x5fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X25, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410d74 <BuildIJLaplacian27pt._omp_fn.0+0x354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 410fb0 <BuildIJLaplacian27pt._omp_fn.0+0x590>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X11, X11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 410d6c <BuildIJLaplacian27pt._omp_fn.0+0x34c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X16, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410d74 <BuildIJLaplacian27pt._omp_fn.0+0x354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 410fd0 <BuildIJLaplacian27pt._omp_fn.0+0x5b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 410ffc <BuildIJLaplacian27pt._omp_fn.0+0x5dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 41100c <BuildIJLaplacian27pt._omp_fn.0+0x5ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X24, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410db4 <BuildIJLaplacian27pt._omp_fn.0+0x394>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 410fbc <BuildIJLaplacian27pt._omp_fn.0+0x59c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X6, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410f20 <BuildIJLaplacian27pt._omp_fn.0+0x500>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X7, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410ef0 <BuildIJLaplacian27pt._omp_fn.0+0x4d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 411080 <BuildIJLaplacian27pt._omp_fn.0+0x660>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 411090 <BuildIJLaplacian27pt._omp_fn.0+0x670>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X24, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410e1c <BuildIJLaplacian27pt._omp_fn.0+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X14, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 410bcc <BuildIJLaplacian27pt._omp_fn.0+0x1ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X30, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410ee8 <BuildIJLaplacian27pt._omp_fn.0+0x4c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 411a60 <BuildIJLaplacian27pt._omp_fn.0+0x1040>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 411b6c <BuildIJLaplacian27pt._omp_fn.0+0x114c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 410e58 <BuildIJLaplacian27pt._omp_fn.0+0x438>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X24, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410e60 <BuildIJLaplacian27pt._omp_fn.0+0x440>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 411a58 <BuildIJLaplacian27pt._omp_fn.0+0x1038>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X6, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 410e80 <BuildIJLaplacian27pt._omp_fn.0+0x460>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X24, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410e88 <BuildIJLaplacian27pt._omp_fn.0+0x468>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X7, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410c48 <BuildIJLaplacian27pt._omp_fn.0+0x228>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 410ea8 <BuildIJLaplacian27pt._omp_fn.0+0x488>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
CSINC X11, X8, X8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X10, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X8, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 410c7c <BuildIJLaplacian27pt._omp_fn.0+0x25c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4111a4 <BuildIJLaplacian27pt._omp_fn.0+0x784>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 4111b4 <BuildIJLaplacian27pt._omp_fn.0+0x794>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X24, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 410c70 <BuildIJLaplacian27pt._omp_fn.0+0x250>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 410c7c <BuildIJLaplacian27pt._omp_fn.0+0x25c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X25, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410e1c <BuildIJLaplacian27pt._omp_fn.0+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 411a88 <BuildIJLaplacian27pt._omp_fn.0+0x1068>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 410e14 <BuildIJLaplacian27pt._omp_fn.0+0x3f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X16, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410e1c <BuildIJLaplacian27pt._omp_fn.0+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
B 410e14 <BuildIJLaplacian27pt._omp_fn.0+0x3f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X24, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410ddc <BuildIJLaplacian27pt._omp_fn.0+0x3bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 410ddc <BuildIJLaplacian27pt._omp_fn.0+0x3bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X12, 410d74 <BuildIJLaplacian27pt._omp_fn.0+0x354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X2, 411b1c <BuildIJLaplacian27pt._omp_fn.0+0x10fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X2, 410dc8 <BuildIJLaplacian27pt._omp_fn.0+0x3a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 410dc8 <BuildIJLaplacian27pt._omp_fn.0+0x3a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X5, 410db4 <BuildIJLaplacian27pt._omp_fn.0+0x394>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 411b10 <BuildIJLaplacian27pt._omp_fn.0+0x10f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 410dac <BuildIJLaplacian27pt._omp_fn.0+0x38c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X16, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410db4 <BuildIJLaplacian27pt._omp_fn.0+0x394>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
B 410dac <BuildIJLaplacian27pt._omp_fn.0+0x38c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X2, 410d98 <BuildIJLaplacian27pt._omp_fn.0+0x378>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 410db4 <BuildIJLaplacian27pt._omp_fn.0+0x394>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 411184 <BuildIJLaplacian27pt._omp_fn.0+0x764>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 411194 <BuildIJLaplacian27pt._omp_fn.0+0x774>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X24, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410d74 <BuildIJLaplacian27pt._omp_fn.0+0x354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X24, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410d38 <BuildIJLaplacian27pt._omp_fn.0+0x318>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 410d38 <BuildIJLaplacian27pt._omp_fn.0+0x318>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X24, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410c3c <BuildIJLaplacian27pt._omp_fn.0+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 410c3c <BuildIJLaplacian27pt._omp_fn.0+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X2, 410e00 <BuildIJLaplacian27pt._omp_fn.0+0x3e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 410e1c <BuildIJLaplacian27pt._omp_fn.0+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X2, 410d24 <BuildIJLaplacian27pt._omp_fn.0+0x304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 410d24 <BuildIJLaplacian27pt._omp_fn.0+0x304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X2, 410c28 <BuildIJLaplacian27pt._omp_fn.0+0x208>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 410c28 <BuildIJLaplacian27pt._omp_fn.0+0x208>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X5, 410c14 <BuildIJLaplacian27pt._omp_fn.0+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 411bf0 <BuildIJLaplacian27pt._omp_fn.0+0x11d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 410c0c <BuildIJLaplacian27pt._omp_fn.0+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X16, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410c14 <BuildIJLaplacian27pt._omp_fn.0+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
B 410c0c <BuildIJLaplacian27pt._omp_fn.0+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X5, 410d10 <BuildIJLaplacian27pt._omp_fn.0+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 411bd4 <BuildIJLaplacian27pt._omp_fn.0+0x11b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X11, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 410d08 <BuildIJLaplacian27pt._omp_fn.0+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X16, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410d10 <BuildIJLaplacian27pt._omp_fn.0+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
B 410d08 <BuildIJLaplacian27pt._omp_fn.0+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X2, 410cf4 <BuildIJLaplacian27pt._omp_fn.0+0x2d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 410d10 <BuildIJLaplacian27pt._omp_fn.0+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X2, 410bf8 <BuildIJLaplacian27pt._omp_fn.0+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X11, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 410c14 <BuildIJLaplacian27pt._omp_fn.0+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X2, 411038 <BuildIJLaplacian27pt._omp_fn.0+0x618>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 410d74 <BuildIJLaplacian27pt._omp_fn.0+0x354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X2, 410ed4 <BuildIJLaplacian27pt._omp_fn.0+0x4b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X11, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 410c7c <BuildIJLaplacian27pt._omp_fn.0+0x25c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X18, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 4111d0 <BuildIJLaplacian27pt._omp_fn.0+0x7b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X17, X17, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 411414 <BuildIJLaplacian27pt._omp_fn.0+0x9f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBNZ X2, 410e68 <BuildIJLaplacian27pt._omp_fn.0+0x448>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
B 410e70 <BuildIJLaplacian27pt._omp_fn.0+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X5, 410e58 <BuildIJLaplacian27pt._omp_fn.0+0x438>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 411c50 <BuildIJLaplacian27pt._omp_fn.0+0x1230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 410e58 <BuildIJLaplacian27pt._omp_fn.0+0x438>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X16, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410e60 <BuildIJLaplacian27pt._omp_fn.0+0x440>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
B 410e58 <BuildIJLaplacian27pt._omp_fn.0+0x438>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X2, 411bfc <BuildIJLaplacian27pt._omp_fn.0+0x11dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 410e14 <BuildIJLaplacian27pt._omp_fn.0+0x3f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X2, 411c08 <BuildIJLaplacian27pt._omp_fn.0+0x11e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 410dac <BuildIJLaplacian27pt._omp_fn.0+0x38c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 410d5c <BuildIJLaplacian27pt._omp_fn.0+0x33c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X2, 411c34 <BuildIJLaplacian27pt._omp_fn.0+0x1214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 410c70 <BuildIJLaplacian27pt._omp_fn.0+0x250>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X2, 411b78 <BuildIJLaplacian27pt._omp_fn.0+0x1158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 410e58 <BuildIJLaplacian27pt._omp_fn.0+0x438>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 410e48 <BuildIJLaplacian27pt._omp_fn.0+0x428>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X2, 411c60 <BuildIJLaplacian27pt._omp_fn.0+0x1240>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X11, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 410d08 <BuildIJLaplacian27pt._omp_fn.0+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X2, 411c6c <BuildIJLaplacian27pt._omp_fn.0+0x124c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 410c0c <BuildIJLaplacian27pt._omp_fn.0+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 410f0c <BuildIJLaplacian27pt._omp_fn.0+0x4ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 410fe8 <BuildIJLaplacian27pt._omp_fn.0+0x5c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 410c60 <BuildIJLaplacian27pt._omp_fn.0+0x240>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBNZ X2, 411b70 <BuildIJLaplacian27pt._omp_fn.0+0x1150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 411a74 <BuildIJLaplacian27pt._omp_fn.0+0x1054>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X11, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 41110c <BuildIJLaplacian27pt._omp_fn.0+0x6ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4110e0 <BuildIJLaplacian27pt._omp_fn.0+0x6c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	BuildIJLaplacian27pt._omp_fn.0
Source file and lines	amg.c:794-1409
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 400 bytes. The binary loop is storing 536 bytes.

General properties

nb instructions	405
loop length	1620
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

50.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	65.00	65.00	39.50	39.50	39.50	39.50	0.00	0.00	0.00	0.00	39.17	38.83	39.00	33.50	33.50
cycles	65.00	65.00	39.50	39.50	39.50	39.50	0.00	0.00	0.00	0.00	39.17	38.83	39.00	33.50	33.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	50.63
Overall L1	65.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 65.00 cycles. At this rate:

6% of peak load performance is reached (6.15 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (8.25 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 410d74

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
CMP X18, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
ORR X2, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CSEL X28, X18, X4, #13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X1, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X0, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 410cb0 <BuildIJLaplacian27pt._omp_fn.0+0x290>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X15, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4110c8 <BuildIJLaplacian27pt._omp_fn.0+0x6a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X11, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 411164 <BuildIJLaplacian27pt._omp_fn.0+0x744>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X11, X8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 411174 <BuildIJLaplacian27pt._omp_fn.0+0x754>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X24, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410c14 <BuildIJLaplacian27pt._omp_fn.0+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4110b4 <BuildIJLaplacian27pt._omp_fn.0+0x694>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X6, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 411068 <BuildIJLaplacian27pt._omp_fn.0+0x648>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X7, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 410eb8 <BuildIJLaplacian27pt._omp_fn.0+0x498>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X25, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410ee8 <BuildIJLaplacian27pt._omp_fn.0+0x4c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 411b60 <BuildIJLaplacian27pt._omp_fn.0+0x1140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 410c70 <BuildIJLaplacian27pt._omp_fn.0+0x250>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X16, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410ee8 <BuildIJLaplacian27pt._omp_fn.0+0x4c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X8, X22, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X11, [X9]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X10, X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X9]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [X27, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X8, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X28, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 41164c <BuildIJLaplacian27pt._omp_fn.0+0xc2c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X8, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X12, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410f38 <BuildIJLaplacian27pt._omp_fn.0+0x518>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X11, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X15, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4110f4 <BuildIJLaplacian27pt._omp_fn.0+0x6d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 411120 <BuildIJLaplacian27pt._omp_fn.0+0x700>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 411130 <BuildIJLaplacian27pt._omp_fn.0+0x710>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X24, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410d10 <BuildIJLaplacian27pt._omp_fn.0+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4110a0 <BuildIJLaplacian27pt._omp_fn.0+0x680>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X6, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 411050 <BuildIJLaplacian27pt._omp_fn.0+0x630>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X7, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 41101c <BuildIJLaplacian27pt._omp_fn.0+0x5fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X25, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410d74 <BuildIJLaplacian27pt._omp_fn.0+0x354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 410fb0 <BuildIJLaplacian27pt._omp_fn.0+0x590>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X11, X11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 410d6c <BuildIJLaplacian27pt._omp_fn.0+0x34c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X16, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410d74 <BuildIJLaplacian27pt._omp_fn.0+0x354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 410fd0 <BuildIJLaplacian27pt._omp_fn.0+0x5b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 410ffc <BuildIJLaplacian27pt._omp_fn.0+0x5dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 41100c <BuildIJLaplacian27pt._omp_fn.0+0x5ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X24, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410db4 <BuildIJLaplacian27pt._omp_fn.0+0x394>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 410fbc <BuildIJLaplacian27pt._omp_fn.0+0x59c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X6, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410f20 <BuildIJLaplacian27pt._omp_fn.0+0x500>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X7, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410ef0 <BuildIJLaplacian27pt._omp_fn.0+0x4d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 411080 <BuildIJLaplacian27pt._omp_fn.0+0x660>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 411090 <BuildIJLaplacian27pt._omp_fn.0+0x670>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X24, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410e1c <BuildIJLaplacian27pt._omp_fn.0+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X14, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 410bcc <BuildIJLaplacian27pt._omp_fn.0+0x1ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X30, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410ee8 <BuildIJLaplacian27pt._omp_fn.0+0x4c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 411a60 <BuildIJLaplacian27pt._omp_fn.0+0x1040>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 411b6c <BuildIJLaplacian27pt._omp_fn.0+0x114c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 410e58 <BuildIJLaplacian27pt._omp_fn.0+0x438>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X24, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410e60 <BuildIJLaplacian27pt._omp_fn.0+0x440>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 411a58 <BuildIJLaplacian27pt._omp_fn.0+0x1038>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X6, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 410e80 <BuildIJLaplacian27pt._omp_fn.0+0x460>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X24, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410e88 <BuildIJLaplacian27pt._omp_fn.0+0x468>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X7, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410c48 <BuildIJLaplacian27pt._omp_fn.0+0x228>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 410ea8 <BuildIJLaplacian27pt._omp_fn.0+0x488>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
CSINC X11, X8, X8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X10, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X8, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 410c7c <BuildIJLaplacian27pt._omp_fn.0+0x25c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4111a4 <BuildIJLaplacian27pt._omp_fn.0+0x784>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 4111b4 <BuildIJLaplacian27pt._omp_fn.0+0x794>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X24, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 410c70 <BuildIJLaplacian27pt._omp_fn.0+0x250>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 410c7c <BuildIJLaplacian27pt._omp_fn.0+0x25c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X25, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410e1c <BuildIJLaplacian27pt._omp_fn.0+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 411a88 <BuildIJLaplacian27pt._omp_fn.0+0x1068>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 410e14 <BuildIJLaplacian27pt._omp_fn.0+0x3f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X16, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410e1c <BuildIJLaplacian27pt._omp_fn.0+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
B 410e14 <BuildIJLaplacian27pt._omp_fn.0+0x3f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X24, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410ddc <BuildIJLaplacian27pt._omp_fn.0+0x3bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 410ddc <BuildIJLaplacian27pt._omp_fn.0+0x3bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X12, 410d74 <BuildIJLaplacian27pt._omp_fn.0+0x354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X2, 411b1c <BuildIJLaplacian27pt._omp_fn.0+0x10fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X2, 410dc8 <BuildIJLaplacian27pt._omp_fn.0+0x3a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 410dc8 <BuildIJLaplacian27pt._omp_fn.0+0x3a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X5, 410db4 <BuildIJLaplacian27pt._omp_fn.0+0x394>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 411b10 <BuildIJLaplacian27pt._omp_fn.0+0x10f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 410dac <BuildIJLaplacian27pt._omp_fn.0+0x38c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X16, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410db4 <BuildIJLaplacian27pt._omp_fn.0+0x394>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
B 410dac <BuildIJLaplacian27pt._omp_fn.0+0x38c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X2, 410d98 <BuildIJLaplacian27pt._omp_fn.0+0x378>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 410db4 <BuildIJLaplacian27pt._omp_fn.0+0x394>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 411184 <BuildIJLaplacian27pt._omp_fn.0+0x764>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 411194 <BuildIJLaplacian27pt._omp_fn.0+0x774>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X24, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410d74 <BuildIJLaplacian27pt._omp_fn.0+0x354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X24, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410d38 <BuildIJLaplacian27pt._omp_fn.0+0x318>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 410d38 <BuildIJLaplacian27pt._omp_fn.0+0x318>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X24, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410c3c <BuildIJLaplacian27pt._omp_fn.0+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 410c3c <BuildIJLaplacian27pt._omp_fn.0+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X2, 410e00 <BuildIJLaplacian27pt._omp_fn.0+0x3e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 410e1c <BuildIJLaplacian27pt._omp_fn.0+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X2, 410d24 <BuildIJLaplacian27pt._omp_fn.0+0x304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 410d24 <BuildIJLaplacian27pt._omp_fn.0+0x304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X2, 410c28 <BuildIJLaplacian27pt._omp_fn.0+0x208>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 410c28 <BuildIJLaplacian27pt._omp_fn.0+0x208>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X5, 410c14 <BuildIJLaplacian27pt._omp_fn.0+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 411bf0 <BuildIJLaplacian27pt._omp_fn.0+0x11d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 410c0c <BuildIJLaplacian27pt._omp_fn.0+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X16, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410c14 <BuildIJLaplacian27pt._omp_fn.0+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
B 410c0c <BuildIJLaplacian27pt._omp_fn.0+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X5, 410d10 <BuildIJLaplacian27pt._omp_fn.0+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 411bd4 <BuildIJLaplacian27pt._omp_fn.0+0x11b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X11, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 410d08 <BuildIJLaplacian27pt._omp_fn.0+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X16, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410d10 <BuildIJLaplacian27pt._omp_fn.0+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
B 410d08 <BuildIJLaplacian27pt._omp_fn.0+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X2, 410cf4 <BuildIJLaplacian27pt._omp_fn.0+0x2d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 410d10 <BuildIJLaplacian27pt._omp_fn.0+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X2, 410bf8 <BuildIJLaplacian27pt._omp_fn.0+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X11, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 410c14 <BuildIJLaplacian27pt._omp_fn.0+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X2, 411038 <BuildIJLaplacian27pt._omp_fn.0+0x618>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 410d74 <BuildIJLaplacian27pt._omp_fn.0+0x354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X2, 410ed4 <BuildIJLaplacian27pt._omp_fn.0+0x4b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X11, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 410c7c <BuildIJLaplacian27pt._omp_fn.0+0x25c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X18, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 4111d0 <BuildIJLaplacian27pt._omp_fn.0+0x7b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X17, X17, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 411414 <BuildIJLaplacian27pt._omp_fn.0+0x9f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBNZ X2, 410e68 <BuildIJLaplacian27pt._omp_fn.0+0x448>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
B 410e70 <BuildIJLaplacian27pt._omp_fn.0+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X5, 410e58 <BuildIJLaplacian27pt._omp_fn.0+0x438>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 411c50 <BuildIJLaplacian27pt._omp_fn.0+0x1230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 410e58 <BuildIJLaplacian27pt._omp_fn.0+0x438>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X16, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 410e60 <BuildIJLaplacian27pt._omp_fn.0+0x440>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
B 410e58 <BuildIJLaplacian27pt._omp_fn.0+0x438>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X2, 411bfc <BuildIJLaplacian27pt._omp_fn.0+0x11dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 410e14 <BuildIJLaplacian27pt._omp_fn.0+0x3f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X2, 411c08 <BuildIJLaplacian27pt._omp_fn.0+0x11e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 410dac <BuildIJLaplacian27pt._omp_fn.0+0x38c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 410d5c <BuildIJLaplacian27pt._omp_fn.0+0x33c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X2, 411c34 <BuildIJLaplacian27pt._omp_fn.0+0x1214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 410c70 <BuildIJLaplacian27pt._omp_fn.0+0x250>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X2, 411b78 <BuildIJLaplacian27pt._omp_fn.0+0x1158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 410e58 <BuildIJLaplacian27pt._omp_fn.0+0x438>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 410e48 <BuildIJLaplacian27pt._omp_fn.0+0x428>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X2, 411c60 <BuildIJLaplacian27pt._omp_fn.0+0x1240>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X11, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 410d08 <BuildIJLaplacian27pt._omp_fn.0+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ X2, 411c6c <BuildIJLaplacian27pt._omp_fn.0+0x124c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 410c0c <BuildIJLaplacian27pt._omp_fn.0+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 410f0c <BuildIJLaplacian27pt._omp_fn.0+0x4ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 410fe8 <BuildIJLaplacian27pt._omp_fn.0+0x5c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 410c60 <BuildIJLaplacian27pt._omp_fn.0+0x240>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBNZ X2, 411b70 <BuildIJLaplacian27pt._omp_fn.0+0x1150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 411a74 <BuildIJLaplacian27pt._omp_fn.0+0x1054>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X11, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 41110c <BuildIJLaplacian27pt._omp_fn.0+0x6ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X8, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X8, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4110e0 <BuildIJLaplacian27pt._omp_fn.0+0x6c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code